JPS58212253A - Control circuit of picture data memory - Google Patents

Abstract

PURPOSE:To read out directly any small unit of a picture as a variable length code data and to improve the storage efficiency, by referencing automatically a head address of a memory area where a code data of each small unit of the picture is stored. CONSTITUTION:A data write circuit 100 separates a data into an assembly of code data of each small unit of a picture and that of head addresses of a memory area where the code data of small units of the picture are stored when writing a picture data PD in the memory 26, by using a counter 21 counting in every small unit of picture of code data and a counter 22 counting the length of the code data in the unit of a word length of the memory 26. Further, a data readout circuit 200 references automatically the head address of the memory area where the code data of each small unit of picture is stored when reading out the picture data from a memory 35.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image data memory control circuit for encoding and storing image signals.

Digital image data obtained by sampling an image signal on the time axis and quantizing it on the amplitude axis has a very large amount of data. For example, in the case of a facsimile signal, if an A4 size image is sampled at a density of 8 dots/mm in the main scanning direction and 8 scanning lines/mm in the sub-scanning direction and quantized into black and white binary, it will be approximately 4 x 10' bits. become. Also, if a television image is sampled at 10.7 MH2 and quantized at 8 bits, the ITV frame will be approximately 2.87xlO.
〇When storing a large number of images in a large capacity memory such as a magnetic disk or optical disk, or temporarily storing images in a semiconductor memory for image transmission, image data such as the above may be stored as is. Memorizing information is inefficient and costly. Therefore, a method is often used in which image data is compressed by encoding and then stored.

FIG. 1 is a block diagram showing the general configuration of such an image storage device. In the figure, 01 is an image input section, 0 is an encoding section, f13 is a storage section, υ is a decoding section, 051 is an image display section, and αQ is a control section.

The image input unit αD is specifically a scanner, a TV camera, etc., and converts the image into an electrical signal. In the encoding section a, the digitized image signal is subjected to encoding processing such as run-length encoding and DPCM, and is then data-compressed. Compressed image data is stored in the storage unit 031 and read out as needed.

In the decoding section αe, the data read from the storage section (13) is restored to an image signal, and this is displayed as an image on an image display section 051 such as a CRT monitor or printer.The control section αe controls the operation of each section mentioned above. This is the part to control.

In the above-mentioned image storage device, images are stored in a data compressed form, and the image signals can only be reproduced and retrieved without going through a decoding section. This causes inconvenience when attempting not only to simply store and reproduce images, but also to perform processing such as enlarging, reducing, moving, or cutting out parts of images. Especially the storage part (
If the correspondence between the hardware structure of 131 and the structure of compressed image data is not simple, it is difficult to directly read the data of a part of the image to be processed, which significantly reduces processing efficiency. make it worse For example, the memory section 0 has a structure in which 8 bits (1 byte) are accessed in parallel like a normal computer memory, and compression obtained by run-length encoding the kore+C7 axis signal for each scanning line. When data is stored sequentially without any gaps, the data for each scanning line is of non-fixed length, so the data for one scanning line generally starts from a bit in the middle of a byte with a certain address, and then It continues until the bit in the middle of a byte with a somewhat (also not constant) large address.In this case, even if there is an identification code at the beginning of each scan line data indicating the start of the scan line, the data of any scan line can be It is not possible to read the image data individually (for example, the data of the n-th scanning line) from the storage unit αJ, but the image data is read from the beginning and the data of the scanning line before the data of the target scanning line is read out by the decoding unit (141). After reading the data, you will get scan line data to be processed.This situation is not limited to cases where encoding is done in units of scan lines, but generally when an image is divided into multiple rectangular blocks, etc. The same applies to the case where each small unit divided into partial images is encoded.

The present invention has been made in view of the problems of the conventional devices as described above. When loading image data into memory, a set of encoded data for each image unit and a counter that counts the length of encoded data in memory word length units are used. A set of starting addresses of the memory area where the unit code data is stored is separated into a set of starting addresses of the memory area where the code data of each unit is stored, and when reading the image data from the memory, the starting address of the memory area where the code data of each image small unit is stored. An image data memory control circuit that can efficiently store encoded data of compressed images by automatically referencing data, and can directly read data of a part of the image as necessary. is intended to provide.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of the data writing circuit (100) of the image data memory control circuit according to the present invention.
121) in the figure, @ is the first. Second counter * (231
゜ (goods) is the first. Second data selection circuit (selector).

(C) is an OR circuit, and @ is a memory. The memory (A) has a parallel structure, and information from several bits of parallel input terminals DI is transferred to the address input terminal AD by the write pulse WR.
It is written to the address specified by R. Address inputs are also given in parallel from several bits to more than ten bits. The image data PD to be written to the memory (26) is also written to the memory (26).
It is a parallel detector having the same number of bits as the word length (b), that is, the number of parallel bits, and is applied to one input terminal l of the selector. The address in the memory (to) where the image data PD is written is given by the output Q of the counter (c), which is applied to one input terminal 11 of the selector (c). Further, a write pulse PC is applied to the terminal WR of the memory (to) via the Ok circuit (to). Usually, the selector (c) and (
Since the input on the terminal Il side reaches terminal 0 due to the control input SEL at the output of the counter (
2) is written to the address in memory (2) specified by the output Q of 2).

Also, the write pulse PC is the clock input CK of the counter.
is also applied and counts up, so the write address becomes larger sequentially for each write pulse PC.

In addition, initial address data PA is connected to the input terminal of the counter @ so that the storage start position of image data can be preset by a pulse PS, and writing can be performed from an arbitrary address.

On the other hand, a pulse LC generated for each small unit of an image such as a scanning line or a rectangular block is applied to a clock input GK of the counter (21), and its counting output Q is applied to the other input terminal I2 of the selector (c). added to.

Further, the count output Q of the counter @ is applied to the other input terminal I2 of the selector. When the pulse LC is applied when the control input SEL of the selector and the control input SEL becomes the opposite logical value, the output Q of the counter Qυ
becomes the address manual ADR of the memory ■, the output Q of the counter @ becomes the data input DI, and furthermore, the pulse LC passes through the Ok circuit (to) and becomes the write pulse Wk, and the address data is written to the memory (to). It will be done. A μ
- If the address data, that is, the output of the counter @, is larger than the word length of the memory (to), that is, the number of parallel input bits, it is necessary to write the address data in several parts. The convolution start position of such address data in the memory (a) can be set arbitrarily by preset data input LA to the counter (211) and pulse LS, and every time the convolution pulse LC is applied, The write address gradually increases.

According to the data writing circuit configured as described above, the code data of each partial image obtained by dividing the image into small units is stored in the memory (A).
In addition to being able to sequentially convolve the code data of each small unit of image, the data at the start address of the code data of each small unit of image can also be sequentially written into the memory (to), and the writing position of the address data can be set separately from the code data. It is possible to specify.

FIG. 3 is a block diagram showing the configuration of the data readout circuit (200) of the image data memory control circuit according to the present invention. In the figure, (31) and (32) are the third. A fourth counter, (33) is a third data selection circuit (ie, selector), (34) is an OR circuit, and C35) is a memory. The memory c35) has a parallel structure, and the read pulse RD
As a result, the memory contents at the address specified by the signal applied to the address input terminal ADH are read out to the output terminal Do as several bits of parallel data, and the output data PD
becomes. Address input to the memory (35) is performed using the selector (
33), one input I of the selector 03) is connected to the output Q of the counter c32), and the other input I2 is connected to the output Q of the counter C31), and the selection control signal Either one of the two inputs Iis"t is selected by SEL. If the pulse PC is applied when the output of the counter (32) is selected as the address input of the memory (35), the pulse PC will be The read pulse RD passes through the OR circuit (34), and the data output PD is obtained from the address.At the same time, the counter (2) is counted up and the address power is updated.Similarly, the counter (31) is counted up. When the pulse LC is applied while the output is selected as the address input, the data output PD is obtained from the address specified by the output of the counter (31), and at the same time the counter (31) is counted up. (31) The input data LA is preset by the Nihahals LS, and the output data PD of the memory (35) is preset by the pulse LC in the counter C32).

Memo from the memory read circuit with the above configuration as described above! When the code data and address data of each small image unit are stored separately in j(35), the image data is read out by the following procedure. First, the counter (3
1), the address in the memory (35) in which the start address of the small image unit to be read is stored is applied as data LA, and reset to 1 by pulse LS. Further, a selection control signal SEL is provided so that the output of the selector c33) becomes the input on the 12 side, that is, the output of the counter (31), and the pulse LC is input. This allows memory (35
) is first read out from the start address of the small image unit to be read out, and then the counter (32) is reset.

Next, the selection control signal SEL of the selector (33) is applied so that the input on the 11 side is output, and the pulse PC is input.

Then, the output of the counter (32) specifies the memo 1'l.
, C35), the first code data of the image small unit to be read out is read out as data PD. At the same time, the counter (32) is counted up, so after the reading is completed, the address of the next code data will be outputted. Therefore, if the pulse PC is input in the same way from now on, This means that the code data is read out sequentially. Further, when the reading of one image small unit is completed and the subsequent image small unit is to be read out, the selection control signal SEL of the selector (33) is temporarily changed to I! If the input on the side is outputted and the pulse LC is input, the start address of the code data of the next small unit of image will be on the counter (
32), so the selection control signal SEL is given again so that the input on the Il side is output, and the pulse PC
You can enter them one after another.

In the above explanation, if it is necessary to input the address to be given to the memory (35) and the pulse LC must also be input the same number of times, it will not be possible.

□ FIGS. 4 and 5 are a circuit diagram and a timing chart showing an embodiment of the data write circuit (100) of the image data memory control circuit according to the present invention.

In this embodiment, the word length of the memory is 8 bits, the address data length is 16 bits, the input code data is serial, and the image subunit is a line, that is, a scanning line.

In FIG. 4, counters (41) to (42), selectors (43) to (44), OR circuit (45), and memory (46) correspond to each block (21) in FIG.
This corresponds to (a) to (a). Also, (47) is a shift register, (48) is a 3-bit binary counter, (
49) to (50) are flip-flops, (51) is O
R circuit, C52) to (53) are AND circuits, (54)
is a NOT circuit. In FIG. 4, symbols are attached to the main signals on the circuit, and their timing relationships are shown in FIG.

Also, FIG. 6 shows that this data writing circuit allows memory IJ
An example of the format of image data written in (46) is shown.

In the circuit diagram of FIG. 4, in the initial state, the counter (41) is set to the starting address xL of the address data area of the memory (46).
A (-0000a; H here indicates hexadecimal data) is the control unit (set pulse LS from the top (
(not shown) and a counter (4
2) contains the start address PA (-129
0u) is preset by a pulse ps (not shown), and flip-flops (49) and (50) are reset. First, one pulse LC is input, and at this rising edge, the output q of the flip-flop (50)
changes from 1"0" to 1f1''.

On the other hand, the least significant digit output LSB of the counter (41) is a pulse L
It remains at 110 without changing until C falls.

In this state, the selector (43) selects the inputs H1 and Ll, and the output of the counter (41) becomes the 16-bit address input ADR of the memory (46), while the selector (44) selects the input It, and the counter The upper 8 bits of the output of (42) become input data to memory (46). At this time, the pulse LC is applied to the memory (46) as the write pulse WR via the OR circuit (45), so data 12'' is written to address 0OOOH of the memory (46).The next pulse LC is the write pulse. When applied as WR, the counter (41) is counted up and the least significant digit output LSB is +11". Therefore, this time, the I3 input of the selector (44), that is, the lower order of the counter (4), is applied to the oooti address. 8-bit LSD value 901
is folded. Since writing to the first address input register is now complete, the counter (48) (reset terminal R is not shown) and flip-flop (50) are reset by the start pulse ST, and input of serial code data SD begins. be done.

The serial code data SD is shifted into a shift register (47) by an input clock SC and converted into 8-bit parallel data P D lc. The input clock SC also counts up a 3-bit binary counter (48) and outputs one pulse PC every 8 clocks from the carry output terminal CA. This pulse PC is an OR circuit (45)
and reaches the WR input terminal of the memory (46). At this time, the inputs HO and LQ are selected by the selector (43), the output of the power center hitter (42) is the address input of the memory (46), and the input Io is selected by the selector (44).
(-I+) is selected and the output FD of the shift register (47) is the data input of the memory (46), so
The first 8 bits of code data are written to the start address 12901 of the code data area. When this compliment is completed, the pulse PC counts up the counter (42), so that the output of the counter (42) indicates the next address 1291H in the code data area. The next 8 bits of the code data are written to this address, and the code data is written in the code data area once in the same manner.

When the input of one line of serial data is completed, the control unit af
End pulse ED is input from il. At this time, if the zero output 2 of the counter (48) is H', '1,
The number of bits of the input serial code data is exactly an integer multiple of 8, and fits perfectly between the word breaks in the memory (46) of the Pi) 4111. However, the counter (48
)'s zero output 2 is lIO, then the last sign of the %1 line is ka18. )”S, 1: @□1,71v,)□(
47). Only in the latter case, the end pulse ED passes through the AND circuit 3) and flips into the flip-flop (
49), and its output FFI becomes l゛1.
shall be. This flip-frog (49) had been reset by the previous pulse PC. As a result, the continuous pulse CC passes through the AND circuit (52),
Drives the counter (48) and shift register (47). Then, the counter (48) outputs the pulse PC, and the output PD of the shift register (47) is written into the memory (46), completing the writing of the 12-in code data. Immediately after this, the counter (42) outputs the next address of the code data area. Then, the counter (41) is activated by the pulse LC.
The code data of each line of the image is sequentially written into the memory (46) by repeating the above process starting from writing the output of the image into the memory (46).

As a result, as shown in FIG. 6, the start address of the code data of each line starts from address 0000)1 in the address data area, and the code data itself is arranged in an orderly and orderly manner in the code data area starting from address 1290H.

FIGS. 7 and 8 are a circuit diagram and a timing chart showing an embodiment of the data reading circuit (200) of the image data memory control circuit according to the present invention.

In this embodiment as well, the word length of the memory is 8 bits, the address data length is 16 bits, the code data to be output is serial, and the small image unit is a line.

In FIG. 7, a counter σ1), a selector (73),
The OR circuit (74) and memory (75) correspond to the blocks (31), G33), (34), and (35) in FIG. Equivalent to.

In addition, (78) is a 3-bit binary counter, C79) is a shift register, ωO) is a flip 1 float 7, (81) is an OR circuit, (82) to (83) are an AND circuit, and Q34
) is the N01 circuit. In FIG. 6, symbols are attached to the main signals on the circuit, and their timing relationships are shown in FIG.

Further, in the following description, an example will be shown in which image data in a format as shown in FIG. 6 written in the memory (46) is read out by this data reading circuit.

In the circuit diagram of FIG. 7, in the initial state, the pulse LS (not shown) from the control unit (161) causes the counter (71) to read the starting address LA (-00〇〇H) of the address data length area.
is preset, and RS Frigg Flots 1 (
80) is set.

First, one pulse LC is input and applied as a read pulse to the terminal RD of the memory (75) via the OR circuit C74). At this time, the selector (73) inputs H1 and L.
1, that is, the output of the counter σ1) is selected and the memory C15
) address is output to manual ADR, so 0OOO
Data 12M is read from address H and sent to output data terminal D.
Output to O. This output is the counter σ6) and (77
), but the least significant digit output LSB of the counter (71) is tt o l+
Therefore, since the pulse LC passes only through the AND circuit (82), it is preset in the counter (76). Next, the counter (71) is counted up at the falling edge of the pulse LC, and when the least significant digit output LST11B becomes 1, the next pulse LC is AND times;
Since only the i path (83) is passed through, data 901 (is read from address 0001) and preset in the counter (77).

Now the start address of the code data of the first line is 129.
Since 0H is set in counter C76) (77),
The counter (78) and flip-flop (80) are reset by the start pulse ST, and serial reading of code data is started. Since the flip-flop (80) is reset, the selector (73) is set to the input HQ and LQ sides, that is, the counter (76) and the counter c17).
Note the output! j (75) address input terminal ADR
Output to. Then, the pulse ST is inputted to the set terminal S of the shift register (79) via the OR circuit (81), and further to the terminal RD of the memory (75) via the OR circuit (74), so the start address of the code data area 1290
The first code data is read from address H and set in the shift register σ9) in an 8-bit column. Subsequently, the output clock SC is input to the counter (78) and shift register σ9), so that the code data is
It is converted into a serial data and output as a serial data SD. On the other hand, the counter (78), which is a 3-bit binary counter, is counted up.
One pulse PC is generated from the carry output terminal CA every 8 clocks of the clock SC.

This pulse PC, like the pulse ST, has a shift register (
79) and a read pulse for the memory (75), and also count up the two cascade-connected 8-bit binary counters σ6) and (77). The code data is sequentially read out from the code data area of the memory σ5), converted into i column data by the shift register c79), and output. Since the output clock SC is input by the number of bits of code data required, it is possible to extract up to the last valid bit of the code data of one line as serial data SD. In this way, one line of code data is output. When this is completed, the end pulse ED is input from the control unit a, and the flip float 7 (80) is set in the same manner as in the initial state. It is clear that by repeating the above process starting from the input of the pulse LC, the stored image data can be sequentially read out in units of 2 inches as shown in FIG.

Furthermore, in the readout circuit of FIG. 7, by setting the line number in the counter σ1) using the pulse LS (not shown) and the data LA before inputting the pulse LC, the 2nd input of that number is set. It should be noted that the configuration is such that the encoded data can be directly read out. For example, if the data LA is 00231, the start address of the code data on the 35th line is first preset in the counter (76) and C77), and then the code data starting from that start address can be read. This means that this circuit configuration enables line-by-line random access, which is actually difficult for non-fixed length code data.

Although the above embodiment has been described assuming that the image is encoded in 2-in units, the same effect can be achieved even if other image division units are used, such as encoding the image in rectangular blocks. Of course. It goes without saying that the data word length and address data length regarding the memory are not limited to the examples given in the above explanation. Further, in the above embodiment, the data write circuit and the data read circuit have been described separately, but this does not in any way prevent the circuit elements from being partially shared in both circuits. 16 again
It is also possible to store a plurality of correspondences between address data areas and code data areas in the memory as shown in the figure.

As described above, according to the present invention, the image data memory control circuit includes a counter that counts the image small units by instructing the memory that stores the image signal as non-fixed length code data for each small unit of the image, and a code data When writing image data to memory using a counter that counts the word length of the memory as a unit, a set of code data for each small image unit and a memory area in which the code data for each small image unit are stored. The system is configured so that when image data is read from memory, the start address of the memory area where the code data of each small image unit is stored can be automatically referred to. Therefore, it is possible to directly read out arbitrary small image units that are non-fixed length code data, and this control circuit allows for efficient storage and image processing suitable for image processing. This has the effect of providing a data storage circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the general configuration of an image storage device according to the invention, FIG. 2 is a block diagram showing the configuration of a data writing circuit of an image data memory control circuit according to the invention, and FIG. 3 is a block diagram showing the configuration of a data writing circuit of an image data memory control circuit according to the invention. 4 and 5 are circuit diagrams and timing charts showing one embodiment of the data writing circuit, and FIG. 6 is a block diagram showing the configuration of a data reading circuit of an image data memory control circuit according to FIGS. 7 and 8 are diagrams showing an example of a data format, and are a circuit diagram and a timing chart showing an embodiment of a data reading circuit. (21) G22) (31) (32)...11th 2nd.
Third. Fourth counter, (23) (24) (33)...
・Show) 1. Second. Third selection circuit (selector), (26
)(35)...Memory, (100)...Data write circuit, (200)...Data read circuit. Note that the same reference numerals in the drawings indicate the same or similar parts. Figure 1 Figure 2 Figure 3 Figure 4! ! !

Claims (1)

[Claims] (1) A first counter that instructs the image data memory control circuit that controls the memory that stores the image signal as non-fixed length code data for each small unit of the image to count the code data for each small unit of the image. and a second counter that counts the length of the input code data in units of word length of the memory, and one of the outputs of the first and second counters is selected and used as the address input of the memory. and a first selection circuit. a second selection circuit which selects one of the output of the second counter and the code data and inputs the image data into the memory; a data writing circuit that writes the code data of each small image unit into the memory separately from a set of starting addresses of a memory area where the code data is stored; and a third counter that counts the code data for each small image unit of the code data. , the output of the first address data of the memory is preset and the fourth counter counts the length of code data in units of word length of the memory, and either one of the outputs of the third and fourth counters is selected. The third input is the address input of the above memory.
a selection circuit, and a data readout circuit that refers to the start address of the memory area where the code data of each small unit of image is stored when reading the image data from the memory. An image data memory control circuit characterized by: