JPH07271327A - Driving circuit for el display device - Google Patents

Driving circuit for el display device

Info

Publication number
JPH07271327A
JPH07271327A JP6145794A JP6145794A JPH07271327A JP H07271327 A JPH07271327 A JP H07271327A JP 6145794 A JP6145794 A JP 6145794A JP 6145794 A JP6145794 A JP 6145794A JP H07271327 A JPH07271327 A JP H07271327A
Authority
JP
Japan
Prior art keywords
screen
voltage
drive circuit
driving circuit
upper screen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6145794A
Other languages
Japanese (ja)
Inventor
Takeshi Nishioka
健 西岡
Masahiko Osada
雅彦 長田
Shigeyuki Akita
成行 秋田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP6145794A priority Critical patent/JPH07271327A/en
Publication of JPH07271327A publication Critical patent/JPH07271327A/en
Pending legal-status Critical Current

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

PURPOSE:To perform a high luminance display without using buffer memories. CONSTITUTION:A thin film EL panel (EL element) 1 is made to be a dual insulation construction and has a memory effect due to a polarization effect. A driving circuit consists of an upper screen scanning electrode driving circuit 2, a lower screen scanning electrode driving circuit 3, an upper screen data electrode driving circuit 4 and a lower screen data electrode driving circuit 5. The upper screen scanning electrode driving circuit 2 and the lower screen scanning electrode driving circuit 3 impress sequentially a writing voltage (-Vth) from the highest scanning electrode 71 on an upper screen 1a to the lowest scanning electrode 7n on a lower screen 1b and also impress a refresh voltage (+VR) to scanning electrodes 7n/2+1 to 7n on the lower screen 1b during the period when the write voltage (-Vth) is impressed on scanning electrode 71 to 7n/2 on the upper screen 1a, conversely to this, impress the refresh voltage (+VR) to scanning electrodes 71 to 7n/2 on the upper screen 1a during the period when the write voltage (-Vth) is impressed on scanning electrodes 7n/2+1 to 7n on the lower screen 1b.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、EL(エレクトロルミ
ネッセンス)表示装置の駆動回路、詳しくは、画面が上
下方向に分割され、分極効果を有するEL表示装置の駆
動回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for an EL (electroluminescence) display device, and more particularly to a drive circuit for an EL display device in which a screen is vertically divided and which has a polarization effect.

【0002】[0002]

【従来の技術】従来から、EL表示装置において高輝度
表示を行なうために、画面を上下方向に分割し、上下各
画面を同時に線順次走査するようにした駆動回路が知ら
れている(例えば、特開昭59−116791号公報、
特開平1−319092号公報参照)。
2. Description of the Related Art Conventionally, a drive circuit has been known in which a screen is divided into upper and lower parts and upper and lower parts are simultaneously line-sequentially scanned in order to perform high-luminance display in an EL display device (for example, for example, JP-A-59-116791,
(See Japanese Patent Application Laid-Open No. 1-319092).

【0003】[0003]

【発明が解決しようとする課題】しかし、上下各画面を
線順次走査する駆動回路の場合、一画面分のデータ信号
をビデオRAM等のバッファメモリに一旦蓄積してお
き、上下各画面を線順次走査する時に、バッファメモリ
から上下各画面についてのデータ信号を読み出して上下
各画面を線順次走査する必要がある(例えば、特開平2
−220090号公報参照)。
However, in the case of a drive circuit which scans the upper and lower screens line-sequentially, a data signal for one screen is temporarily stored in a buffer memory such as a video RAM and the upper and lower screens are line-sequentially. At the time of scanning, it is necessary to read out the data signals for the upper and lower screens from the buffer memory and to scan the upper and lower screens line-sequentially (for example, Japanese Patent Laid-Open No. Hei 2).
-222090).

【0004】従って、上記のような上下各画面を同時に
線順次走査する従来の駆動回路においては、バッファメ
モリが必要不可欠で、しかも画素数や階調数の増加に従
って容量の大きなバッファメモリが必要になるため回路
規模が大型になるという問題がある。
Therefore, in the conventional driving circuit for scanning the upper and lower screens simultaneously in a line-sequential manner, a buffer memory is indispensable, and a buffer memory having a large capacity is required as the number of pixels and the number of gradations increase. Therefore, there is a problem that the circuit scale becomes large.

【0005】そこで、請求項1に係るEL表示装置の駆
動回路は、二重絶縁構造のEL素子には分極効果による
メモリ効果がある点に着目し、バッファメモリを用いる
ことなく高輝度表示を行なわせることを目的とする。
Therefore, in the drive circuit of the EL display device according to the first aspect, attention is paid to the fact that the EL element having the double insulation structure has a memory effect due to the polarization effect, and high-luminance display is performed without using a buffer memory. The purpose is to let.

【0006】また、請求項2に係るEL表示装置の駆動
回路は、リフレッシュ電圧を線順次走査的に走査電極に
対して印加する方式をとるEL表示装置において、バッ
ファメモリを用いることなく高輝度表示を行なうことを
目的とする。
The drive circuit for an EL display device according to a second aspect of the present invention is an EL display device that adopts a method of applying a refresh voltage to scan electrodes in a line-sequential scanning manner, with a high-luminance display without using a buffer memory. The purpose is to do.

【0007】また、請求項3に係るEL表示装置の駆動
回路は、リフレッシュ電圧を分割画面毎の走査電極に対
して同時に印加する方式をとるEL表示装置において、
バッファメモリを用いることなく高輝度表示を行なうこ
とを目的とする。
The drive circuit for an EL display device according to a third aspect of the present invention is an EL display device that employs a system in which a refresh voltage is simultaneously applied to scan electrodes for each divided screen.
The purpose is to perform high-intensity display without using a buffer memory.

【0008】[0008]

【課題を解決するための手段】上記目的の下、請求項1
に係るEL表示装置の駆動回路は、画面が上下方向に分
割され、分極効果を有するEL表示装置の駆動回路にお
いて、上画面の最上位の走査電極から下画面の最下位の
走査電極まで順に書込電圧を印加してゆくとともに、前
記上画面の走査電極に書込電圧が印加される期間に、前
記下画面の走査電極に対しリフレッシュ電圧を印加し、
これとは逆に、前記下画面の走査電極に書込電圧が印加
される期間に、前記上画面の走査電極に対しリフレッシ
ュ電圧を印加するよう構成したことを特徴とする。
For the above-mentioned purpose, the method according to claim 1
In the drive circuit of the EL display device according to the above, the screen is divided in the vertical direction, and in the drive circuit of the EL display device having a polarization effect, writing is performed in order from the uppermost scan electrode of the upper screen to the lowermost scan electrode of the lower screen. While applying a built-in voltage, a refresh voltage is applied to the scan electrodes of the lower screen during a period in which a write voltage is applied to the scan electrodes of the upper screen,
On the contrary, it is characterized in that the refresh voltage is applied to the scan electrodes of the upper screen while the write voltage is applied to the scan electrodes of the lower screen.

【0009】また、請求項2に係るEL表示装置の駆動
回路は、請求項1に係るEL表示装置の駆動回路におい
て、前記リフレッシュ電圧は、前記上画面の走査電極へ
の書込電圧印加に同期して、前記上画面の走査電極と同
じ順位に相当する前記下画面の走査電極に対して印加さ
れ、また、前記下画面の走査電極への書込電圧印加に同
期して、前記下画面の走査電極と同じ順位に相当する前
記上画面の走査電極に対して印加されることを特徴とす
る。
According to a second aspect of the present invention, there is provided a drive circuit for an EL display device according to the first aspect, wherein the refresh voltage is synchronized with application of a write voltage to scan electrodes on the upper screen. Then, the voltage is applied to the scan electrodes of the lower screen corresponding to the same order as the scan electrodes of the upper screen, and in synchronization with the application of the write voltage to the scan electrodes of the lower screen. It is characterized in that the voltage is applied to the scan electrodes of the upper screen corresponding to the same rank as the scan electrodes.

【0010】また、請求項3に係るEL表示装置の駆動
回路は、請求項1に係るEL表示装置の駆動回路におい
て、前記リフレッシュ電圧を、前記上画面毎及び前記下
画面毎に同時に印加することを特徴とする。
According to a third aspect of the present invention, there is provided a drive circuit of an EL display device according to the first aspect, wherein the refresh voltage is applied to each of the upper screen and the lower screen at the same time. Is characterized by.

【0011】[0011]

【発明の作用効果】請求項1に係るEL表示装置の駆動
回路では、画面は上下方向に分割されてはいるが、書込
電圧を走査電極に印加する線順次走査は、上下各画面を
同時に線順次走査する従来の方式とはならず、画面を上
下方向に分割しない通常の画面に対する線順次走査と一
致したものとなる。このため、データ信号を蓄積する必
要がなくなり、バッファメモリが不要になる。また、リ
フレッシュ電圧印加時、直前の書込電圧印加により発光
した画素においては分極が生じており、この分極効果に
より再び発光させることができる。このため、画面を上
下方向に分割したEL表示装置の従来の駆動回路と同
様、高輝度表示を行なうことができる。
In the drive circuit of the EL display device according to the first aspect of the present invention, although the screen is divided in the vertical direction, the line-sequential scanning in which the write voltage is applied to the scan electrodes is performed in the upper and lower screens simultaneously. This is not the conventional method of line-sequential scanning, and is the same as line-sequential scanning for a normal screen in which the screen is not vertically divided. Therefore, it is not necessary to store the data signal, and the buffer memory becomes unnecessary. In addition, when a refresh voltage is applied, polarization is generated in a pixel that emits light when a write voltage is applied immediately before, and the polarization effect allows light to be emitted again. Therefore, high-luminance display can be performed as in the conventional drive circuit of the EL display device in which the screen is divided in the vertical direction.

【0012】また、請求項2に係るEL表示装置の駆動
回路によると、リフレッシュ電圧を線順次走査的に走査
電極に対して印加する方式をとるEL表示装置におい
て、バッファメモリを用いずに高輝度表示を行なうこと
ができるようになる。
Further, according to the driving circuit of the EL display device of the second aspect, in the EL display device which adopts a method of applying the refresh voltage to the scan electrodes in a line-sequential scanning manner, a high brightness is obtained without using a buffer memory. The display can be performed.

【0013】また、請求項3に係るEL表示装置の駆動
回路によると、リフレッシュ電圧を分割画面毎の走査電
極に対して同時に印加する方式をとるEL表示装置にお
いて、バッファメモリを用いることなく高輝度表示を行
なうことができるようになる。
Further, according to the drive circuit of the EL display device of the third aspect, in the EL display device which adopts the method of simultaneously applying the refresh voltage to the scan electrodes for each divided screen, a high brightness is obtained without using a buffer memory. The display can be performed.

【0014】[0014]

【実施例】以下、本発明の一実施例を図面に基づいて説
明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0015】図1は、一実施例に係る駆動回路が組み込
まれたEL表示装置の構成、図2は、同駆動回路の詳細
な構成、図3は、その動作を説明するためのタイミング
チャートをそれぞれ示している。
FIG. 1 is a configuration of an EL display device incorporating a drive circuit according to an embodiment, FIG. 2 is a detailed configuration of the drive circuit, and FIG. 3 is a timing chart for explaining the operation thereof. Shown respectively.

【0016】図1において、EL表示装置の薄膜ELパ
ネル(EL素子)1は、二重絶縁構造をしており、分極
効果によるメモリ効果を有するものである。そして、こ
の薄膜ELパネル1は、上下に2分割され、上画面1a
と下画面1bとから構成される。この薄膜ELパネル1
を駆動する駆動回路は、上画面走査電極駆動回路2と下
画面走査電極駆動回路3と上画面データ電極駆動回路4
と下画面データ電極駆動回路5とからなる。上画面走査
電極駆動回路2、下画面走査電極駆動回路3、上画面デ
ータ電極駆動回路4及び下画面データ電極駆動回路5は
タイミング制御回路6と接続され、これらの駆動回路2
〜5の出力タイミングは、水平同期信号及び垂直同期信
号を入力するタイミング制御回路6が出力する制御信号
により決定される。また、上画面データ電極駆動回路4
及び下画面データ電極駆動回路5には、それぞれ、上画
面表示データ及び下画面表示データが入力される。
In FIG. 1, a thin film EL panel (EL element) 1 of an EL display device has a double insulating structure and has a memory effect due to a polarization effect. The thin film EL panel 1 is divided into upper and lower parts, and the upper screen 1a
And a lower screen 1b. This thin film EL panel 1
The drive circuit for driving the upper screen scan electrode drive circuit 2, the lower screen scan electrode drive circuit 3, and the upper screen data electrode drive circuit 4 are
And a lower screen data electrode drive circuit 5. The upper screen scan electrode drive circuit 2, the lower screen scan electrode drive circuit 3, the upper screen data electrode drive circuit 4, and the lower screen data electrode drive circuit 5 are connected to a timing control circuit 6, and these drive circuits 2
The output timings of 5 to 5 are determined by the control signal output by the timing control circuit 6 which receives the horizontal synchronizing signal and the vertical synchronizing signal. In addition, the upper screen data electrode drive circuit 4
The upper screen display data and the lower screen display data are input to the lower screen data electrode driving circuit 5, respectively.

【0017】上画面走査電極駆動回路2は、図2に示す
ように、シフトレジスタ2aと複数のドライバIC2b
とから構成される。シフトレジスタ2aは、n/2ビッ
トシフトレジスタで構成され、上画面1aのn/2個の
走査電極71 〜7n/2 を最上位の走査電極(第1ロウの
走査電極)71 から最下位の走査電極(第n/2ロウの
走査電極)7n/2 まで1つずつ順に駆動可能とする駆動
内容を記憶内容としており、タイミング制御回路6から
の制御信号にもとづくタイミングでシフト動作を行ない
記憶内容を各ドライバIC2bに出力するよう構成され
ている。ドライバIC2bは、各走査電極71 〜7n/2
と1対1に対応して設けられ、n/2ビットシフトレジ
スタ2aの対応するビットの記憶内容に応じて、負極性
の書込電圧(−Vth)、正極性のリフレッシュ電圧(+
R )又は接地電圧を走査電極7 1 〜7n/2 に印加する
よう構成される。ここで、書込電圧(−Vth)とリフレ
ッシュ電圧(+VR )は、交互に出力される。
The upper screen scan electrode drive circuit 2 is shown in FIG.
As described above, the shift register 2a and the plurality of driver ICs 2b
Composed of and. The shift register 2a has n / 2 bits
It is composed of a shift register and has n / 2
Scanning electrode 71 ~ 7n / 2 The uppermost scanning electrode (of the first row
Scanning electrode) 71 To the lowest scan electrode (n / 2th row)
Scanning electrode) 7n / 2 Drive that can sequentially drive up to one by one
The contents are stored, and the timing control circuit 6
Shift operation is performed at the timing based on the control signal of
It is configured to output the stored contents to each driver IC 2b.
ing. The driver IC 2b is connected to each scan electrode 71 ~ 7n / 2 
And n / 2 bit shift register
Depending on the stored contents of the corresponding bit of the star 2a.
Write voltage (-Vth), Positive refresh voltage (+
VR ) Or ground voltage to scan electrode 7 1 ~ 7n / 2 Apply to
Is configured. Here, the write voltage (-Vth) And reflation
Voltage (+ VR ) Are output alternately.

【0018】下画面走査電極駆動回路3は、図2に示す
ように、上画面走査電極駆動回路2と同様、シフトレジ
スタ3aと複数のドライバIC3bとから構成される。
シフトレジスタ3aは、n/2ビットシフトレジスタで
構成され、下画面1bのn/2個の走査電極7n/2+1
n を最上位の走査電極(第(n/2+1)ロウの走査
電極)7n/2+1 から最下位の走査電極(第nロウの走査
電極)7n まで1つずつ順に駆動可能とする駆動内容を
記憶内容としており、タイミング制御回路6からの制御
信号にもとづくタイミングでシフト動作を行ない記憶内
容を各ドライバIC3bに出力するよう構成されてい
る。ドライバIC3bは、各走査電極7n/ 2+1 〜7n
1対1に対応して設けられ、n/2ビットシフトレジス
タ3aの対応するビットの記憶内容に応じて、負極性の
書込電圧(−Vth)、正極性のリフレッシュ電圧(+V
R )又は接地電圧を走査電極に印加するよう構成され
る。ここで、書込電圧(−Vth)とリフレッシュ電圧
(+VR )は、交互に出力される。
As shown in FIG. 2, the lower screen scan electrode drive circuit 3 is composed of a shift register 3a and a plurality of driver ICs 3b, like the upper screen scan electrode drive circuit 2.
The shift register 3a is composed of an n / 2-bit shift register, and has n / 2 scan electrodes 7 n / 2 + 1 to n of the lower screen 1b.
7 n can be sequentially driven one by one from the highest scan electrode (scan electrode of the (n / 2 + 1) th row) 7 n / 2 + 1 to the lowest scan electrode (scan electrode of the nth row) 7 n. The drive contents to be stored are stored, and the shift operation is performed at a timing based on the control signal from the timing control circuit 6 to output the stored contents to each driver IC 3b. The driver IC 3b is provided in a one-to-one correspondence with each of the scan electrodes 7 n / 2 + 1 to 7 n, and writes in the negative polarity according to the stored content of the corresponding bit of the n / 2 bit shift register 3a. Voltage (-V th ), positive refresh voltage (+ V
R ) or ground voltage is applied to the scan electrodes. Here, writing voltage (-V th) and a refresh voltage (+ V R) is output alternately.

【0019】上画面データ電極駆動回路4は、図2に示
すように、シフトレジスタ4aと複数のドライバIC4
bとから構成される。シフトレジスタ4aは、mビット
シフトレジスタで構成され、上画面1aのm個のデータ
電極(第1カラムから第mカラムまでのデータ電極)8
1 〜8m に対する上画面表示データを記憶内容としてお
り、タイミング制御回路6からの制御信号にもとづくタ
イミングでシフト動作を行ない記憶内容を各ドライバI
C4bに出力するよう構成されている。ドライバIC4
bは、各データ電極81 〜8m と1対1に対応して設け
られ、mビットシフトレジスタ4aの対応するビットの
記憶内容に応じて、変調電圧(+VM )又は接地電圧を
データ電極に印加するよう構成される。
As shown in FIG. 2, the upper screen data electrode driving circuit 4 includes a shift register 4a and a plurality of driver ICs 4
b. The shift register 4a is composed of an m-bit shift register, and has m data electrodes (data electrodes from the first column to the m-th column) 8 of the upper screen 1a.
The upper screen display data for 1 to 8 m is stored, and the shift operation is performed at the timing based on the control signal from the timing control circuit 6 to store the stored contents in each driver I.
It is configured to output to C4b. Driver IC4
b is provided in a one-to-one correspondence with each of the data electrodes 8 1 to 8 m, and the modulation voltage (+ V M ) or the ground voltage is applied to the data electrode depending on the stored content of the corresponding bit of the m-bit shift register 4 a. Is configured to apply to.

【0020】下画面データ電極駆動回路5は、図2に示
すように、上画面データ電極駆動回路4と同様、シフト
レジスタ5aと複数のドライバIC5bとから構成され
る。シフトレジスタ5aは、mビットシフトレジスタで
構成され、下画面1bのm個のデータ電極(第1カラム
から第mカラムまでの走査電極)91 〜9m に対する下
画面表示データを記憶内容としており、タイミング制御
回路6からの制御信号にもとづくタイミングでシフト動
作を行ない記憶内容を各ドライバIC5bに出力するよ
う構成されている。ドライバIC5bは、各データ電極
1 〜9m と1対1に対応して設けられ、mビットシフ
トレジスタ5aの対応するビットの記憶内容に応じて、
変調電圧(+VM )又は接地電圧をデータ電極に印加す
るよう構成される。
As shown in FIG. 2, the lower screen data electrode drive circuit 5 is composed of a shift register 5a and a plurality of driver ICs 5b, like the upper screen data electrode drive circuit 4. Shift register 5a is composed of m-bit shift register, and the lower screen display data for (scanning electrodes from the first column to the m column) 9 1 to 9 m m pieces of data electrodes of the lower screen 1b stored data The shift operation is performed at the timing based on the control signal from the timing control circuit 6 and the stored contents are output to each driver IC 5b. The driver IC 5b is provided in a one-to-one correspondence with each of the data electrodes 9 1 to 9 m, and according to the stored content of the corresponding bit of the m-bit shift register 5a,
A modulation voltage (+ V M ) or ground voltage is configured to be applied to the data electrodes.

【0021】次に、駆動回路による駆動方法の一例を図
3に基づいて説明する。
Next, an example of the driving method by the driving circuit will be described with reference to FIG.

【0022】本実施例では、1フレームを、上画面フィ
ールドと、これに続く下画面フィールドとから構成す
る。
In the present embodiment, one frame is composed of an upper screen field and a lower screen field following the upper screen field.

【0023】上画面フィールドでは、上画面走査電極駆
動回路2により、上画面走査側1番目の電極(上画面の
最上位の走査電極)71 から、上画面走査側n/2番目
の電極(上画面の最下位の走査電極)7n/2 まで、順に
書込電圧(−Vth)を印加してゆき、また、この書込電
圧印加と同期させて、下画面走査電極駆動回路3によ
り、下画面走査側1番目(下画面の最上位の走査電極)
n/2+1 から、下画面走査側n/2番目の電極(下画面
の最下位の走査電極)7n まで、順にリフレッシュ電圧
(+VR )を印加してゆき、また、上画面フィールドで
は、書込電圧印加と同期させて、上画面データ電極駆動
回路4により、上画面表示データに基づき変調電圧(+
M )又は接地電圧をデータ側のi番目(i=1,2,
…,m)の電極8i に印加してゆく。ここで、上画面1
aにおいて、変調電圧(+VM )が印加されたデータ電
極とこの時の走査電極とが交差する画素部分の発光層に
は、発光閾値電圧を超える電圧(+VM +Vth)が印加
されるため、当該画素は発光し、一方、接地電圧が印加
されたデータ電極とこの時の走査電極とが交差する画素
部分の発光層には、発光閾値電圧を超えない電圧(+V
th)が印加されるため、当該画素は発光しない。一方、
下画面1bにおいては、直前の下画面フィールドで発光
した画素は、分極効果によるメモリ効果を有しているた
め、リフレッシュ電圧(+VR )が印加されても発光
し、一方、直前の下画面フィールドで発光しなかった画
素は、分極効果によるメモリ効果を有していないため、
リフレッシュ電圧(+VR )が印加されても発光しな
い。
In the upper screen field, the upper screen scan electrode driving circuit 2 starts from the first electrode on the upper screen scan side (the uppermost scan electrode of the upper screen) 7 1 to the n / 2nd electrode on the upper screen scan side ( The write voltage (-V th ) is sequentially applied up to 7 n / 2 of the lowermost scan electrode of the upper screen, and in synchronization with the application of the write voltage, the lower screen scan electrode drive circuit 3 is used. , Lower screen scan side 1st (uppermost scan electrode of lower screen)
From 7 n / 2 + 1, until the (lowest scan electrodes of the lower screen) 7 n lower screen scanning side n / 2-th electrode, so on are sequentially applying the refresh voltage (+ V R), also on the screen field Then, in synchronization with the writing voltage application, the modulation voltage (+
V M ) or the ground voltage is the i-th (i = 1, 2,
, M) is applied to the electrode 8 i . Here, upper screen 1
In a, a voltage (+ V M + V th ) exceeding the light emission threshold voltage is applied to the light emitting layer of the pixel portion where the data electrode to which the modulation voltage (+ V M ) is applied and the scanning electrode at this time intersect. , The pixel emits light, and in the light emitting layer of the pixel portion where the data electrode to which the ground voltage is applied intersects the scan electrode at this time, a voltage (+ V
th ) is applied, the pixel does not emit light. on the other hand,
In the lower screen 1b, immediately before the pixels which emit light under the screen field, since it has a memory effect due to the polarization effect, even if a refresh voltage (+ V R) is applied emits light, whereas, under the previous screen field Pixels that did not emit light in, because they do not have a memory effect due to polarization effect,
Refresh voltage (+ V R) does not emit light be applied.

【0024】下画面フィールドでは、下画面走査電極駆
動回路3により、下画面走査側1番目の電極(下画面の
最上位の走査電極)7n/2+1 から、下画面走査側n/2
番目の電極(下画面の最下位の走査電極)7n まで、順
に書込電圧(−Vth)を印加してゆき、また、この書込
電圧印加と同期させて、上画面走査電極駆動回路2によ
り、上画面走査側1番目(上画面の最上位の走査電極)
1 から、上画面走査側n/2番目の電極(上画面の最
下位の走査電極)7n/2 まで、順にリフレッシュ電圧
(+VR )を印加してゆき、また、下画面フィールドで
は、書込電圧印加と同期させて、下画面データ電極駆動
回路5により、下画面表示データに基づき変調電圧(+
M )又は接地電圧をデータ側のi番目(i=1,2,
…,m)の電極9i に印加してゆく。ここで、下画面1
bにおいて、変調電圧(+VM )が印加されたデータ電
極とこの時の走査電極とが交差する画素部分の発光層に
は、発光閾値電圧を超える電圧(+VM +Vth)が印加
されるため、当該画素は発光し、一方、接地電圧が印加
されたデータ電極とこの時の走査電極とが交差する画素
部分の発光層には、発光閾値電圧を超えない電圧(+V
th)が印加されるため、当該画素は発光しない。一方、
上画面1aにおいては、直前の上画面フィールドで発光
した画素は、分極効果によるメモリ効果を有しているた
め、リフレッシュ電圧(+VR )が印加されると発光
し、一方、直前の上画面フィールドで発光しなかった画
素は、分極効果によるメモリ効果を有していないため、
リフレッシュ電圧(+VR )が印加されても発光しな
い。
In the lower screen field, the lower screen scan electrode driving circuit 3 starts from the first electrode on the lower screen scan side (the uppermost scan electrode of the lower screen) 7 n / 2 + 1 to the lower screen scan side n / 2.
The write voltage (-V th ) is sequentially applied to the 7th electrode (the lowest scan electrode of the lower screen) 7 n , and the upper screen scan electrode drive circuit is synchronized with the application of the write voltage. 2, the first on the upper screen scan side (the uppermost scan electrode on the upper screen)
7 1, until (lowest scan electrodes of the upper screen) 7 n / 2 on the screen scanning side n / 2-th electrode, so on are sequentially applying the refresh voltage (+ V R), also in the lower screen field, In synchronization with the application of the write voltage, the lower screen data electrode drive circuit 5 causes the modulation voltage (+
V M ) or the ground voltage is the i-th (i = 1, 2,
, M) is applied to the electrode 9 i . Here, lower screen 1
In b, since a voltage (+ V M + V th ) exceeding the light emission threshold voltage is applied to the light emitting layer of the pixel portion where the data electrode to which the modulation voltage (+ V M ) is applied and the scan electrode at this time intersect with each other. , The pixel emits light, and in the light emitting layer of the pixel portion where the data electrode to which the ground voltage is applied intersects the scan electrode at this time, a voltage (+ V
th ) is applied, the pixel does not emit light. on the other hand,
In the upper screen 1a, the pixels emitted in the screen field on immediately before, because it has a memory effect due to the polarization effect, and emitting a refresh voltage (+ V R) is applied, whereas, on the previous screen field Pixels that did not emit light in, because they do not have a memory effect due to polarization effect,
Refresh voltage (+ V R) does not emit light be applied.

【0025】以上説明したように、本実施例の駆動回路
によると、画面1は上下方向に分割されてはいるが、書
込電圧(−Vth)を走査電極71 〜7n に印加する線順
次走査は、上下各画面1a,1bを同時に線順次走査す
る従来の方式とはならず、画面1を上下方向に分割しな
い通常の画面に対する線順次走査と一致したものとな
る。このため、データ信号を蓄積する必要がなくなり、
バッファメモリが不要になり、回路規模を縮小化するこ
とができる。また、リフレッシュ電圧(+VR )印加
時、直前の書込電圧印加により発光した画素においては
分極が生じており、この分極効果により再び発光させる
ことができる。このため、画面1を上下方向に分割した
EL表示装置の従来の駆動回路と同様、通常の走査周波
数の2倍の周波数で走査することができるため高輝度表
示を行なうことができる。
As described above, according to the drive circuit of this embodiment, although the screen 1 is divided in the vertical direction, the write voltage (-V th ) is applied to the scan electrodes 7 1 to 7 n . The line-sequential scanning is not the conventional method of line-sequentially scanning the upper and lower screens 1a and 1b at the same time, and is the same as the line-sequential scanning for a normal screen in which the screen 1 is not vertically divided. This eliminates the need to store data signals,
The buffer memory becomes unnecessary, and the circuit scale can be reduced. Furthermore, the refresh voltage (+ V R) applied, and the polarization occurs in the pixel emitted by the write voltage application just before, it is possible to re-emit light by the polarization effect. Therefore, similarly to the conventional drive circuit of the EL display device in which the screen 1 is divided in the vertical direction, scanning can be performed at a frequency twice the normal scanning frequency, so that high-luminance display can be performed.

【0026】なお、本発明は、上述したようなリフレッ
シュ電圧(+VR )を線順次走査的に走査電極71 〜7
n に対して印加する方式をとるEL表示装置に限定され
るものではなく、その他、リフレッシュ電圧(+VR
を分割画面1a,1b毎の走査電極71 〜7n/2 ,7
n/2+1 〜7n に対して同時に印加する方式をとるEL表
示装置にも容易に適用でき、同様の効果を奏する。
[0026] The present invention is scanned above such refreshing voltage (+ V R) line-sequentially scanned electrodes 7 1 to 7
is not limited to the EL display device taking method to be applied to n, other, the refresh voltage (+ V R)
Scan electrodes 7 1 to 7 n / 2 , 7 for each of divided screens 1a and 1b
It can be easily applied to an EL display device that adopts a method of simultaneously applying to n / 2 + 1 to 7 n , and has the same effect.

【図面の簡単な説明】[Brief description of drawings]

【図1】一実施例に係る駆動回路が適用されるEL表示
装置の構成図
FIG. 1 is a configuration diagram of an EL display device to which a drive circuit according to an embodiment is applied.

【図2】同駆動回路の構成図FIG. 2 is a configuration diagram of the drive circuit.

【図3】同駆動回路の動作を説明するためのタイミング
チャート
FIG. 3 is a timing chart for explaining the operation of the drive circuit.

【符号の説明】[Explanation of symbols]

1a 上画面 1b 下画面 2 上画面走査電極駆動回路 3 下画面走査電極駆動回路 4 上画面データ電極駆動回路 5 下画面データ電極駆動回路 71 上画面の最上位の走査電極 71 〜7n/2 上画面の走査電極 7n/2+1 〜7n 下画面の走査電極 7n 下画面の最下位の走査電極 −Vth 書込電圧 +VR リフレッシュ電圧1a on the screen 1b bottom of the screen 2 on the screen scanning electrode drive circuit 3 under the screen scanning electrode driving circuit 4 on the screen data electrode driving circuit 5 lower screen data electrode driving circuit 7 1 scan electrodes 7 uppermost of the upper screen 1 to 7-n / 2 on the screen of the scanning electrode 7 n / 2 + 1 to 7-lowest scanning electrodes 7 n the bottom of the screen of the n bottom of the screen of the scanning electrodes -V th writing voltage + V R refresh voltage

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 画面が上下方向に分割され、分極効果を
有するEL表示装置の駆動回路において、上画面の最上
位の走査電極から下画面の最下位の走査電極まで順に書
込電圧を印加してゆくとともに、前記上画面の走査電極
に書込電圧が印加される期間に、前記下画面の走査電極
に対しリフレッシュ電圧を印加し、これとは逆に、前記
下画面の走査電極に書込電圧が印加される期間に、前記
上画面の走査電極に対しリフレッシュ電圧を印加するよ
う構成したことを特徴とするEL表示装置の駆動回路。
1. A drive circuit of an EL display device in which a screen is divided in the vertical direction and has a polarization effect, a write voltage is sequentially applied from the uppermost scan electrode of the upper screen to the lowermost scan electrode of the lower screen. As the write voltage is applied to the scan electrodes of the upper screen, a refresh voltage is applied to the scan electrodes of the lower screen, and conversely, a write voltage is applied to the scan electrodes of the lower screen. A drive circuit for an EL display device, characterized in that a refresh voltage is applied to the scan electrodes of the upper screen during a period in which a voltage is applied.
【請求項2】 前記リフレッシュ電圧は、前記上画面の
走査電極への書込電圧印加に同期して、前記上画面の走
査電極と同じ順位に相当する前記下画面の走査電極に対
して印加され、また、前記下画面の走査電極への書込電
圧印加に同期して、前記下画面の走査電極と同じ順位に
相当する前記上画面の走査電極に対して印加されること
を特徴とする請求項1に記載のEL表示装置の駆動回
路。
2. The refresh voltage is applied to the scan electrodes of the lower screen corresponding to the same order as the scan electrodes of the upper screen in synchronization with the application of the write voltage to the scan electrodes of the upper screen. , And is applied to the scan electrodes of the upper screen corresponding to the same rank as the scan electrodes of the lower screen in synchronization with the application of the write voltage to the scan electrodes of the lower screen. Item 2. A drive circuit for an EL display device according to item 1.
【請求項3】 前記リフレッシュ電圧は、前記上画面毎
及び前記下画面毎に同時に印加されることを特徴とする
請求項1に記載のEL表示装置の駆動回路。
3. The drive circuit for an EL display device according to claim 1, wherein the refresh voltage is applied simultaneously to each of the upper screen and each of the lower screens.
JP6145794A 1994-03-30 1994-03-30 Driving circuit for el display device Pending JPH07271327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6145794A JPH07271327A (en) 1994-03-30 1994-03-30 Driving circuit for el display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6145794A JPH07271327A (en) 1994-03-30 1994-03-30 Driving circuit for el display device

Publications (1)

Publication Number Publication Date
JPH07271327A true JPH07271327A (en) 1995-10-20

Family

ID=13171596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6145794A Pending JPH07271327A (en) 1994-03-30 1994-03-30 Driving circuit for el display device

Country Status (1)

Country Link
JP (1) JPH07271327A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980081805A (en) * 1997-04-28 1998-11-25 모리시타요우이치 Liquid crystal display device and driving method thereof
KR100316980B1 (en) * 1998-09-28 2001-12-22 가타오카 마사타카 Liquid crystal display device
KR100468173B1 (en) * 2000-12-07 2005-01-26 산요덴키가부시키가이샤 Active matrix type display device
KR100469600B1 (en) * 2000-12-07 2005-02-02 가부시키가이샤 히타치세이사쿠쇼 Display device
KR100508030B1 (en) * 1997-09-09 2005-10-26 삼성전자주식회사 LCD Display
JP2006023539A (en) * 2004-07-08 2006-01-26 Tohoku Pioneer Corp Self light emitting display panel and its driving method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980081805A (en) * 1997-04-28 1998-11-25 모리시타요우이치 Liquid crystal display device and driving method thereof
KR100508030B1 (en) * 1997-09-09 2005-10-26 삼성전자주식회사 LCD Display
KR100316980B1 (en) * 1998-09-28 2001-12-22 가타오카 마사타카 Liquid crystal display device
KR100468173B1 (en) * 2000-12-07 2005-01-26 산요덴키가부시키가이샤 Active matrix type display device
KR100469600B1 (en) * 2000-12-07 2005-02-02 가부시키가이샤 히타치세이사쿠쇼 Display device
JP2006023539A (en) * 2004-07-08 2006-01-26 Tohoku Pioneer Corp Self light emitting display panel and its driving method

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