JPH07264877A - Surge suppressing device for semiconductor switch of inverter circuit - Google Patents

Abstract

PURPOSE:To reduce the loss of an inverter circuit by means of resistors by connecting a third capacitor to the connecting point between each diode of both positive and negative semiconductor switches and a capacitor and the positive and negative poles of a DC power source facing both ends of the third capacitor through the resistors. CONSTITUTION:When a GTO 21 is turned off and another GTO 11 is turned on, an electric current which is interrupted by a current circulating diode 24 and flows to the GTO 11 flows to a load side from an AC output terminal 2 and, at the same time, gives a charge of electricity to a snubber capacitor 23. The electric charges in an overcharged clamp capacitor 3 and the snubber capacitor 23 are discharged through snubber resistors 16 and 26 and, at the same time, fed back to a DC power source 1. When the GTO 11 is turned off, the capacitor 3 is overcharged, but the electric current flowing to the capacitor 23 flows from the output terminal 2 so that the current can be utilized as a load current. The electric charges in the capacitors 3 and 13 are fed back to the power source 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter for obtaining AC power from a DC power supply, and more particularly to a surge suppressor for a semiconductor switch in an inverter circuit in which the energy of a snubber capacitor is returned to the DC power supply to reduce snubber resistance loss. Is.

[0002]

2. Description of the Related Art FIG. 3 shows a prior art example. FIG. 3 shows one arm of an inverter circuit of a conventional example, 1 is a DC power source, 11 and 21 are semiconductor switches (hereinafter referred to as GTO) using a gate turn-off thyristor of an example of a self-turn-off switching element, 2 is an AC output terminal. Here, the DC power supply 1 and the GTO 11 are arranged on the anode side and the GTO 21 is arranged on the cathode side and connected in series.

In FIG. 3, a snubber diode 12 and a snubber capacitor 13 are connected in series to the GTO 11 in parallel. A snubber diode 22 and a snubber capacitor 23 are connected in series to the GTO 21 in parallel. The AC output terminal 2 is drawn out from the connection point of the snubber capacitors 13 and 23. 14 and 24 are free wheeling diodes connected in parallel to the GTOs 11 and 21.

Reference numerals 15 and 25 are snubber resistors, 3 is a clamp capacitor, and 41 is a reactor. A resistor 43 for damping reactor energy and a diode 42 are connected in series to the reactor 41 in parallel.
In such a circuit configuration, the DC power supply 1 is obtained and the GTO is
11 and 21 alternately repeat on / off operation to supply AC power to the AC output terminal 2. This is as follows.

First, when the GTO 11 is turned on, the snubber capacitor 13 charged to the power source voltage of the DC power source 1
Is discharged through the snubber resistor 15, which is a loss. After that, it is overcharged, and the polarity of the voltage across the reactor 41 is (-) on the DC power supply 1 side, and GT
The anode side of O11 is applied at (+), and this energy is discharged through the resistor 42 through the diode 42, which is also a loss.

Then, when the GTO 11 is turned off, the electric charge of the snubber capacitor 23 charged to the power supply voltage is
It is discharged to the load side which is the AC output terminal 2. After that, it is overcharged, the voltage across the recoil 41 is applied with the opposite polarity, and is discharged through the diode 42 and the resistor 43 as in the above-mentioned turn-on, resulting in a loss.

[0007]

As described above, in the conventional example of this kind, the charges overcharged in the capacitors 3, 13, 23 at the time of turning on and off of the semiconductor switch are mainly caused by the snubber resistor 15, It was discharged through the resistor 25 and the resistor 43, and there was a problem that the loss due to the resistor 43 was particularly large.

[0008]

The present invention has been made in view of the above points. The purpose thereof is to reduce the loss of such a resistor and to feed it back to a DC power supply, thereby making the inverter circuit compact and improving the efficiency.

Therefore, according to the present invention, the third capacitor is connected to the connection point of each diode and the capacitor of both the positive and negative semiconductor switches, and the charge of the third capacitor can be discharged to the DC power supply. The positive and negative sides of the DC power supply facing both ends of the capacitor are coupled by a husband and wife resistor. More specifically, a reactor is arranged on the DC power supply side of both positive and negative semiconductor switches, and the other end of the snubber resistor is connected to the DC power supply side of the reactor, and the anode and cathode sides of both positive and negative semiconductor switches are connected. The snubbers of are arranged symmetrically.

[0010]

With this solution, the energy stored in the capacitor at the time of switching the semiconductor switch can be returned to the DC power supply, and snubber loss can be reduced. In particular, when the semiconductor switch is turned on, the electric charge of the capacitor is discharged through the reactor, so that it can be easily returned to the DC power supply, and the effect of reducing snubber loss is great. Furthermore, the resistor and the diode for attenuating the reactor energy, which are conventionally connected in parallel with the reactor, can be eliminated.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. FIG. 1 shows the configuration of an essential part of an embodiment of the present invention expressed in a manner similar to FIG. 3, in which 12, 26 are snubber resistors, 17,
18 is a reactor. That is, the reactor 17 is GT
It is arranged between the anode side of O and the positive electrode of the DC power supply 1, and the reactor 18 is arranged between the cathode side of the GTO 21 and the negative electrode of the DC power supply 1.

Further, one ends of the snubber resistors 16 and 26 are connected to the snubber capacitor 13 (clamp capacitor 3) side, respectively, and the other ends are connected so as to couple the positive and negative sides of the DC power source 1, respectively. And the resistor 42 and the diode 42 shown in FIG. 3 have been removed. Next, the operation of this circuit configuration will be described with reference to FIG.

First, in the turn-on operation of the GTO 11, since the GTO 11 is initially in the OFF state and the GTO 21 is in the ON state, the snubber capacitor 13 is charged to the power source voltage of the DC power source 1, and the snubber capacitor 23 is at the voltage level. It is zero. At this time, as shown in FIG. 2A, the current passes through the freewheeling diode 24 and flows from the AC output terminal 2 to the load side.

When the GTO 21 is turned off and the GTO 11 is turned on from the operation mode shown in FIG. 2A, the electric current for discharging the electric charge of the snubber capacitor 13 is: snubber capacitor 13 → snubber resistor 16 → reactor 17 →
It flows through the GTO 11 and becomes a path for discharging through the reactor 17.

Further, the free wheeling diode 24 turns off the GT.
The current flowing through O11 flows from the AC output terminal 2 to the load side and charges the snubber capacitor 23. Figure 2
This is the operation mode shown in (b). Thereafter, the overcharged charges of the clamp capacitor 3 and the snubber capacitor 23 are discharged through the snubber resistors 16 and 26 and fed back to the DC power supply 1, and the mode of FIG. 2C in which the GTO 11 is turned on is shown.

Next, regarding the turn-off operation of the GTO 11, since the GTO 11 is initially in the ON state and the GTO 21 is in the OFF state, the snubber capacitor 13 has zero voltage,
The snubber capacitor 23 is charged to the power supply voltage.
At this time, the current is flowing from the DC power supply 1 through the GTO 11 to the load side from the AC output terminal 2.

When the GTO 11 is turned off from the operation mode shown in FIG. 2C, the current flowing in the GTO 11 is divided into the snubber diode 12, the snubber capacitor 13, the snubber diode 12, the clamp capacitor 3, and the snubber capacitor 23.

At this time, the clamp capacitor 3 is overcharged, but the current flowing through the snubber capacitor 23 flows so that the charge flows from the AC output terminal 2 to the load side and is used as a load current. This is the operation mode of FIG. After that, the overcharged charges of the clamp capacitor 3 and the snubber capacitor 13 are discharged through the snubber resistors 16 and 26 and fed back to the DC power supply 1 to the GTO.
11 The mode is as shown in FIG.

In such an example, the resistor for attenuating the reactor energy and the diode connected in parallel to the reactor shown in FIG. 3 are eliminated, and the snubber loss in the switching of the semiconductor switch is reduced from that of the conventional circuit. Since it has the effect of reducing by 40%, the practical effect of reducing the cost of the inverter circuit, further reducing the size, and improving the efficiency is remarkable. In addition,
Although only the turn-on and turn-off operations of the GTO 11 have been described in this description, it is clear that the load dual semiconductor switches have symmetrical operation modes.

[0020]

As described above, according to the present invention, it is possible to provide a device capable of significantly reducing snubber loss, downsizing an inverter circuit, and improving efficiency.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main configuration of an embodiment of the present invention.

2 (a), (b), (C), and (d) are explanatory views showing each operation mode of FIG.

FIG. 3 is a partial circuit diagram showing a conventional voltage source inverter.

[Explanation of symbols]

 1 DC power supply 11 Semiconductor switch (GTO) 21 Semiconductor switch (GTO) 12 Snubber diode 22 Snubber diode 13 Snubber capacitor 23 Snubber capacitor 14 Return diode 24 Return diode 3 Clamp capacitor 15 Snubber resistor 25 Snubber resistor 16 Snubber resistor 26 Snubber resistor 17 Reactor 18 Reactor 41 Reactor 42 Diode 43 Resistor

Claims (1)

[Claims] 1. A device for suppressing a surge voltage of a semiconductor switch of a voltage type inverter using a self-arc-extinguishing type semiconductor switching element, wherein a reactor for suppressing a current change is provided on a DC power source side of each semiconductor switch, and each semiconductor is provided. Connect a surge voltage suppression circuit in which a diode and a capacitor are connected in series to the switch so that the capacitor is on the output side, and connect a third capacitor between the connection point of the diode and the capacitor of both positive and negative semiconductor switches. An inverter characterized in that the positive and negative sides of the DC power supply facing both ends of the third capacitor are coupled by a husband and resistor so that the electric charge of the third capacitor can be discharged to the DC power supply. Surge suppressor for semiconductor switch in circuit.