JPH07264630A - Muse decoder motion correcting circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a field memory and suppress an accompanying increase in circuit scale by performing motion correction processing for both a luminance (Y) signal part and a color (C) signal part, and using an inverse correcting circuit for the motion correction position of the C signal part even as a circuit for video animation signal reproduction processing in common. CONSTITUTION:The motion correction processing is performed for both the Y signal part and C signal part and the C signal part after motion correction at an in-field insert part is inversely corrected. This circuit constitution is provided with a Y/C signal switching selector 9 which switches the Y signal part of an inter-frame insert signal and the C signal outputted from an in-field interpolation processing part 8. Then the C signal part still picture outputted from the in-field interpolation processing part 8 is replaced by the selector 9 with the C signal part after inter-frame interpolation and outputted as a still picture signal from a terminal 12. Therefore, the inverse correcting circuit for the C signal can be used in common as the in-field interpolation part by equalizing the delay quantity of a signal for inter-frame interpolation to those of the Y signal and C signal.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to band-compressed MUSE.
The present invention relates to a MUSE decoder that demodulates a signal into an original broadband high-definition television signal and reproduces the signal, and particularly to a motion correction processing circuit in the MUSE decoder.

[0002]

2. Description of the Related Art As a method of band-compressing a wideband high-definition television signal to a practical level for transmission, MUSE (Multiple Sub-Nyquist Sampling) is applied to the original high-definition television signal to make a sub-Nyquist sample that makes a round in four fields.
Encoding) method.

The MUSE system is a system developed by NHK (Japan Broadcasting Corporation), and various documents (for example, Yuichi Ninomiya, "MUSE-Hi-Vision transmission system", Institute of Electronics, Information and Communication Engineers, December 1, 1990). Issued), detailed description is omitted.

In the MUSE system, a luminance signal (“Y signal”)
In order to transmit a high-definition television signal (referred to as "baseband signal") having a bandwidth of up to about 7 MHz for a color signal (referred to as "C signal") on one channel of satellite broadcasting with a bandwidth of 27 MHz, Band compression processing is performed up to a width of about 8 MHz. The MUSE decoder demodulates the band-compressed signal (hereinafter referred to as "MUSE signal") into the original baseband signal.

FIG. 8 is a block diagram showing a part of a conventional MUSE decoding process. The MUSE signal is supplied to the input terminal 1. The selector 2 is a selector for inter-frame interpolation of a still image signal, and a signal of one frame before (a signal for inter-frame interpolation) 7 and a signal of the current frame are 3
Interpolation is performed by alternately switching with a sampling clock of 2 MHz.

As the signal to be interpolated, the signal one frame before which is delayed by the two field memories 3 and 4, and the motion vector signal 11 detected by the control signal detector 10 are used.
Based on the above, the Y signal portion is subjected to motion correction processing by the motion correction processing portion 5, and the output of the motion correction processing portion 5 is supplied to a contact on one side of the selector 45. Further, the C signal portion is not subjected to the motion correction processing and is supplied to the contact on the other side of the selector 45.

The MUSE signal is a TCI (Time Compressed).
Since it has been encoded, the signal form is as shown in FIG. 9, and the selector 45 in FIG. 8 switches the C signal 49 and the Y signal 50 at the X point and the Y point. The TCI is a general term for a signal system in which both the Y signal and the C signal in one line or only the C signal are time-compressed and multiplexed as a time division multiplexing system.

The motion correction process in the MUSE decoder is proposed in, for example, Japanese Patent Laid-Open No. 59-221090. According to the publication, in the motion correction process, position information obtained by adding movement information of a sample position based on a predetermined sample positional relationship between adjacent frames to the motion information detected on the encoder side (referred to as “motion vector”) is added. Based on this, the interpolation position of the sample value that is delayed and interpolated is corrected.

According to the above-mentioned document "MUSE-Hi-Vision transmission system" by Ninomiya, page 120, the motion vector is detected on the encoder side, and the obtained motion vector is transmitted as a control signal. Uses 7 bits out of 32 bits of control signal and 4
Bits are assigned to the horizontal vector and 3 bits are assigned to the vertical vector. Therefore, motion vectors in the range of +7 to -8 clocks in the horizontal direction and +3 to -4 lines in the vertical direction (see Tables 1 and 2) are transmitted.

It is also described that the C signal is not subjected to motion correction processing (page 51 of the same document). For this reason,
As shown in FIG. 8, the inter-frame interpolation signal is switched between the Y signal portion and the C signal portion by the selector 45.

As shown in FIG. 8, the conventional MUSE decoder has a structure in which a Y signal motion correction processing section 5 and a switching selector 45 for switching between the Y signal section and the C signal section are built in the field memory (broken line 6c in the figure). In many cases).

The motion correction process for performing uniform motion vector correction on the entire screen is performed by increasing or decreasing the buffer amount (for example, +3 to + vertically).
Since the correction of the range of -4 lines corresponds to the increase / decrease of the buffer amount), by the memory address control (for example, the offset of the write start address and the read start address of the memory is controlled corresponding to the motion vector), This can be achieved by increasing or decreasing the buffer amount.

The block indicated by the broken line 6c has to separately control the increase / decrease in the buffer amount of the Y signal in response to the motion vector from the control signal detection unit 10 during the motion correction, and therefore, the C signal. Normally, two tables for Y signals and C signals are separately provided. Since the field memory 3 does not need to consider the motion correction, it is composed of a FIFO type memory.

The signal interpolated by the selector 2 in FIG. 8 has the signal form shown in FIG. 10 and is output from the terminal 12 as a still image signal.

On the other hand, the signal interpolated by the selector 2 is thinned out by the selector 46 to the state before interframe interpolation, and then interpolated by the field interpolating unit 8 to be a video signal. Is output from the terminal 13.

Regarding the field interpolation processing of the moving image portion, as described in, for example, the above-mentioned document "MUSE-Hi-Vision transmission system", pages 71 to 72, it is constituted by a two-dimensional low-pass filter, and a two-dimensional low-pass filter is used. For example, a spread of taps of about 5 lines × 9 pixels is suitable.

FIG. 11 shows an example of the field interpolating process composed of a two-dimensional low-pass filter. This filter acts as a spatial interpolation filter, and the input signals input to the terminal 14 are delayed by the line memories 47 and 21 line by line for the Y signal and every two lines for the C signal. In the C signal, two color difference signals (RY, B-
For Y), since the RY signal and the BY signal are repeated for each line, a delay circuit 47 of 2H (2 horizontal scanning periods) is provided.
Is provided.

The delayed signals are 1 line delay of Y signal and 2 lines delay of C signal, 2 lines delay of Y signal and 4 lines delay of C signal, 3 lines delay of Y signal and 6 lines delay of C signal. , A 4-line delay of the Y signal and a 8-line delay of the C signal are shown in FIG. 9 at the switching points (Y point, X
Points) to switch the selectors 23, 24, 25 and 26, respectively, and obtain five signals 27, 28, 29, 30 and 31.

Of the five signals selectively output by the selectors 23 to 26, the signal 29 is converted into a horizontal low-pass filter (L
PF) 34, and the signals 28 and 30 and the signals 27 and 31 are added by adders 33 and 32, respectively, and are input to horizontal low-pass filters 35 and 36.

The output signals of the three horizontal low-pass filters 34 to 36 are mixed by an adder 37 and output from a terminal 38 as a moving image signal (field interpolation signal).

[0021]

As described above, in the MUSE decoder, since the motion correction processing is performed only on the Y signal, the inter-frame interpolation signal is the motion correction processed by the Y signal portion and the C signal portion. It is necessary to switch between and those that have not been subjected to motion correction processing.

In the case where the Y signal motion correction processing and the selector for switching between the Y signal portion and the C signal portion are built in the field memory as in the conventional example, the memory cannot be constructed only by the address control. It was not possible, and the circuit configuration was complicated.

In the conventional example shown in FIG. 8, the broken line 6
If the block indicated by c is composed of one memory, the buffer amounts of the Y signal and the C signal must be switched when the motion correction is performed. Therefore, two tables for the Y signal and the C signal are separately provided. Simple FIF required to be prepared
An O (first in, first out) type memory structure could not be formed.

On the other hand, since the field memory 3 does not need to consider the motion correction, it can be constituted by a simple FIFO type memory.

Therefore, in the MUSE decoder,
The field memory 3 and the field memory constructing the block indicated by the broken line 6c have different structures from each other, and as a result, there arises a problem that two types of memories having different structures are required.

Therefore, the present invention demodulates the MUSE signal into the original broadband high-definition television signal and reproduces it.
It is an object of the present invention to solve the above-mentioned problems in the E decoder, simplify the configuration of the field memory, and suppress the increase in circuit scale accompanying it.

[0027]

In order to achieve the above object, the MUSE decoder of the present invention uses a MUS band-compressed by sub-samples that make a cycle with a period of 4 fields.
In a MUSE decoder that demodulates an E signal into an original broadband high-definition television signal and reproduces it, a motion correction processing unit performs motion correction on both a luminance (Y) signal part and a color (C) signal part, and motion correction is performed. It is characterized in that the circuit for performing the inverse correction for the interpolated position of the generated C signal portion is also used as the reproduction processing circuit for the video / moving image signal.

As a preferred mode of the MUSE decoder of the present invention, the line processing circuit and the circuit for performing the inverse correction (referred to as "inverse correction circuit") share the line delay circuit network, and the inverse correction circuit is A first selector that selects one of a plurality of line-by-line delay outputs of the line delay circuit network based on vertical motion correction information, a circuit that horizontally reverse-corrects based on horizontal motion correction information, and one input The output of the circuit for inversely correcting in the horizontal direction is connected to the terminal, the output corresponding to the zero delay of the line delay network is connected to the other input terminal, and these two inputs are switched and output at a predetermined frequency. 2 selectors are provided.

Further, the present invention provides, as another viewpoint, a MUSE decoder in which the motion correction processing unit only performs vertical motion correction for the color (C) signal unit.

In a preferred aspect of the above-mentioned another aspect of the present invention, the line processing circuit and the inverse correction circuit for the video and moving image signal share a line delay circuit network, and the inverse correction circuit includes a plurality of line delay circuit networks for each line. A first selector that selects one of the delay outputs of the first selector based on the vertical motion correction information, the output of the first selector is connected to one input terminal, and the zero of the line delay network is connected to the other input terminal. An output corresponding to the delay is connected, and a selector for switching between these two inputs at a predetermined frequency and outputting is provided.

[0031]

According to the present invention, based on the above configuration, the memory configuration of the motion correction processing unit can be simplified, the increase in circuit scale can be suppressed, and two field memories can be configured with the same configuration memory.

Further, according to the present invention, an increase in circuit scale can be suppressed by the circuit configuration in which the line processing circuit is shared by the video processing signal reproduction processing circuit and the inverse correction circuit. Then, the inverse correction circuit switches the current frame that is not inversely corrected for the C signal portion and the signal that is not motion-corrected by the inverse correction by the selector, and outputs the output of the inverse correction circuit of the signal interpolated between frames. It is replaced with the C signal part and output as a still image signal.

According to another aspect of the present invention, the motion correction processing unit only performs vertical motion correction on the C signal unit, thereby simplifying the structure of the inverse correction circuit.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

[0035]

[Embodiment 1] A first embodiment of the present invention will be described with reference to FIGS.
Also, description will be made with reference to Tables 1 to 3.

As described above, the inter-frame interpolation signal is obtained by subjecting the signal one frame before to the motion correction processing. In the conventional example, only the Y signal portion is subjected to the motion correction processing, but in the present embodiment, both the Y signal portion and the C signal portion are subjected to the motion correction processing, and the C is subjected to the motion correction by the field interpolating portion. Inverse correction of the signal part is performed.

FIG. 1 is a block diagram showing the configuration of this embodiment. As shown in the figure, in the configuration of the present embodiment, the Y / C signal switching selector 45 for interframe interpolation signals in the conventional example does not exist, and the Y of interframe interpolation signals is set.
A major difference from the conventional example shown in FIG. 8 is that a Y / C signal switching selector 9 for switching between the signal section and the C signal output from the field interpolation processing section 8 is added.

In this embodiment, since the buffer amounts of the Y signal portion and the C signal portion are the same, the block indicated by the broken line 6a is
If address control is performed in consideration of the motion vectors shown in Tables 1 and 2, a FIFO type memory can be used.

FIG. 2 shows the signal form after interpolating between frames by the selector 2 of FIG. As shown in FIG. 2, since all the previous frame data are motion-corrected, the C signal portion and the Y signal portion have the same form. In FIG. 2, the point ◯ represents the data of the current frame, and the point x represents the frame data of one frame before the motion correction.

In the MUSE decoder processing, in the C signal portion still image signal, the data at the X point of the C signal portion shown in FIG. 2 needs to be the data of the previous frame that has not been motion-corrected, and therefore this data is required. It is necessary to correct the interpolation position for the data in the opposite direction to the motion correction. Since the inverse correction amount may be temporally opposite to the motion correction amount, it has the values shown in Table 1 in the horizontal direction and Table 2 in the vertical direction.

By the way, as described in the conventional example, the field interpolation for a moving image has a two-dimensional low-pass filter structure as shown in FIG. 11, and the C signal is delayed every two lines.

If the delay for each two lines in the two-dimensional low-pass filter is divided for each line as shown in FIG. 3, the data B to I with a delay of 1 to 8 lines can be extracted for each line of the input signal. In this embodiment, this B
Inverse correction of the C signal that has been vertically motion-corrected using the I signal component is performed.

In FIG. 1, the signal input to the field interpolating unit 8 is a signal that is not thinned out, unlike the conventional example (FIG. 8) in order not to erase the data inter-frame interpolated.

The field interpolation processing section 8 will be described with reference to FIG.

The signal input to the terminal 14 is 1H in the 1H (1 horizontal scanning period) line memory 15 for the C signal portion.
Data B to I delayed by 1 to 8 lines are obtained for each line. C
Regarding the signal part, the inverse correction of the vertical motion correction performed in the motion correction processing block 6a is performed by the control signal detection part 10
This is performed by switching the selector 16 on the basis of the vertical motion vector signal from the above and selecting any one of the data B to I.

Table 3 shows the vertical motion vector and the selector 16
Indicates the correspondence of the data selected with. Selector 16 is shown in Table 3
Accordingly, when the motion correction processing block 6a performs vertical motion correction of, for example, +3 lines, the selector 16 selectively outputs the signal B delayed by -3 lines from the center position E point.

Next, the horizontal motion correction reverse correction processing unit 17 performs reverse correction in the horizontal direction on the signal output from the selector 16. The inverse correction processing unit 17 for horizontal motion correction performs the inverse correction for each pixel shown in Table 1 based on the horizontal motion vector signal from the control signal detection unit 10.

C of the signal subjected to vertical / horizontal inverse correction
The signal part has the form shown in FIG. FIG. 4 shows a signal form of the output of the horizontal motion correction / inverse correction processing unit 17 of FIG. In the figure, point Δ represents the previous frame data returned to the state where the motion correction processing is not performed by the inverse correction circuit, and point □ represents the current frame data that is inversely corrected.

In the signal form of FIG. 4, since the data of the current frame is inversely corrected, it cannot be used as the C signal portion still image signal. The data of the current frame which has not been subjected to the motion correction processing is input from the input terminal 1 to the field interpolation processing section 8 via the selector 2 and is subjected to the inverse correction.

Therefore, in the field interpolation processing section 8 shown in FIG. 3, the data E at the central position in time is input to the contact on one side of the selector 18 as the data of the current frame, and the horizontal motion correction reverse correction is performed. The output of the processing unit 17 is input to the contact on the other side of the selector 18, and the selector 18 outputs 32 MH.
The output is switched by the z sampling clock.

The data thus obtained has the form shown in FIG. 5, and C after the inter-frame interpolation shown in FIG. 10 of the conventional example.
Signal part Same as still image signal. In FIG. 5, point ◯ represents the current frame data obtained from point E, which is at the center position in time of FIG. 3, and point Δ represents the previous frame data that has been subjected to no motion processing by inverse correction. Is Figure 4
Corresponds to the point.

On the other hand, in the field interpolation of the moving image in FIG. 3, the data A for the C signal is thinned out by the selector 20, and the data C, E, G, I are thinned out by the selector 22, respectively.
The Y signal is subjected to field interpolation by a two-dimensional low-pass filter after thinning data A by the selector 20 to restore the signal state before inter-frame interpolation. The basic configuration of the two-dimensional low-pass filter is the same as that of the conventional example described above, and therefore the description is omitted.

In FIG. 1, the field interpolation processing unit 8
The C signal portion still image signal output from the above is replaced with the C signal portion of the signal after inter-frame interpolation by the selector 9 and output from the terminal 12 as a still image signal.

Therefore, according to the above-mentioned first embodiment of the present invention, the delay amount of the inter-frame interpolation signal is made the same for the Y signal and the C signal, and the inverse correction of the C signal (return processing for motion correction is performed. ) Can be shared with the field interpolator, it is possible to suppress an increase in circuit scale and configure the two field memories 3 and 4 with the same FIFO type memory. For this reason,
In the present embodiment, the circuit configuration of the memory can be simplified and the cost can be reduced, as compared with the conventional example which requires two memories having different configurations.

[0055]

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS.

FIG. 6 shows an MU according to the second embodiment of the present invention.
FIG. 8 is a block diagram showing an SE decoding process, and FIG. 7 is a block diagram of a field interpolation unit of the MUSE decoder according to the second embodiment of the present invention.

In FIG. 6, the inter-frame interpolation signal is obtained by subjecting the signal one frame before to the motion compensation process. In this embodiment, the vertical motion compensation processing unit 43 outputs Y.
Vertical motion correction is applied to both the signal part and the C signal part, and an output signal of the vertical motion correction processing part 43 is subjected to horizontal motion correction in the horizontal motion correction processing part 44 for the Y signal part, C
A signal that is not subjected to horizontal motion correction processing in the signal portion is a signal for interframe interpolation.

The selector 45 switches between the Y signal and the C signal as in the conventional example.

In the structure of the present embodiment, the block shown by the broken line 6b can be composed of a FIFO type memory if address control is performed in consideration of the vertical motion correction amount shown in Table 2.

In this embodiment, unlike the first embodiment, it is only necessary to perform the inverse correction of only the vertical motion correction on the signal after the inter-frame interpolation. The inverse correction of the vertical motion correction is performed using the circuit of the field interpolation processing unit 8 as in the first embodiment.

The field interpolation processing unit 8 of this embodiment is
As shown in FIG. 7, the horizontal motion correction reverse correction processing unit 1 of FIG.
The difference from the configuration of the first embodiment is that there is no 7. Then, the output of the selector 16 for selecting any one of the signals B to I to perform vertical motion correction and the output of the point E are connected to the contacts of the selector 18, respectively. The other circuit configuration is the same as that of the first embodiment.

In the present embodiment, the field interpolation processing unit 8
In the preceding stage, since the horizontal motion correction process is performed only on the Y signal, the horizontal inverse correction is not performed on the C signal. It should be noted that the inverse correction for the vertical motion correction is performed by the first
The description is omitted because it is the same as the embodiment.

Therefore, also in the above-described second embodiment of the present invention, the delay amount of the inter-frame interpolation signal is made the same for the Y signal and the C signal, and the inverse correction of the C signal (return processing for vertical motion correction is performed. ) Can be shared with the field interpolation processing section, it is possible to suppress an increase in circuit scale and to configure two field memories with the same FIFO type memory.

Although the present invention has been described above with reference to various embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various embodiments according to the principle of the present invention are included.

Table 1 is a correspondence table showing horizontal motion vectors and their corresponding inverse correction amounts, and Table 2 is a correspondence table showing vertical motion vectors and their corresponding inverse correction amounts.
Table 3 is a correspondence table showing the vertical motion vector and the data selected by the selector 16.

[0066]

[Table 1]

[0067]

[Table 2]

[0068]

[Table 3]

[0069]

As described above, the present invention is based on MUSE.
The motion correction processing of the decoder is performed on both the Y signal portion and the C signal portion, and the inverse correction circuit for the correction position of the motion correction of the C signal portion is configured to be shared with the circuit of the video / video signal reproduction processing. The field memory in the block can be configured by a simple FIFO type memory, the memory configuration is simplified, an increase in circuit scale is suppressed, and cost reduction is achieved.

Further, according to the present invention, since the field interpolation circuit for moving images and the inverse correction circuit share the line delay circuit, it is possible to suppress an increase in circuit scale. Then, the inverse correction circuit switches the current frame that is not inversely corrected for the C signal portion and the signal that is not motion-corrected by the inverse correction by the selector, and outputs the output of the inverse correction circuit of the signal interpolated between frames. It is replaced with the C signal part and output as a still image signal.

According to another aspect of the present invention, the C signal section is configured to perform only vertical motion correction processing, thereby eliminating the need for the horizontal motion correction circuit in the inverse correction circuit, and eliminating the need for the inverse correction circuit. The circuit configuration is simplified. Further, also in the MUSE decoder of another aspect of the present invention, there is an effect that the memory configuration in the motion correction processing block is simplified, an increase in circuit scale is suppressed, and cost reduction is achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a signal form of the first embodiment of the present invention.

FIG. 3 is a block diagram showing field interpolation processing according to the first embodiment of this invention.

FIG. 4 is a schematic diagram showing a signal form of a C signal region according to the first embodiment of the present invention.

FIG. 5 is a schematic diagram showing a signal form of a C signal region according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a second embodiment of the present invention.

FIG. 7 is a block diagram showing field interpolation processing according to the second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional MUSE decoder.

FIG. 9 is a schematic diagram showing a signal form of a MUSE signal.

FIG. 10 is a schematic diagram showing a signal form after inter-frame interpolation.

FIG. 11 is a block diagram showing field interpolation processing in a conventional MUSE decoder.

[Explanation of symbols]

1 ... MUSE signal input terminal 2 ... Interframe interpolating selector 3, 4 ... Field memory 5 ... Motion correction processing unit 6a, 6b, 6c ... Corresponding processing block in field memory 7 ... Interframe interpolating signal 8 ... Field Interpolation processing unit 9 ... Y / C signal switching selector 10 ... Control signal detection unit 11 ... Motion vector signal 12 ... Still image signal output terminal 13 ... Video signal output terminal 14 ... Input terminal 15 ... C signal 1H line memory 16 ... C signal reverse correction selector 17 ... Horizontal motion correction reverse correction processing unit 18 ... Selector 19 ... C still image output terminal 20 ... Video thinning selector 21 ... Y signal 1H line memory 22 ... C video thinning selector 23, 24, 25 , 26 ... Y / C signal switching selector 27, 28, 29, 30, 31 ... Two-dimensional filter data 32, 33 ... Calculator 34, 35, 36 ... Horizontal low-pass filter 37 ... Adder 38 ... Movie output terminal 39 ... Current frame data 40 ... Previous frame data 41 subjected to motion correction processing 41 ... Previous frame data without motion correction processing 42 ... Current after inverse correction Frame data 43 ... Vertical motion correction processing unit 44 ... Horizontal motion correction processing unit 45 ... Y / C signal switching selector 46 ... Movie thinning-out selector 47 ... C signal 2H line memory 48 ... Sync signal 49 ... C signal 50 ... Y signal A Input data to the field interpolator B ... 1 line delay data of data A C ... 2 line delay data of data A D ... 3 line delay data of data A E ... 4 line delay data of data A F ... Data A delayed by 5 lines G ... Data A delayed by 6 lines H ... Data A delayed by 7 lines I ... Data A 8 lines behind data X point ... C signal start point in one line of MUSE signal Y point ... Y signal start point in one line of MUSE signal

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Claims (4)

[Claims] 1. In a MUSE decoder for demodulating and reproducing an original wide band high-definition television signal from a MUSE signal band-compressed by sub-samples that make a cycle of four field cycles, a motion compensation processing section includes a luminance signal section and a luminance signal section. A MUSE decoder characterized in that a circuit for performing motion correction for both of the color signal parts and performing inverse correction for an interpolation position of the motion-corrected color signal parts is also used as a reproduction processing circuit for a video / video signal. 2. The MUSE decoder according to claim 1, wherein the motion correction processing unit only performs vertical motion correction for the color signal unit. 3. A line delay circuit network is shared by the reproduction processing circuit for the video and moving image signal and the circuit for performing the inverse correction (referred to as "inverse correction circuit"), and the inverse correction circuit is a circuit of the line delay circuit network. A first selector that selects any one of a plurality of delay outputs in line units based on vertical motion correction information;
A circuit for reversely correcting in the horizontal direction based on horizontal motion correction information, an output of the circuit for reversely correcting in the horizontal direction is connected to one input terminal, and the other input terminal is equivalent to the zero delay of the line delay circuit network. 2. The MUSE decoder according to claim 1, further comprising a second selector which is connected to the outputs of the above and outputs the two inputs switched at a predetermined frequency. 4. The line processing circuit and the inverse correction circuit share the line delay circuit network, and the inverse correction circuit is any one of a plurality of line-by-line delay outputs of the line delay circuit network. A first selector for selecting one on the basis of vertical motion correction information, an output of the first selector is connected to one input terminal, and an output corresponding to zero delay of the line delay network is connected to another input terminal. 3. The MUSE decoder according to claim 2, further comprising a selector that is connected and outputs these two inputs by switching them at a predetermined frequency.