JPH07264259A - Frame transfer circuit - Google Patents

Abstract

PURPOSE:To reduce a memory data capacity required for address control by delaying required bit number of a reference timing signal at a shift register to generate a write address to a twoplane memory and setting a read address to be a fixed value based on the reference timing signal. CONSTITUTION:The circuit is provided with a write counter 7 to generate a write address to a control section 2 and with a shift register 8 delaying a reference timing signal FT to the counter 7. Furthermore, an address to a timing ROM 3 being a read address set to be a fixed address by only the count value from a frame counter 1 is given to the control section 2. Then a write address by a write counter to a 2-plane memory 5 is made variable by changing the signal FT by the register 8. On the other hand, a read address by a read address generating section (counter 1 and ROM 3) receiving the signal FT is fixed, then timing data required for reading the memory 5 are minimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame switching circuit, and more particularly to a circuit for switching between different types of frames in a digital transmission device.

[0002] In a digital transmission apparatus, it is necessary to process various frames conforming to the transmission frame structure standard, and for this purpose, a frame transfer circuit is required.

[0003]

2. Description of the Related Art FIG. 9 shows a conventionally used frame transfer circuit. Reference numeral 1 denotes a frame counter for counting a reference timing signal FT synchronized with a data frame cycle. The count value of is sent to the write / read controller (R / W CONT) 2 as a write address.

Further, the count value of the frame counter 1 is given to a timing ROM 3 for controlling an address together with control information corresponding to various frames to be changed,
Correspondingly, a read address stored in advance for changing frames is given to the control section 2 from the ROM 3.

The reference timing signal FT is a surface switching circuit (B
NK) 4 to generate a switching control signal, which is supplied to the controller 2 and the two-sided memory 5.

In response to the switching control signal, the control unit 2 gives a write address to one of the two-sided memory (RAM) 5 (which is in an enabled state by the switching control signal) to write data and read out a read address of 2. The data is read out by giving it to the other of the surface memory 5 (which is also enabled by the switching control signal).

As a result, the input data has been subjected to frame transfer as data.

Further, in the case where speed conversion is required before such a frame change, in the speed conversion circuit 6 provided in the front stage of the two-sided memory 5, a frame aligner (FA) is provided before writing data in the memory 5. Performs processing to add functions and establish synchronization.

[0009]

[Problems to be Solved by the Invention]

(1) In the above-mentioned conventional example, the timing ROM 3 for controlling the two-sided memory 5 needs to store various control timings according to the frame configuration of the data to be changed as described above. A capacity of several kilobytes to several megabytes is required depending on the control timing to be set.

This is because the reference timing is fixed and a plurality of read timings are stored in the ROM 3 with respect to one write timing, so that there is a problem that the data capacity increases.

(2) Also, the speed conversion circuit 6 shown in FIG.
FIG. 10 shows a conventional example of E. In this conventional example, E
The speed conversion is performed using an S (elastic store) 61. A parity operation unit 62 is provided after this ES 61 to perform a parity check of input data and insert the data into the data. Detection unit 6
In step 4, it is detected whether or not the data is normal, and this data is sent to the two-sided memory 5.

FIG. 11 shows a concrete configuration example of the ES 61 and the parity calculation unit 62 in FIG.
The ES 61 has a built-in R / W individual counter (not shown), and the control circuit 60 controls writing of data by WI (write inhibit) and WR (write reset), and the internal data is read as needed. Written to memory. The reading side reads data from the head of the internal memory by RI based on RR (read reset).

Therefore, the data cannot be read out by designating only a certain address, and only the data after the speed conversion can be processed next. That is, the parity calculator 62 uses the ES
Since it is located after 61, the printed circuit in FIG. 10 has a problem that the parity detection unit 63 cannot detect the failure even if the ES 61 fails.

Therefore, an object of the present invention is to provide a frame transfer circuit in which the capacity of a timing ROM for generating an address to a two-sided memory is reduced.

Another object of the present invention is to make it possible to detect a failure in the built-in memory in such a speed conversion circuit for input data to the two-sided memory of the frame transfer circuit.

[0016]

To achieve the above object, a frame transfer circuit according to the present invention includes a shift register for delaying a reference timing signal synchronized with a data frame period by a predetermined number of bits, and a shift register for the shift register. A write counter that generates the write address by an output signal, a read address generator that counts the reference timing signal and generates a fixed read address, and writes the data by the write address and by the read address. A two-face memory for reading the data and a face switching circuit for controlling the face switching of the two-face memory based on the reference timing signal are provided.

Further, in the above frame transfer circuit, the shift register is a variable shift register, and control information which causes a bit delay amount of the variable shift register corresponding to a plurality of transfer modes is inputted as an address in advance. A ROM for reading the written set value of the shift register delay stage number may be provided.

Further, in the above frame transfer circuit, when there is a temporal regulation that the switching timing of the shift register is at least one frame later, the ROM
A RAM for controlling the switching timing is connected to the
It is also possible to make the number of stages of the shift register variable by controlling the read timing of.

Further, in the above frame changing circuit, the ROM and the RAM can be operated by counters which operate with the reference timing signal.

Further, in the frame transfer circuit described above, a timing adjusting unit may be provided to match the phase of the reference timing signal to the read address generating unit with the reference timing signal output from the shift register.

On the other hand, in the above frame changing circuit, a speed conversion circuit can be provided in front of the two-sided memory, and in this case, the speed conversion circuit performs dual memory side switching and speed conversion based on a reference timing signal. .Port memory and writing / writing of the dual port memory
A read control circuit, a latch circuit for latching read data in the previous state of the dual port memory, and write data and read data of the dual port memory are switched to the dual port memory. A selector for overwriting and a parity operation circuit for performing a parity operation on the read data at the time of writing the last data are provided.

A relay having the same control signal and logic element may be used instead of the selector.

[0023]

In the present invention, the write address by the write counter for the two-sided memory can be made variable by changing the reference timing signal by the shift register.

On the other hand, since the read address generated by the read address generation unit that receives the reference timing signal is fixed, the timing data necessary for reading the two-sided memory can be minimized, and the read address generation unit can read the same. A lot of memory capacity can be reduced.

Further, since the operation of the reference timing signal and the control information can be regulated by using the delay ROM which makes the shift register variable and determines the number of stages, the read address generating section can be realized with a small capacity memory.

Further, in the present invention, the dual port memory has two ports, each having an independent address, control system and I / O system. The address can also be read / written independently.

Paying attention to the function of such an independent I / O system, writing and reading are simultaneously performed on the input / output data bits on the writing side. That is, the data for speed conversion is once written, and when the next data is written in another input / output data bit, the previously written data is overwritten in the same read address.

By repeating this, the parity operation is performed from the first bit at which the nth last data is started to be written, and it is written into the memory at any time, and the written data is
It is read at the same time as the speed-converted data and output in accordance with the surface switching signal.

Therefore, the parity operation can be performed at the same time when the speed conversion is performed.

[0030]

FIG. 1 shows an embodiment of a frame transfer circuit according to the present invention. The difference between this embodiment and the embodiment of FIG. 9 is that a write address for the control unit 2 is generated. The point is that the write counter 7 is provided and the shift register 8 that delays the reference timing signal FT to the write counter 7 is provided.

Furthermore, the read address fixed to the timing ROM 3 as the count value from the frame counter 1 is given to the control unit 2. The frame counter 1 and the timing ROM 3
And constitute a read address generator.

The shift register 8 is composed of a variable shift register, and the shift register stage number determining unit 9 is provided.
The number of stages is controlled by. The shift register stage number determining unit 9 can be composed of a ROM, and control information is given to its address so that it can support a plurality of frame transfer modes.

Further, when there is a temporal regulation that the switching timing of the shift register 8 is at least one frame later, the determining unit (ROM) 9 controls the switching timing R.
The number of stages of the shift register can be made variable by connecting AM and controlling the read timing of the RAM.

Further, these ROM and RAM are each operated by a counter which operates with the reference timing signal.

A timing adjusting unit 10 is provided to match the phase of the reference timing signal FT to the frame counter 1 with the reference timing signal FT output from the shift register 8.

The operation of the above embodiment will be described below with reference to the time charts shown in FIGS.

In FIG. 2, reference timing signal FT
Is a reference signal FT delayed by several bits from the reference timing signal FT through a timing adjusting unit 10 that performs a phase adjustment process according to the characteristics of the variable shift register 8, and is supplied to the frame counter 1 and sent to the surface switching circuit 4. And becomes a surface switching timing signal and is given to the control unit 2 and the two-surface memory 5.

Next, as shown in FIG. 2, when data is extracted from the beginning based on the reference signal FT, the variable shift register 8 controlled by the shift register stage number determining unit 9 delays it by several stages. The signal output from the variable shift register 8 is used as a reference signal FT so as to match the reference signal signal FT.

The output of the counter 7 which operates on the basis of the reference signal FT is used as it is as the write side address of the two-sided memory 5. In addition, the timing ROM 3 is determined by the count value of the frame counter 1 which operates according to the reference signal FT
The output value from the ROM 3 becomes the address on the reading side of the two-sided memory 5.

That is, the write timing of the two-sided memory 5 is changed by the shift register stage number determining unit 9 and the variable shift register 8, and the read timing is fixed by setting only the count value from the frame counter 1 as the input to the ROM 3. Then, it is possible to read the data in which the frame is changed from the input data like the data of FIG.

FIG. 3 shows a case where data is extracted from other than the beginning, and the number of stages of the variable shift register 8 is changed by the setting of the shift register stage number determining unit 9 to delay the reference signal FT (8 in this example). Bit delay)
Shift the beginning of the write address.

On the other hand, since the read timing by the reference signal FT does not change, the output data after frame change can be read like the data in FIG.

Even when the partial data to be read is different as shown in FIGS. 2 and 3, it is sufficient to store one read timing in the timing ROM 3. Further, the read address output from the timing ROM 3 can be controlled only by the value of the frame counter 1.

The shift register stage number determining unit 9 can meet all conditions by forming a combination circuit of a ROM or a memory depending on the switching factor of the control information and the nature of the signal.

Here, as shown in FIGS. 4 and 5, the data of the system A (data when 8 bits are 1 TS (time slot) and 24 TS is one frame) is a frame of the system B (1 frame = 2048). Consider the case of inserting into a certain bit in (bit).

There are two types of control information at this time: (1) the transmission rate of the system A and (2) which bit of the frame on the system B side to insert (frame change).

For example, assume that system A data has two transmission rates of 64 kbps and 192 kbps (semi-fixed).
Then, at 192 kbps, three TSs such as TS1 to 3 and 4 to 6 are read, and the frame is changed to the system B side frame.

At this time, in the conventional example, the case of 64 kbps is n.
Assuming that there are m ways at 192 kbps, a total of n
It was necessary to store + m read timings in the timing ROM 3.

However, in the present invention, 64 kb
It is only necessary to store two types of timing information for ps and 192 kbps.

As described above, when extracting the data of TS4 from 64 kbps, the above control information (1) and (2) are input to the address of the ROM constituting the shift register stage number determining unit 9 and written in this ROM in advance. The write counter is operated from the beginning of TS4 by outputting the reference timing thus set.

Further, even if there is a time limit, it can be easily dealt with by once storing it in the memory and performing the processing.

FIG. 6 shows an embodiment of the speed conversion circuit 6 used in the frame transfer circuit according to the present invention, in which 10 is a dual port (DP) RAM,
The write / read counter (not shown) of the RAM 10 is operated by inputting the reference timing signal FT via the control circuit 11, and the address value is input to the lower address and the surface switching signal is input to the upper address of the RAM 10. .

The RAM 10 has two ports, and has an independent address, a control system for CS (chip select), WE (write enable), and OE (out enable) and an I / O system. There is. Unlike ES, each port can independently read / write to any address in the memory.

Paying attention to the function of the independent I / O system, writing and reading are simultaneously performed with respect to the input / output data bits of the memory side on the writing side. That is, the data for speed conversion is once written, and when the next data is being written to another input / output data bit, the previously written data is read and overwritten at the same address.

By repeating this, the parity operation is performed from the first bit where the n-th last data is started to be written, and the data is written into the RAM 10 at any time.

The written data is read at the same time as the speed-converted data and is output in accordance with the surface switching.

This will be described with reference to an example of speed conversion as shown in the time chart of FIG. 7. On the writing side of the RAM 10, when writing the first data A in the input data into the input / output data bits, the selector 13 of FIG. Selects and writes the data A to the port D ₀ , while the other ports D ₁ to
D ₃ (bits to) writes some data latched by the flip-flop 12.

Next, when writing the second data B into the input / output data bit (that is, in the next frame), the data A of the input / output data bit written first is read and written to the same address. That is, when writing new data, the other input / output data bits always overwrite the previous data.

The parity operation circuit is controlled so as not to operate until the last data is written, and the operation is started simultaneously with the writing.

The calculation result is stored in the RAM 10 at any time and is output simultaneously with the data reading. By doing this, RA
Parity can be inserted from the input side of M10.

It should be noted that instead of the above selector 13, FIG.
It can be replaced with a relay as shown in Fig. 1 and the control signal and the like have a common function.

[0062]

As described above, according to the frame transfer circuit of the present invention, the reference timing signal is bit-delayed by the shift register as necessary to generate the write address for the two-sided memory, while the read address is used. Is configured to be set to a fixed value based on the reference timing signal, so that the memory data capacity required for address control can be reduced and the number of man-hours for creating the memory can be reduced.

Further, by providing the speed conversion circuit for performing the parity calculation simultaneously with the speed conversion in the preceding stage of the two-sided memory, it is possible to detect the failure in the speed conversion circuit and to improve the design quality at the device and shelf level. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frame transfer circuit according to the present invention.

FIG. 2 is a time chart diagram showing the operation (when extracting from the beginning of data) of the frame transfer circuit according to the present invention.

FIG. 3 is a time chart showing the operation of the frame transfer circuit according to the present invention (when extracting from a portion other than the beginning of data).

FIG. 4 shows a frame transfer circuit according to the present invention,
It is a time chart figure which shows the example (1) of the frame transfer performed between two systems.

FIG. 5 is a frame transfer circuit according to the present invention,
It is a time chart figure which shows the example (2) of the frame transfer performed between two systems.

FIG. 6 is a block diagram showing an embodiment (1) of a speed conversion circuit used in the frame transfer circuit according to the present invention.

FIG. 7 is an operation time chart diagram of the embodiment (1) of the speed conversion circuit.

FIG. 8 is a block diagram showing an embodiment (2) of the speed conversion circuit used in the frame transfer circuit according to the present invention.

FIG. 9 is a block diagram showing a configuration example of a conventional frame transfer circuit.

FIG. 10 is a block diagram showing a configuration example of a conventional speed conversion circuit.

FIG. 11 is a block diagram showing a more specific configuration example of a conventional speed conversion circuit.

[Explanation of Codes] 1 frame counter 2 writing / reading control unit 3 timing ROM 4 surface switching circuit 5 2 surface memory (RAM) 6 speed conversion circuit 7 writing counter 8 variable shift register 9 shift register stage number determining unit (ROM) 10 Timing Adjustment Unit In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (7)

[Claims] 1. A shift register for delaying a reference timing signal synchronized with a frame period of data by a predetermined bit, a write counter for generating the write address by an output signal of the shift register, and counting the reference timing signal. Of the two-sided memory based on the reference timing signal, a read-out address generating section for generating a fixed read-out address, a two-sided memory for writing the data at the write-in address and reading the data at the read-out address. A frame switching circuit comprising a surface switching circuit that controls surface switching. 2. The frame transfer circuit according to claim 1, wherein the shift register is a variable shift register, and control information that causes a bit delay amount of the variable shift register is addressed corresponding to a plurality of transfer modes. And a ROM for reading the shift register delay stage number set value that has been input as 3. The frame transfer circuit according to claim 2, wherein when there is a temporal regulation that the switching timing of the shift register is at least one frame later, the R
A RAM for controlling the switching timing is connected to the OM and the R
A frame transfer circuit characterized in that the number of stages of the shift register is made variable by controlling the AM read timing. 4. The frame transfer circuit according to claim 3, wherein the ROM and the RAM are operated by counters that operate according to the reference timing signal. 5. The frame transfer circuit according to claim 1, wherein a timing adjustment for matching the phase of the reference timing signal to the read address generation unit with the reference timing signal output from the shift register. A frame transfer circuit characterized by having a section. 6. The frame transfer circuit according to claim 1, wherein a speed conversion circuit is provided in front of the two-sided memory.
A dual port memory in which the speed conversion circuit performs memory plane switching and speed conversion based on a reference timing signal; a write / read control circuit for the dual port memory; and a front of the dual port memory. A latch circuit for latching read data in the state of, and a selector for switching between write data and read data of the dual port memory and overwriting the dual port memory.
And a parity operation circuit that performs a parity operation on the read data at the time of writing the last data. 7. The frame transfer circuit according to claim 6, wherein a relay having the same control signal and logic element is used instead of the selector.