JPH07263967A - Output circuit - Google Patents

Abstract

PURPOSE:To surely drive a load and to reduce the power consumption by providing a circuit, which absorbs the negative potential generated at the time of the occurrence of a counter-electromotive force, to prevent the malfunction due to the counter-electromotive force. CONSTITUTION:An output transistor TR 24 is turned on/off by an input signal IN, and the base current proportional to an output terminal voltage Vo is supplied from a base current adjusting circuit 2. If a negative potential detecting circuit 3 detects that the voltage Vo is reduced to a negative potential lower than a power source GND, a current I is supplied to an output terminal 1 from a negative potential absorbing circuit 4 to absorb the negative potential. Thus, the base current proportional to the output terminal voltage Vo is supplied to the output TR and supply of the unnecessary base current is prevented to reduce the power consumption, and the negative potential of the output voltage is absorbed and the malfunction of the load, which generates a counter- electromotive force at the time of reversing of a motor or the like, is prevented to surely drive the load.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an output circuit for driving a load such as a motor.

In recent years, various types of electronic devices using small motors have been put into practical use. In such electronic devices,
It is necessary to secure a stable load driving capability without being influenced by the characteristics of the load.

[0003]

2. Description of the Related Art An example of a semiconductor device having an output circuit for driving a motor will be described with reference to FIG.

The input signals IN1 and IN2 are pulse signals having opposite phases. The H level of the input signal IN1 is the power supply Vcc level, and the L level is a level lower than the power supply Vcc by the emitter-base voltage drop VEB of the PNP transistor Tr7 or more.

The L level of the input signal IN2 is the ground GND level, and the H level is the NPN transistor T.
The level is higher than the base-emitter voltage drop VBE of r3.

The PNP transistors Tr1 and Tr2 are always turned on by the operation of the current source 1a. In this state, when the input signal IN1 becomes L level and the input signal IN2 becomes H level, the NPN transistor Tr3 is turned on and the NPN transistor Tr3 is turned on.
The base potentials of the transistors Tr4 and Tr6 drop and the NPN
The base current IB1 supplied to the transistor Tr9 decreases and the transistor Tr9 is turned off.

Further, the transistor Tr7 is turned on and the NPN transistor Tr8 is turned on. Therefore, the output current Io1 is supplied to the motor M from the output terminal T1.
The output terminal T2 connected to the motor M is an output terminal of another output circuit driven in a reverse phase to this output circuit. When the output current Io1 flows through the motor M due to the operation of both output circuits, the motor M is normally rotated, for example.

On the other hand, when the input signal IN1 is at the H level and the input signal IN2 is at the L level, the off operation of the transistor Tr3 raises the base potentials of the transistors Tr4 and Tr6 and the base IB1 supplied to the transistor Tr9 increases. Then, the transistor Tr9 is turned on.

The transistor Tr7 is turned off and the transistor Tr8 is turned off. Therefore, the motor M
The output current Io2 flows from the output terminal T1 to the output terminal T1, and the motor M is reversely rotated. Then, such an output circuit is formed on one chip constituting the semiconductor device.

In the output circuit as described above, when the transistor Tr9 is turned on and the motor M is in a light load state and the output terminal voltage Vo drops, the emitter potential of the PNP transistor Tr5 drops and the transistor Tr4. , T
The base potential of r6 decreases, and the base current IB1 supplied to the transistor Tr9 decreases.

Therefore, as shown in FIG. 14, as the output terminal voltage Vo decreases, the base current IB1 also decreases.
As shown in (1), the base current IB1 decreases as the output current Io2 decreases.

By such an operation, the base current IB1 is prevented from flowing unnecessarily when the load is light, and the power consumption is reduced.

[0013]

In the above output circuit, the transistor Tr8 is turned on to output the output current Io1.
When the transistor Tr9 is turned on and the output current Io2 is passed to reverse the rotation direction of the motor M from the state where the current is flowing, the potential of the output terminal T1 is grounded by the back electromotive force generated in the motor M. The following negative potentials may occur.

At this time, the NPN transistor Tr10 is parasitic between the P-type substrate and the N-type well of this chip, and a current flows from the bases of the transistors Tr6 and Tr7 to the collector of the transistor Tr9.

Then, the transistor Tr8 is not sufficiently turned off, and the output current Io2 does not flow sufficiently, so that the motor M cannot be driven reliably. Therefore, the system using the motor M may malfunction.

An object of the present invention is to provide an output circuit capable of reliably driving a load generating a counter electromotive force while reducing power consumption.

[0017]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, the collector of the output transistor Tr24 is connected to the output terminal T1 and the emitter is connected to the low-potential-side power supply GND, and the output transistor Tr24 is driven on / off based on the input signal IN to set the output terminal voltage Vo. A base current adjusting circuit 2 is provided for supplying a proportional base current to the output transistor Tr24. When the output terminal voltage Vo is the low potential side power supply GND
A negative potential detection circuit 3 that detects a decrease in the negative potential below, and a negative potential absorption circuit that supplies a current I to the output terminal T1 based on an output signal of the negative potential detection circuit 3 to absorb the negative potential. 4 is provided.

Further, as shown in FIG. 2, the base current adjusting circuit is connected to the base of the output transistor Tr24 in a Darlington connection to supply a transistor Tr20 for supplying a base current to the output transistor Tr24 and the output terminal voltage Vo. A proportional base current is applied to the transistor Tr2.
Output potential detection circuits Tr17, Tr18, Tr19 supplied to 0
The negative potential detection circuit is composed of transistors Tr16 and Tr15 which are turned off when the output terminal voltage Vo becomes a negative potential based on the output signals of the output potential detection circuits Tr17, Tr18 and Tr19. An output current Io1 for absorbing a negative potential is supplied from the negative potential absorbing circuit 4 to the output terminal T1 based on the OFF operation of the transistors Tr16 and Tr15.

As shown in FIG. 2, the negative potential absorbing circuit is connected to the transistor Tr21 which is turned on when the transistors Tr16 and Tr15 are turned off, and Darlington connection to the transistor Tr21.
The output current I is turned on when the r21 is turned on.
The transistor Tr23 supplies o1 to the output terminal T1.

Further, as shown in FIG. 7, the negative potential absorption circuit is connected to the transistor Tr21 which is turned on when the transistors Tr16 and Tr15 are turned off, and Darlington connection to the transistor Tr21.
The output transistor Tr24 is turned on in the opposite direction based on the turning-on operation of r21 and supplies the output current Io1 to the output terminal T1.

Further, as shown in FIG. 6, the output potential detecting circuits Tr17, Tr18, Tr19 have a negative potential detecting circuit Tr1 at the time of saturation operation of the negative potential detecting circuits Tr16, Tr15.
Clamp prevention circuits Tr25 and R2 for preventing the output voltage from being clamped by 6 and Tr15 are provided.

Further, as shown in FIG. 8, the transistor Tr20 constituting the base current adjusting circuit has a base connected to the output transistor Tr24 until the output terminal voltage Vo rises from the low potential side power supply GND by a certain level. An operating voltage adjusting circuit R3 that operates so as not to supply current
R4, 1c and 1d are connected.

Further, as shown in FIG. 10, the transistors Tr16 and Tr15 forming the negative potential detection circuit are
Until the output terminal voltage Vo drops from the low-potential-side power supply GND by a certain level, the transistors Tr16, Tr15
Operating voltage adjusting circuit R2 that operates so as not to turn off
1e and 1f are connected.

[0024]

Since the base current proportional to the output terminal voltage Vo is supplied to the output transistor Tr24, the unnecessary supply of the base current to the output transistor Tr24 is prevented and the power consumption is reduced. When the output terminal voltage Vo has a negative potential, the negative potential is detected by the negative potential detection circuit 3, and the negative potential absorption circuit 4 outputs a current I to the output terminal T1 to absorb the negative potential.

In FIG. 2, the output terminal voltage Vo is detected by the output potential detecting circuits Tr17, Tr18, Tr19, and when the output terminal voltage Vo becomes a negative potential, the transistor Tr16 is detected.
, Tr15 is turned off. Transistors Tr16, Tr15
When is turned off, the output current Io1 for absorbing the negative potential is supplied from the negative potential absorbing circuit to the output terminal T1.

Further, in FIG. 2, the transistor Tr1 is
6 and Tr15 are turned off, the transistor Tr21 is turned on, and when the transistor Tr21 is turned on, the transistor Tr23 is turned on and the output current Io1 is output from the output terminal T1.
Is supplied to.

In FIG. 7, transistors Tr16 and T16 are provided.
When r15 is turned off, transistor Tr21 is turned on,
When the transistor Tr21 is turned on, the output transistor Tr24 is turned on in the reverse direction, and the output current Io1 is supplied to the output terminal T1.

In FIG. 6, transistors Tr16 and T16 are provided.
Even if r15 is saturated, output potential detection circuits Tr17, Tr18,
The output voltage of Tr19 is not clamped at the same level as the saturation level of the transistors Tr16 and Tr15.

In FIG. 8, the operating voltage adjusting circuit R3
The output transistor Tr24 is not turned on until the output terminal voltage Vo rises from the low potential side power supply GND by a certain level by the operation of R4, 1c, 1d.

In FIG. 10, the operating voltage adjusting circuit R
The transistors Tr16 and Tr15 are not turned off and thus the transistor Tr23 is not turned on until the output terminal voltage Vo drops by a certain level from the low-potential-side power supply GND by the operation of 2, 1e and 1f.

[0031]

FIG. 2 shows a first embodiment embodying the present invention. The input signals IN1 and IN2 are pulse signals similar to those in the conventional example. The PNP transistor Tr11 has an emitter connected to the power supply Vcc, a collector connected to the ground GND via the current source 1b, and a base connected to the collector.

The base of the transistor Tr11 is PN
It is connected to the bases of the P transistors Tr14 and Tr18, and the emitters of the transistors Tr14 and Tr18 are connected to the power supply Vcc.

The collector of the transistor Tr14 is NP
It is connected to the collector of the N-transistor Tr16, and the collector of the transistor Tr18 is the NPN transistor Tr17.
Connected to the collector.

The bases of the transistors Tr16 and Tr17 are connected to the collector of the transistor Tr17 and the collector of the NPN transistor Tr12.

The input signal IN2 is input to the base of the transistor Tr12, and the emitter is ground GND.
Connected to. The emitter of the transistor Tr16 is P
It is connected to the emitter of the NP transistor Tr15, and the collector of the transistor Tr15 is connected to the ground GND.

The base of the transistor Tr15 is NPN.
It is connected to the emitter of transistor Tr13 and
It is connected to the ground GND via the resistor R1. The collector of the transistor Tr13 is connected to the power source Vcc.

The emitter of the transistor Tr17 is PN.
It is connected to the emitter of the P-transistor Tr19 and to the base of the transistor Tr13. The base of the transistor Tr19 is connected to the output terminal T1 and the collector is connected to the ground GND.

The collector of the transistor Tr12 is N
It is connected to the base of the PN transistor Tr20, the collector of the transistor Tr20 is connected to the power supply Vcc, and the emitter is connected to the base of the NPN transistor Tr24.

The collector of the transistor Tr24 is connected to the output terminal T1 and the emitter is connected to the ground GND. The collector of the transistor Tr14 is an NPN
It is connected to the base of the transistor Tr21, the collector of the transistor Tr21 is connected to the power source Vcc, and the emitter is connected to the base of the NPN transistor Tr23.

The input signal IN1 is input to the base of the PNP transistor Tr22, the emitter of the transistor Tr22 is connected to the power source Vcc, and the collector is connected to the base of the transistor Tr23.

The collector of the transistor Tr23 is connected to the power source Vcc, and the emitter is connected to the output terminal T1. With such a configuration, the transistors Tr23,
A totem pole type output circuit is configured by Tr24, and includes transistors Tr22 and Tr23 and transistors Tr21 and Tr2.
3 and the transistors Tr20 and Tr24 are in Darlington connection.

A motor M is connected to the output terminal T1 as a load as in the conventional example. Next, the operation of the output circuit as described above will be described. Transistors Tr11, Tr1
4, Tr18 is always turned on by the operation of the current source 1b. In this state, the input signal IN1 is at L level and the input signal I
When N2 becomes H level, the on-operation of the transistor Tr12 lowers the base potentials of the transistors Tr16, Tr17 and Tr20, the base current IB2 supplied to the transistor Tr24 is reduced, and the transistor Tr24 is turned off.

When the transistor Tr22 is turned on,
The transistor Tr23 is turned on. Therefore, the output terminal T
The output current Io1 is supplied from 1 to the motor M, and the motor M is normally rotated.

On the other hand, when the input signal IN1 is at the H level and the input signal IN2 is at the L level, the base potential of the transistors Tr16, Tr17, Tr20 rises due to the off operation of the transistor Tr12, and the base IB2 supplied to the transistor Tr24. As a result, the transistor Tr24 is turned on.

The transistor Tr22 is turned off and the transistor Tr23 is turned off. Therefore, the output current Io2 flows from the motor M to the output terminal T1, and the motor M
Is rotated in reverse.

When the transistor Tr24 is turned on and the motor M is in a light load state and the output terminal voltage Vo drops, the emitter potential of the transistor Tr19 drops, the base potential of the transistor Tr20 drops, and the transistor Tr24 drops. The base current IB2 supplied to the IC decreases.

Therefore, as shown in FIG. 3, the output terminal voltage V
The base current IB2 decreases as o decreases. By such an operation, the base current IB2 is prevented from flowing unnecessarily when the load is light, and the power consumption is reduced.

In the output circuit as described above, the motor M
When the output terminal voltage Vo becomes a negative potential below the ground GND level due to the counter electromotive force generated in the transistor T,
Since the emitter potential of r19 drops and the transistor Tr13 is turned off, the emitter potential of the transistor Tr15 also drops.

Then, the base potentials of the transistors Tr16 and Tr17 decrease, and the transistors Tr16 and Tr17 are turned off. Then, the base current is supplied from the collector of the transistor Tr14 to the transistor Tr21, the transistor Tr21 is turned on, and the base current IB3 flows from the transistor Tr21 to the transistor Tr23.

The base current IB3 increases as the output terminal voltage Vo decreases, as shown in FIG. Therefore,
An output current Io1 flows from the transistor Tr23 to the output terminal T1, and the output terminal voltage Vo is raised to the ground GND potential.

In this way, the input signal IN1 is at H level,
The input signal IN2 becomes L level and the transistor Tr24
FIG. 5 shows output voltage-output current characteristics when the switch is turned on.

That is, the output terminal voltage Vo is the ground G
If it is higher than the ND potential, the output current Io2 flows through the transistor Tr24. When the output terminal voltage Vo becomes a negative potential below the ground GND potential, the transistor Tr23
An output current Io1 flows from.

Therefore, even if the output terminal voltage Vo has a negative potential, the negative potential can be quickly absorbed. FIG. 6 shows a second embodiment embodying the present invention. In this embodiment, a resistor R2 and an NPN transistor Tr25 are added to the first embodiment.

The resistor R2 is a transistor Tr16, Tr1.
Is connected between the bases of 7 and the transistor Tr25 is
The collector is connected to the power supply Vcc, the base is connected to the collector of the transistor Tr18, and the emitter is connected to the base of the transistor Tr17.

With such a configuration, the transistor Tr1
Even when 6 and Tr15 are saturated, the transistor Tr25 makes it possible to supply a sufficient base current to the transistors Tr16, Tr17 and Tr20, and the transistor Tr17.
, Tr20 have base potentials of transistors Tr15, Tr16.
The voltage drop between the base and emitter of VBE is not clamped by VBE.

Therefore, a sufficient base current IB2 can be supplied from the transistor Tr20 to the transistor Tr24. Other operations are the same as those in the first embodiment.
FIG. 7 shows a third embodiment embodying the present invention. In this embodiment, the emitter of the transistor Tr21 of the second embodiment is connected to the base of the transistor Tr24.

With this configuration, the output terminal voltage Vo
Becomes a negative potential, the emitter potential of the transistor Tr24 becomes higher than the collector potential. When the base current IB3 is supplied from the transistor Tr21 in this state, the transistor Tr24 operates in the reverse direction, and a current flows from the emitter to the collector. Therefore, as in the above embodiment, the negative potential of the output terminal T1 is absorbed.

FIG. 8 shows a fourth embodiment embodying the present invention. This embodiment is the same as the second embodiment except that the resistor R
3, R4 and current sources 1c and 1d are added. The resistor R3 is connected between the bases of the transistors Tr16 and Tr17 and the base of the transistor Tr20, and the resistor R4 is connected between the emitter of the transistor Tr20 and the base of the transistor Tr24.

The current source 1c is connected between the base of the transistor Tr20 and the ground GND, and the current source 1d is connected to the base of the transistor Tr24 and the ground GND.
Connected between and.

With such a configuration, the transistor Tr2 is driven by the current I1 flowing through the current source 1c through the resistor R3.
The base potential of 0 is lower than that of the first embodiment by a certain level.

The base potential of the transistor Tr24 is lower than that of the first embodiment due to the current I2 flowing through the current source 1d through the resistor R4. Then, the transistor Tr24 is not turned on until the output terminal voltage Vo rises from the ground GND level by a certain level or more, and the output current Io2 does not flow as shown in FIG.

Therefore, when the output terminal voltage Vo changes from the positive potential to the negative potential or from the negative potential to the positive potential, the transistors Tr23 and Tr24 are not turned on at the same time.

As a result, from the power source Vcc to the transistor Tr2
It is possible to prevent the generation of a through current that flows to the ground GND via 3 and Tr24. The other operations are the same as those in the first embodiment.

FIG. 10 shows a fifth embodiment embodying the present invention. In this embodiment, the transistor Tr25 is removed from the second embodiment and current sources 1e and 1f are added.

The current source 1e is connected between the base of the transistor Tr16 and the power source Vcc, and the current source 1f is
It is connected between the base of the transistor Tr17 and the ground GND.

With this configuration, the output terminal voltage Vo
Becomes negative potential, the current I3 flowing from the current source 1e to the current source 1f via the resistor R2 causes the transistor T to flow.
The base potential of r16 is higher than that in the second embodiment.

Then, the transistor Tr16 is not turned off until the output terminal voltage Vo decreases from the ground GND level by a certain level or more, the transistor Tr21 is turned on based on the off operation of the transistor Tr16, and the base current IB3 is supplied to the transistor Tr23. To do.

Then, the transistor Tr23 is not turned on until the output terminal voltage Vo drops from the ground GND level by a certain level or more, and the output current Io1 is output as shown in FIG.
Does not flow.

Therefore, when the output terminal voltage Vo changes from the positive potential to the negative potential or from the negative potential to the positive potential, the transistors Tr23 and Tr24 are not turned on at the same time.

As a result, from the power supply Vcc to the transistor Tr2
It is possible to prevent the generation of a through current that flows to the ground GND via 3 and Tr24. The other operation is the same as that of the second embodiment.

FIG. 12 shows a sixth embodiment embodying the present invention. In this embodiment, the transistor Tr12 of the first embodiment is omitted, and the PNP transistor Tr26 and N
This is a configuration in which a PN transistor Tr27 is added.

The transistor Tr26 has an emitter connected to the power supply Vcc, a base connected to the base of the transistor Tr22, and a collector connected to the base of the transistor Tr27.

The collector of the transistor Tr27 is connected to the base of the transistor Tr20, and the emitter is connected to the ground GND. With such a configuration, when the input signal IN1 becomes L level, the transistor Tr22 is turned on, the transistor Tr23 is turned on, and the output current Io1 is output.

Further, as the transistor Tr22 is turned on, the transistor Tr26 is turned on. As the transistor Tr26 is turned on, the transistor Tr2 is turned on.
7 is turned on.

Then, the transistor Tr20 is turned off and the base current IB2 of the transistor Tr24 is cut off.
The transistor Tr24 is turned off. On the other hand, the input signal I
When N1 becomes H level, the transistor Tr22 is turned off and the transistor Tr23 is turned off.

Further, the transistor Tr26 is turned off along with the turning-off operation of the transistor Tr22. With the turning-off operation of the transistor Tr26, the transistor Tr2 is turned on.
7 is turned off.

Then, the base current is supplied to the transistor Tr20 from the transistor Tr18 to turn on the transistor Tr20, and the base current IB2 is supplied to the transistor Tr24 to turn on the transistor Tr24.
Therefore, the output current Io2 is output.

With this operation, when the output currents Io1 and Io2 are inverted based on the inversion of the input signal IN1,
The transistors Tr23 and Tr24 are never turned on at the same time.

Therefore, from the power supply Vcc to the transistor Tr23.
, Tr24 to prevent the generation of a through current flowing to the ground GND. Also, a single-phase input signal I
The output currents Io1 and Io2 can be controlled only by N1. The other operation is the same as that of the second embodiment.

[0080]

As described in detail above, the present invention can provide an output circuit capable of reliably driving a load that generates a counter electromotive force while reducing power consumption.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is an operation characteristic diagram of the first embodiment.

FIG. 4 is an operating characteristic diagram of the first embodiment.

FIG. 5 is an output voltage-output current characteristic diagram of the first embodiment.

FIG. 6 is a circuit diagram showing a second embodiment.

FIG. 7 is a circuit diagram showing a third embodiment.

FIG. 8 is a circuit diagram showing a fourth embodiment.

FIG. 9 is an output voltage-output current characteristic diagram of the fourth embodiment.

FIG. 10 is a circuit diagram showing a fifth embodiment.

FIG. 11 is an output voltage-output current characteristic diagram of the fifth embodiment.

FIG. 12 is a circuit diagram showing a sixth embodiment.

FIG. 13 is a circuit diagram showing a conventional example.

FIG. 14 is an operation characteristic diagram of a conventional example.

FIG. 15 is an operation characteristic diagram of a conventional example.

[Explanation of symbols]

 2 Base current adjustment circuit 3 Negative potential detection circuit 4 Negative potential absorption circuit Tr24 Output transistor T1 Output terminal GND Low potential side power supply IN Input signal Vo Output terminal voltage I Current

Claims (7)

[Claims] 1. A collector of an output transistor (Tr24) is connected to an output terminal (T1), an emitter is connected to a low-potential side power source (GND), and the output transistor (Tr24) is connected based on an input signal (IN). An output circuit comprising a base current adjusting circuit (2) which is turned on / off and supplies a base current proportional to the output terminal voltage (Vo) to the output transistor (Tr24), wherein the output terminal voltage (Vo) ) Is the low potential side power source (GN
D) A negative potential detecting circuit (3) for detecting a decrease in negative potential below, and a current (I) is supplied to the output terminal (T1) based on the output signal of the negative potential detecting circuit (3). And a negative potential absorption circuit (4) for absorbing a negative potential. 2. The base current adjusting circuit is Darlington-connected to the base of the output transistor (Tr24) to supply a base current to the output transistor (Tr24), and the output terminal voltage (V).
the base current proportional to the transistor (Tr20)
Output potential detection circuit (Tr17, Tr18, Tr)
19) and the negative potential detection circuit is turned off when the output terminal voltage (Vo) becomes a negative potential based on the output signal of the output potential detection circuit (Tr17, Tr18, Tr19). (Tr16, Tr15), and the negative potential absorption circuit (4) is connected to the transistor (T16).
Output terminal (T1) based on the off operation of r16, Tr15)
The output circuit according to claim 1, wherein an output current (Io1) for absorbing a negative potential is supplied to the output circuit. 3. The negative potential absorption circuit (4) is connected to the transistor (Tr21) which is turned on based on the off operation of the transistors (Tr16, Tr15) and Darlington connection to the transistor (Tr21), and the transistor (Tr21). 3. A transistor (Tr23) which is turned on based on an ON operation of Tr21) and supplies the output current (Io1) to an output terminal (T1).
The output circuit described. 4. The negative potential absorption circuit (4) is connected to a transistor (Tr21) which is turned on based on an off operation of the transistors (Tr16, Tr15) and Darlington connection to the transistor (Tr21), and the transistor (Tr21). It is turned on in the opposite direction based on the ON operation of Tr21),
3. The output circuit according to claim 2, wherein the output circuit comprises the output transistor (Tr24) for supplying the output current (Io1) to the output terminal (T1). 5. The output potential detection circuit (Tr17, Tr18)
, Tr19) are connected to the negative potential detection circuits (Tr16, Tr15).
), The negative potential detection circuit (Tr16, Tr15)
3. The output circuit according to claim 2, further comprising a clamp prevention circuit (Tr25, R2) for preventing the output voltage from being clamped by (4). 6. The output terminal voltage (Vo) is applied to the transistor (Tr20) constituting the base current adjusting circuit.
) Operates to prevent the base current from being supplied to the output transistor (Tr24) until a constant level rises from the low potential side power supply (GND).
3. The output circuit according to claim 2, wherein R4, 1c, 1d) are connected. 7. The transistor (Tr16, Tr15) constituting the negative potential detection circuit is kept in the transistor (Tr16) until the output terminal voltage (Vo) drops from a low potential side power supply (GND) to a constant level. , Tr15) so as not to turn off the operating voltage adjusting circuit (R2, 1
3. The output circuit according to claim 2, wherein e, 1f) are connected.