JPH07262364A - Device and method for image processing - Google Patents

Abstract

PURPOSE:To provide the device and method for image processing with which throughput is not lowered even when normal font data are rotated. CONSTITUTION:Corresponding to a mode signal 119 expressing a rotation angle, a computing element 102 sets the shift amount of a shift circuit 103 from an address signal 112, and a computing element 104 calculates the input/output address of a memory 106 from the address signal 112. Image data inputted through a data bus 114 are shifted for the prescribed amount, written in the memory 106 and read out of the memory 106 by the address corresponding to the rotation angle. The read image data are shifted by the shift circuit 103 corresponding to the rotation angle, and the MSB and LSM are converted by a bit align converter 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and a method thereof, and more particularly, to an image processing apparatus and a method for rotating an image.

[0002]

2. Description of the Related Art A conventional image processing apparatus determines whether or not rotation processing is necessary before expanding image data to create bitmap data. Then, if the rotation process is necessary, the rotated bitmap data is created by using the previously rotated font data.

[0003]

However, the above-mentioned conventional example has the following problems. In other words, there is a problem that the rotation processing cannot be performed again on the once created bitmap data. Further, since the font data rotated in advance is required, at least twice the amount of font data is prepared, or special processing for rotating the normal font data is required. With this rotation processing, the throughput of the image processing apparatus was significantly reduced.

The present invention is intended to solve the above-mentioned problems, and its purpose is as follows. An object of the present invention is not to reduce the throughput even when the normal font data is rotated.

[0005]

The present invention has the following structure as one means for achieving the above object. An image processing method for rotating an image, comprising: a storage step of storing image data shifted by a predetermined amount in a storage means including a plurality of memories that store image data in predetermined units; and the storage means according to the rotation processing. Of the image data read from the storage means by the first address common to the memories and the second address different between the memories, and the image data read from the storage means to the rotation processing. A shift process that shifts in predetermined units according to
And a conversion step of converting the data order of the shifted image data according to the rotation processing.

[0006] An image processing apparatus for rotating an image, comprising storage means comprising a plurality of memories for storing image data in predetermined units and image data input / output to / from the storage means in a predetermined manner according to the rotation processing. An input / output address of the storage means is controlled by a shift means for shifting in units, a first address common to each memory of the storage means according to the rotation processing, and a second address different between the memories. It has a control means and a conversion means for converting the data order of the image data read from the storage means and shifted by the shift means in accordance with the rotation processing.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image processing apparatus according to an embodiment of the present invention will be described in detail below with reference to the drawings.

[0008]

[First Embodiment] FIG. 1 is a block diagram showing a configuration example of a bitmap memory used in an image processing apparatus according to a first embodiment of the present invention. This bitmap memory is, for example, 16 bits × 16 controlled by a 16-bit wide data bus.
It is a bit size. In FIG. 1, 101 is a latch, which latches address data on the address bus 110 with a timing signal ASB 111 from a CPU (not shown) and outputs a 4-bit address signal 112 to the memory 106.

Reference numeral 102 denotes an arithmetic unit, which operates the input address signal 112 according to the mode signal 119 and outputs a shift value obtained as a result to the shift circuit 103.
The shift circuit 103 shifts the input data in units of, for example, a 16-bit data block based on the shift value. Reference numeral 104 is also a computing unit, which responds to the mode signal 119 by inputting the address signal 11
2 is calculated, and the resulting address signal is output to the memory 106. Note that FIG. 2 shows a detailed configuration example of the arithmetic unit 104 and the memory 106. That is, the memory 1
06 is composed of 16 16-bit memory devices, and the memory device 203 stores the dot 0 in the memory device 2
04 stores 16 bits of each dot 1.

Reference numeral 105 designates a selector, which receives a read / write signal R / W 113 from the CPU and causes a data bus 114 at the time of writing.
The signal sent via the memory is selected and the memory 10 is used for reading.
The signal output from 6 is selected. Reference numeral 107 denotes a bit-align converter, which is controlled by a mode signal 119 and controls the output order of input data.

Next, the operation of the bit map memory shown in FIG. 1 will be described. First, the CPU writes data to the memory 106 via the data bus 114 to create bitmap data. In this case, since it is a write operation, signal R / W1
13, the selector 105 selects data on the data bus 114, and the memory 10 is selected via the shift circuit 103.
Data from the CPU is input to 6. Also, the latch 10
1 latches the address data on the address bus 110 and outputs the address signal 112.

The shift value and the address value are determined by the arithmetic unit 102 and the arithmetic unit 104. In the writing operation, each arithmetic unit is not affected by the mode signal 119, and the address signal output from the latch 101 is It becomes the shift value and the address value as they are. That is, when arbitrary data is written in the memory 106, the data is written in the address 0 as it is, and the data shifted by the respective address values is written in the addresses 1 to 15. 3 and 4
Is a diagram showing this state.

That is, FIG.
Bit data '00, 10,20,30, ..., F0 ', 16-bit data '01, 11,21,31, ..., F1' with address value 1 ...
16-bit data '0F, 1F, 2F, 3F, with address value 15
..., FF 'is an example output by the CPU. Here, '0
"0" and "F0" do not mean the value of data, but are labels for representing each bit.

FIG. 4 shows the data of FIG. 3 in the memory 106.
An example of the state written to
10,20,30, ..., F0 'is shifted to address 1 by the address value'F1,01,11,21, ..., E1', ..., Address 15 is similarly shifted to '1F , 2F, 3F, 4F, ..., 0F 'are written. Next, the reading operation will be described in order for each rotation angle.

In the case of zero degree In this case, it is necessary to format the memory contents shown in FIG. 4 into the state shown in FIG. That is, the memory 106
If the address is 0, the data read from is unchanged, if the address is 1, the data is shifted by 15, and if the address is 2, the data is shifted by 14,
… If the address is 15, shift that data by one,
Only read each.

After setting the mode signal 119 to the zero-degree rotation reading, the CPU outputs the same address signal as that at the time of writing to the address bus 110 for sequentially reading the data from the memory 106. Since the mode signal 119 is set to the zero-degree rotation reading, the arithmetic unit 102 receives the input address.
Set the shift amount S from ADD as follows. S = 0-ADD (1) Further, the arithmetic unit 104 outputs the input address ADD as it is because the mode signal 119 is set to the zero-degree rotation reading.

ADD1 = ADD (2) Further, the bit-align converter 107 also has the mode signal 1
Since 19 is set to the zero-degree rotation reading, the data input from the shift circuit 103 is output as it is. Then, the data is output from the memory 106 to the selector 105 by a control signal (not shown) according to the read cycle of the CPU. This data is input to the shift circuit 103,
After being shifted by the shift value S calculated by the equation (1), it is output via the bit align converter 107.

In the case of 90 degrees In this case, it is necessary to format the memory contents shown in FIG. 4 into the state shown in FIG. As shown in FIG. 6, for example, the data at address 0 is'F0, F1, F2, F3, ..., FF ', and the data at address 1 is'E0, E1, E2, E3, ..., EF'. .

To read this from the memory 106,
First, the dot D0 at address 0 is the bit at address 1
Read F1, read bit F2 of address 2 with dot D1,
…, Read bit F0 of address 0 with dot D15. Next, the dot D0 of the address 1 reads the bit E2 of the address 2, the dot D1 reads the bit E3 of the address 3, and the dot D15 reads the bit E1 of the address 1. Further, the data read out in this way is'F1, F2, F3, F in the case of address 0, for example.
Since the sequence is 4, ..., F0 ', the data shown in FIG. 6 can be obtained by shifting the sequence.

In this case, it is necessary to supply different addresses to the memory allocated to each dot.
In order to realize this, it is necessary to convert the address by the arithmetic unit 104. That is, as shown in the following equation, the arithmetic unit 104 adds a first address ADD1 obtained by adding 1 to the address ADD represented by the input address signal 112, and an address for adding a value corresponding to a dot position to ADD1. Generate ADD2 and.

ADD1 = ADD + 1 (3) ADD2 = + DOT (4) To explain the operation in detail, the CPU uses the mode signal 119.
Is set to 90-degree rotation reading, the address signal similar to that at the time of writing is output to the address bus 110 in order to sequentially read the data from the memory 106. Since the mode signal 119 is set to 90-degree rotation reading, the arithmetic unit 102 sets the shift amount S from the input address ADD according to the following equation.

S = ADD + 1 (5) Further, since the mode signal 119 is set to 90-degree rotation reading, the arithmetic unit 104 converts the input address ADD according to the following equation, Also turns on the address. The memory 106 outputs the data of the address obtained by adding the value corresponding to the dot position to the first address.

ADD1 = ADD + 1 (6) Further, the bit-align converter 107 outputs the mode signal 1
Although 19 is set to read by 90 degrees, the input data is output as it is in this mode. In the case of 180 degrees In this case, it is necessary to format the memory contents shown in FIG. 4 into the state shown in FIG.

As shown in FIG. 7, for example, the data at address 0 is'FF, EF, DF, CF, ..., 0F 'and the data at address 1 is'FE, EE, DE, CE, ..., 0E. 'Is. This is memory 1
To read from 06, first read each bit of address 15 at address 0, then address 1 at address 1.
Read each bit of 4. Further, the data read in this way is, for example, in the case of address 0, '1F, 2F, 3F, 4F, ...,
Since it is in the order of 0F ', after shifting this, that MS
By reversing B and LSB, the data shown in FIG. 7 is obtained.

To explain the operation in detail, the CPU sets the mode signal 119 to 180 ° rotation reading, and then the memory 1
In order to read data sequentially from 06, the address bus 11
The same address signal as when writing to 0 is output. Calculator 1
In 02, since the mode signal 119 is set to 180-degree rotation reading, the shift amount S is set from the input address ADD by the following equation.

S = 1 + ADD (7) Further, since the mode signal 119 is set to 180-degree rotation reading, the arithmetic unit 104 converts the input address ADD according to the following equation. ADD1 = F-ADD (8) Furthermore, the bit-align converter 107 has the mode signal 1
Since 19 is set for 180 degree rotation reading, MSB and LSB
Is output in reverse.

In the case of 270 degrees In this case, it is necessary to format the memory contents shown in FIG. 4 into the state shown in FIG. As shown in FIG. 8, for example, the data at address 0 is “0F, 0E, 0D, 0C, ..., 00”, and the data at address 1 is “1F, 1E, 1D, 1C, ..., 10”. .

To read this from the memory 106,
First, the dot D0 of the address 0 reads the bit 00, the dot D1 reads the bit 01 of the address 1, the dot D15 reads the bit 0F of the address 15. Then address 1
Read bit 1F of address 15 at dot D0, read bit 10 of address 0 at dot D1, ..., address at dot D15
Read 14 bits 1E. Further, the data read in this way is, for example, in the case of address 1, '1F, 10,11,12, ...,
Since the order is 1E ', the data shown in FIG. 9 is obtained by reversing the data order after shifting 15 times.

In this case, it is necessary to supply different addresses to the memory assigned to each dot.
In order to realize this, it is necessary to convert the address by the arithmetic unit 104. That is, as shown in the following equation, the arithmetic unit 104 adds a first address ADD1 obtained by adding 1 to the address ADD represented by the input address signal 112, and an address for adding a value corresponding to a dot position to ADD1. Generate ADD2 and.

ADD1 = 0-ADD (9) ADD2 = + DOT (10) The operation will be specifically described.
Is set to 270-degree rotation reading, the address signal similar to that at the time of writing is output to the address bus 110 for sequentially reading data from the memory 106. Since the mode signal 119 is set to 270 ° rotation reading in the arithmetic unit 102,
The shift amount S is set from the input address ADD by the following equation.

S = 0-ADD (11) Further, since the mode signal 119 is set to 270 ° rotation reading, the arithmetic unit 104 converts the input address ADD as the following equation, Also turns on the address. The memory 106 outputs the data of the address obtained by adding the value corresponding to the dot position to the first address.

ADD1 = 0-ADD (12) Further, the bit-align converter 107 outputs the mode signal 1
Since 19 is set to 270 ° rotation reading, the data is output in the reverse order from the input order. The operations in the four modes from 0 to 270 degrees have been described above. The relationship between the shift amount, the first address and the second address, and the bit-aligned conversion in these modes is summarized in FIG.

As described above, according to this embodiment,
When writing the input data to the memory, shift the data according to the address and write it, and set the order and shift amount according to the rotation angle of the image and read the data from the memory. Can be subjected to rotation processing.

[0034]

[Second Embodiment] An image processing apparatus according to a second embodiment of the present invention will be described below. In the second embodiment, the first
About the same configuration as the embodiment, the same reference numerals are given,
Detailed description thereof will be omitted. FIG. 10 is a block diagram showing a configuration example of a bit map memory used in the image processing apparatus according to the embodiment of the present invention.

FIG. 11 is a diagram showing a detailed configuration example of the bit map memory in this embodiment, which has a width of 16 dots × 1000H in the X direction and a width of Y line in the Y direction. In the figure, each block such as blocks A, B, C, ... Shows a matrix of 16 × 16 dots, and each of these blocks is the same as that described in the first embodiment. Next, an example in which the image rotation method described in the first embodiment is applied to this embodiment will be described.

In FIG. 10, reference numeral 1001 denotes an address converter, which calculates an address input from the address bus 110 based on the X direction register signal 1111 and outputs the lower 4 bits in the Y direction to the bit map memory space. It is output as the line address 112. When an address is supplied from the CPU (not shown) via the address bus 110,
The address converter 1001 calculates, based on the supplied X-direction register signal 1111, the line number of a block obtained by dividing the input address value by 16 × 16 dots in the bitmap memory space, and the result is obtained. Is output as the line address and 112.

In this case, since the X-direction register value is 1000H, 4 bits of bits 12 to 15 in the address are extracted and directly output as 1012. Further, the address converter 1001 has 12 bits of bits 0 to 11 which are not extracted as a line address in the input address.
The bit is supplied to the memory 106 as an upper address.

In this way, the image rotation method described in the first embodiment can be applied to this embodiment. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device.
Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0039]

As described above, according to the present invention,
Even if the normal font data is rotated, the throughput can be prevented from being lowered.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a bitmap memory used in an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration example of a computing unit 104 and a memory 106 in FIG.

FIG. 3 is a diagram illustrating data written in a bitmap memory.

FIG. 4 is a diagram showing a state in which the data of FIG. 3 is written in a memory 106.

FIG. 5 is a diagram showing an example of a state read from the memory 106 in the zero-degree rotation mode.

FIG. 6 is a diagram showing an example of a state read from the memory 106 in the 90-degree rotation mode.

FIG. 7 is a diagram showing an example of a state read from the memory 106 in the 180-degree rotation mode.

FIG. 8 is a diagram showing an example of a state read from the memory 106 in the 270-degree rotation mode.

FIG. 9 is a diagram showing a relationship between a shift amount, a first address and a second address, and bit-aligned conversion in each mode.

FIG. 10 is a block diagram showing a configuration example of a bitmap memory used in the image processing apparatus of the second embodiment according to the present invention.

FIG. 11 is a diagram showing a detailed configuration example of a bitmap memory in the second embodiment.

[Explanation of symbols]

 101 Latch 102 Operation Unit 103 Shift Circuit 104 Operation Unit 105 Selector 106 Memory 107 Bit Alignment Converter

Claims (2)

[Claims] 1. An image processing method for rotating an image, comprising: a storage step of storing image data shifted by a predetermined amount in a storage unit composed of a plurality of memories for storing image data in predetermined units; A read step of reading image data from the storage means by a first address common to each memory of the storage means and a second address different between the memories, and the image data read from the storage means. An image processing method comprising: a shift step of shifting the image data in a predetermined unit according to the rotation processing; and a conversion step of converting a data order of the image data shifted according to the rotation processing. 2. An image processing apparatus for rotating an image, comprising: a storage unit including a plurality of memories for storing image data in predetermined units; and image data input / output to / from the storage unit according to the rotation process. The input / output address of the storage means is changed by the shift means for shifting in predetermined units, the first address common to each memory of the storage means according to the rotation processing, and the second address different between the memories. An image processing apparatus comprising: control means for controlling; and conversion means for converting a data order of image data read from the storage means and shifted by the shift means in accordance with the rotation processing.