JPH07262246A - Method and device for designing logic circuit - Google Patents

Abstract

PURPOSE:To tune timing so that the paths of a logic circuit have appropriate delay time. CONSTITUTION:A net data generation means 22 generating net data showing a gate, a register and the input/output relation of them, a critical path extraction means 25 referring to information on delay time on the gate and extracting the path corresponding to a condition from net data based on the condition of a signal in the path between two registers in net data and a gate information extraction means 28 referring to delay time on the gate, and detecting/extracting the gate to be changed on the gate included in the extracted path are provided. Net data is generated to change the extracted gate to be changed, which is extracted based on change rules where information on the gate to be changed is made to correspond to information on the gate becoming a change object, into the new gate based on the rules on the gate having information on the new gate corresponding to the condition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a device for designing a logic circuit, and more particularly to a method and a device for designing a logic circuit suitable for performing timing tuning of a large-scale logic circuit.

[0002]

2. Description of the Related Art Conventionally, when designing a logic circuit, input / output pin names, register names,
Describe the relationship between the clock and each signal, the logic between the signals,
There is known a compiler (net compiler) that selects predetermined gates and registers by inputting them to a computer and creates data called net data in which input / output signals are described for each of the gates and registers.

For this compiler, for example, FIG.
As shown in FIG. 4, it is described in the hardware description language and input. In this example, for the input signal in the <IN> column,
This shows that the output signal in the <OUT> column is obtained by using the seven registers in the <REG> column. The next paragraph shows that each of the registers R1 to R5 takes in a signal connected by “=” in synchronization with the clock CLK, and the next paragraph shows a signal T generated in the middle of the register.
The logic of 1 to T4 is described, and the final paragraph shows that the registers R6 and R7 of the output stage take in the signal connected by "=" in synchronization with the clock CLK.

That is, the logic circuit shown in the block diagram of FIG. 15 described in the hardware description language is
It is the description of FIG. When the logic circuit described in the hardware description language is input, the net compiler creates net data as shown in FIG.
That is, by automatically adding I1 to I14 shown in FIG. 16, the relationship between each gate and register and their inputs is expressed in a predetermined format and output.

By the way, a net compiler is a tool for uniquely generating net data when a logic circuit described in a hardware description language is input, and is designed in consideration of a signal delay time in a gate or a line. is not. For example, assuming that the cycle of the clock CLK is a predetermined time, the register R6,
No guarantee is made as to whether a signal is properly propagated to R7 to perform a desired operation, that is, an operation considering a signal delay time due to a gate.

Regarding this signal delay, the designer calculates the delay time due to the gate between the registers (paths), detects the path in which the required operation is not performed, and changes the gate to a new high speed gate. The work was done by trial and error. For this reason, there has been a problem that a huge amount of time and personnel are required.

Therefore, based on the net data and the delay time of each gate, the delay time due to the gate between each register (path) is calculated and compared with the appropriate delay time between the separately input paths to determine the proper delay time. A system is provided that points out paths with delay times that do not fit within the delay time.

[0008]

However, this system merely points out a problematic path, not how to change a gate existing in the path. In order to have a delay time within the time, it is necessary for the designer to perform trial and error, which requires a huge amount of time and personnel.

The present invention has been made to solve the problems of the conventional method and apparatus for designing a logic circuit described above, and an object thereof is to automatically make a path have a delay time within an appropriate delay time. Another object of the present invention is to provide a method and apparatus for designing a logic circuit capable of performing timing tuning of the logic circuit. Another object of the present invention is to provide a method and apparatus for designing a logic circuit capable of performing well-balanced timing tuning in consideration of the whole even in the case of a large-scale logic circuit. Another object of the present invention is to provide a method and apparatus for designing a logic circuit capable of performing timing tuning in good balance from a gate portion having a particular problem even in the case of a large-scale logic circuit considering the whole. Another object of the present invention is to provide a method and apparatus for designing a logic circuit capable of performing timing tuning in a well-balanced manner particularly from a significant path portion in the logic circuit in consideration of the whole even in the case of a large-scale logic circuit. is there. Another object of the present invention is to provide a method and apparatus for designing a logic circuit capable of performing well-balanced timing tuning from a gate portion that is often used in consideration of the whole even in the case of a large-scale logic circuit. . Still another object is to automatically and properly perform timing tuning of a logic circuit so that a path has a delay time within an appropriate delay time, and a logic that can change a gate more appropriately and efficiently. It is to provide a circuit design device.

[0010]

Therefore, a method of designing a logic circuit according to the invention of claim 1 of the present application is directed to a gate and a register to be used based on input design information of the logic circuit, and input of signals to the gate and the register. A step of creating net data representing an output relationship, and a step of referring to information regarding a delay time regarding a gate, and extracting a path based on a signal condition in a path between two registers in the net data and the net data And referring to the information regarding the delay time regarding the gate, detecting the gate to be changed and extracting the information regarding this gate from the gates included in the path extracted in the above step, Based on the change rule in which the relevant information and the information about the gate to be changed are associated with each other, For a gate to be changed, a gate having information relating to the new gate corresponding to the condition is selected, and an instruction is given to change the gate to be changed to the new gate selected in the step. And a step of changing the net data to new net data in response to the instruction, and the logic circuit is designed by repeating the steps.

According to a second aspect of the present invention, there is provided a logic circuit designing method, wherein a gate and a register to be used on the basis of design information of the input logic circuit and a net representing the input / output relation of signals to the gate and the register. A step of creating data, a step of extracting a path based on a condition of a signal in a path between two registers in the net data and the net data by referring to information about a delay time of the gate, and a delay related to the gate With reference to the time-related information, with respect to the gates included in the path extracted in the step, a gate to be changed is detected,
A step of extracting information related to this gate and ranking the gates to be changed based on a predetermined rule, and a change in which the information related to the gate to be changed and the information related to the gate to be changed are associated with each other. Based on a rule, for the extracted gate to be changed, a process of selecting a gate having information relating to the new gate corresponding to the condition,
A step of performing a predetermined number of gates from the higher order gate; an instruction to change the gate to be changed to a new gate selected in the step; and, in response to the instruction, And changing the net data to new net data, and the logic circuit is designed by repeating the above steps.

The logic circuit designing method according to the invention of claim 3 of the present application is different from the logic circuit designing method of claim 1 or 2 in that a signal condition is set in a path between two registers. It is characterized by being configured as a signal delay time.

The logic circuit designing method according to the invention of claim 4 of the present application is the same as that of the logic circuit designing method of claim 2 or claim 3, except that a predetermined rule is set according to the delay time of the gate itself and the load capacitance. One of the following: a large total delay time determined by the charging time and a high priority of the path, a gate having a large number of uses in the extracted path, or these. It is characterized in that it is configured to be a combination of.

According to a fifth aspect of the present invention, there is provided a logic circuit designing apparatus, an input means for inputting information, a gate, a register, and a gate used based on the design information of the logic circuit inputted from the input means. Net data creating means for creating net data indicating the input / output relationship of signals to and from the gate, cell data storage means for storing information on delay time related to the gate, and information stored in this cell data storage means And a delay time relating to a gate, and a critical path extracting means for extracting a path according to the condition from the net data created by the net data creating means based on a signal condition in a path between two registers in the net data. The information included in the path included in the path extracted by the critical path extracting unit is referred to. Regarding the change rule, the gate information extracting means for detecting the gate to be changed and extracting the information related to the gate, and the change rule information in which the information related to the gate to be changed and the information related to the gate to be changed are associated with each other. And a change rule storage unit that stores the information, and a gate having information about a new gate corresponding to the condition for the gate to be changed extracted by the gate extraction unit based on the information stored in the change rule storage unit. Edit command creating means for selecting a rule according to the above, and the net data creating means creates net data for changing to a new gate based on the rule selected by the edit command creating means.

According to a sixth aspect of the present invention, there is provided a logic circuit designing apparatus, input means for inputting information, gates and registers used based on the design information of the logic circuit inputted from the input means, and these. Net data creating means for creating net data representing a signal input / output relationship with respect to a gate and a register, cell data storing means for storing information relating to a gate delay time, and information stored in the cell data storing means And a delay time relating to a gate, and a critical path extracting means for extracting a path according to the condition from the net data created by the net data creating means based on a signal condition in a path between two registers in the net data. The information included in the path included in the path extracted by the critical path extracting unit is referred to. , A gate information extracting unit that detects a gate to be changed, extracts information related to the gate, and ranks the gate to be changed based on a predetermined rule, and information related to the gate to be changed and the change. The change rule storage means stores change rule information associated with the information about the target gate, and the gate information extraction means ranks the information based on the change rule storage means. The net data creating unit includes an edit command creating unit that selects a rule relating to a gate having information about the new gate corresponding to the condition, for the gates to be changed from the top of the order to the predetermined position. The feature is that net data is created to change to a new gate based on the rule selected by this edit command creating means. To.

In the logic circuit designing device according to the invention of claim 7 of the present application, the gate information extracting means is extracted from the logic circuit designing device according to claim 5 or 6 by the critical path extracting means. For the gates included in the path, the delay amount detection unit that calculates the total delay time determined by the delay time of the gate itself and the charging time for the load capacitance, and the total delay time calculated by this delay amount detection unit are large. It is characterized by including a gate in the order of the gates and a comparison order assigning unit for ranking the information related to the gate.

In the logic circuit designing device according to the invention of claim 8 of the present application, in addition to the logic circuit designing device of claim 5 or 6, the gate information extracting means is provided to the net data path. A path priority detection unit that detects the priority information that is present, a comparison order assignment unit that ranks the paths extracted by the critical path extraction means according to the priority detected by this path priority detection unit, and this comparison For each path ranked by the ranking unit, a delay amount detection unit that obtains a total delay time determined by the delay time of the gate itself and the charging time for the load capacitance for the gates included in the path, and the delay amount. A gate is provided in the order of the gate having the longest total delay time obtained by the detection unit, and an in-path data rank assigning unit that ranks information related to this gate in the path. And wherein the door.

According to a ninth aspect of the present invention, there is provided a logic circuit designing apparatus according to the fifth or sixth aspect of the logic circuit designing apparatus, wherein the gate information extracting means is extracted by the critical path extracting means. For the gate included in the critical path, a delay amount detection unit for obtaining a total delay time determined by the delay time of the gate itself and the charging time for the load capacitance, and the critical path,
Usage count detecting means for detecting the usage count of the same gate having the same total delay time and number of ways obtained by the delay amount detecting part, and the total sum of gates corresponding to the usage count detected by the usage count detecting means. It is characterized by comprising a weight calculation means for calculating a product of the delay time, a gate in a descending order of weight calculated by the weight calculation means, and a comparison order assigning section for ranking the information related to the gate.

In the logic circuit designing apparatus according to the invention of claim 10 of the present application, in the logic circuit designing apparatus of claim 5 or 6, the gate information extracting means is extracted by the critical path extracting means. For the gates included in the critical path, based on the delay amount detection unit that calculates the total delay time determined by the delay time of the gate itself and the charging time for the load capacity, and the priority information given to the net data path. A path priority detection unit that detects the priority information of the critical path, and a weight that calculates the product of the priority information detected by the path priority detection unit and the total delay time detected by the delay amount detection unit. Calculating means and ranking the gates and information related to the gates for each critical path in descending order of weight calculated by the weight calculating means Characterized in that it comprises a comparator rank allocation unit and that.

According to the eleventh aspect of the invention of the present application, in the logic circuit designing apparatus according to any one of the fifth to tenth aspects, the net data generating means is a logic circuit. Regarding the net data created based on the design information of the circuit or according to the edit command, the critical path data extracted by the critical path extraction means and the rule selected by the edit command creation means are fetched and held, and the critical path data and the rule are stored. And a change rule management means for changing the order of the rules stored in the change rule storage means.

According to a twelfth aspect of the present invention, there is provided a logic circuit designing apparatus according to the logic circuit designing apparatus according to any one of the fifth to eleventh aspects, in which a signal condition is 2 It is characterized in that it is a signal delay time in a path between two registers.

According to a thirteenth aspect of the present invention, in a logic circuit designing apparatus, the change rule storage means is different from that of the logic circuit designing apparatus according to any one of the fifth to twelfth aspects. The change rule determined by the delay time and the number of ways is stored in association with the gate name,
The edit command creating means selects from the change rule storage means a change rule associated with the gate name, delay time, and gate name of the gate extracted by the gate information extracting means, the delay time, and the number of ways. It is characterized by that.

[0023]

Since the method of designing a logic circuit according to the invention of claim 1 of the present application is configured as described above, by inputting the design information of the logic circuit, the net data is automatically created and the conditions are met. Path extraction, detection of gate to be changed and extraction of information related to this gate, selection of gate having information related to new gate corresponding to condition, instruction to change to new selected gate, new net data Is repeated, and the timing of the logic circuit is tuned according to the signal conditions in the path.

Since the method of designing a logic circuit according to the invention of claim 2 of the present application is configured as described above, in the detection of the gate to be changed and the extraction of the information related to this gate,
The gates to be changed are ranked, and the gates having a higher order are changed to a predetermined number of gates. Therefore, by appropriately setting the predetermined rule of ranking, it is ensured that the timing tuning is performed in a well-balanced manner in consideration of the whole even in the case of a large-scale logic circuit.

Since the method of designing a logic circuit according to the invention of claim 3 of the present application is configured as described above, the path between the two registers corresponding to the condition of the signal delay time is appropriately extracted and this path is selected. Regarding, regarding the detection of the gate to be changed and the extraction of the information related to this gate, the selection of the gate having the information related to the new gate corresponding to the condition, the instruction to change to the selected new gate, the change to the new net data Is repeated, the timing of the logic circuit is tuned so that the path has a delay time within an appropriate delay time.

Since the method of designing a logic circuit according to the invention of claim 4 of the present application is configured as described above, even in the case of a large-scale logic circuit, considering the whole, from the gate portion having a particular problem, Or, especially from the path part that is important in the logic circuit, or from the gate part that is often used,
Alternatively, it becomes possible to perform the timing tuning in good balance by using any one of these combinations.

Since the logic circuit designing apparatus according to the invention of claim 5 of the present application is configured as described above, by inputting the design information of the logic circuit, the net data is automatically created and the conditions are met. Path extraction, detection of gate to be changed and extraction of information related to this gate, selection of gate having information related to new gate corresponding to condition, instruction to change to new selected gate, new net data Is repeated, and the timing of the logic circuit is tuned according to the signal conditions in the path.

Since the logic circuit designing apparatus according to the invention of claim 6 of the present application is configured as described above, in the detection of the gate to be changed and the extraction of the information related to this gate,
The gates to be changed are ranked, and a predetermined number of gates are changed from the gate having a higher rank. Therefore, by appropriately setting the predetermined rule of ranking, it is ensured that the timing tuning is performed in a well-balanced manner in consideration of the whole even in the case of a large-scale logic circuit.

Since the logic circuit designing apparatus according to the invention of claim 7 of the present application is configured as described above, the gate and the information related to this gate are ranked in the order of the gate having the longest total delay time. The number of gates is changed from the gate with the highest rank to a predetermined number. Therefore, even in the case of a large-scale logic circuit, it is ensured that the gate having a large total delay time is subjected to timing tuning in good balance in consideration of the whole.

Since the logic circuit designing apparatus according to the invention of claim 8 of the present application is configured as described above, the gate and the gate are arranged in the order of the delay time in the path in accordance with the priority of the path. The information about the gates is ranked, and the gates having a higher rank are changed to a predetermined number of gates. Therefore, even in the case of a large-scale logic circuit, it is possible to ensure that the timing tuning is performed in a well-balanced manner for the gate having a high path priority and a large total delay time in consideration of the whole.

Since the logic circuit designing apparatus according to the invention of claim 9 of the present application is configured as described above, the gate and the gate thereof are weighted by the product of the frequency of use and the total delay time of the corresponding gate. The information is ranked, and the gates having a higher rank are changed to a predetermined number of gates. For this reason, even in the case of a large-scale logic circuit, it is possible to ensure that the timing tuning is performed in a well-balanced manner in consideration of the whole of the gates, which has a large weight due to the total delay time of the gates corresponding to the frequency of use.

Since the logic circuit designing apparatus according to the invention of claim 10 of the present application is configured as described above, the product of the path priority and the total delay time is used as a weight, and the critical paths are arranged in descending order of the weight. The gates and information related to the gates are ranked for each time, and a predetermined number of gates are changed according to the order and the path priority. Therefore, even in the case of a large-scale logic circuit, it is possible to ensure that well-balanced timing tuning is performed in consideration of the weight of the product of the path priority and the total delay time and the path priority in consideration of the whole.

Since the device for designing a logic circuit according to the invention of claim 11 of the present application is configured as described above, the order of rules stored in the change rule storage means is the history information of critical path data, It will be changed based on the change rules adopted when changing the gate. That is, the order of the change rules is changed according to the success or failure of the timing tuning of the logic circuit based on the rules, and the change is made so that the appropriate rule is selected.

Since the logic circuit designing apparatus according to the invention of claim 12 of the present application is configured as described above, the path between the two registers corresponding to the condition of the signal delay time is appropriately extracted, and this path is extracted. Regarding, regarding the detection of the gate to be changed and the extraction of the information related to this gate, the selection of the gate having the information related to the new gate corresponding to the condition, the instruction to change to the selected new gate, the change to the new net data Is repeated, the timing of the logic circuit is tuned so that the path has a delay time within an appropriate delay time.

Since the logic circuit designing apparatus according to the thirteenth aspect of the present invention is configured as described above, the gate name of the change rule storage means, the delay time, A change rule that matches the number of ways is selected, the signal logic between both ends of the path is appropriate, and a new gate path configuration that matches the number of branches (way number) in the middle of the path is secured. . That is, the timing of the logic circuit is automatically tuned according to the signal conditions in the path.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method and apparatus for designing a logic circuit according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same components are designated by the same reference numerals, and overlapping description will be omitted. FIG. 1 shows the configuration of a logic circuit designing apparatus according to an embodiment of the present invention. This design apparatus is realized by, for example, a computer system as shown in FIG. Computer system is CP
Main unit 1 with U, main memory, and various interfaces
And the keyboard input device 2, CR connected to it
The display device 3 includes a T display device 3, a printer device 4, and a mouse 5 which is a pointing device. The input by the keyboard input device 2 and the mouse 5 performs a logic circuit design process and an output process from the CRT display device 3 and the printer device 4. It Further, a magnetic disk storage device 6 which is an external storage device is connected to the main body 1 and stores programs and data necessary for designing a logic circuit, and the CPU of the main body 1 stores the programs and data as necessary. Load the data into main memory and execute the process.

FIG. 3 is a block diagram of the computer system shown in FIG. A main memory 8 is connected to a CPU 7 built in the main body 1, and a bus 9 extends, and the interface 9 is connected to the bus 9.
14 is connected. A keyboard input device 2, a CRT display device 3, a printer device 4, a mouse 5 as a pointing device, and a magnetic disk storage device 6 as an external storage device are connected to the interfaces 10 to 14, respectively. An alarm generator 17 is connected to the bus 9 via a driver 16.

In the logic circuit designing device constituted by the above computer system, the logic circuit designing information is inputted from the input means 21 corresponding to the keyboard input device 2 and the mouse 5. The design information of this logic circuit is the information in the hardware description language shown in FIG. 14 as described above. The design information of the logic circuit is taken into the net data creating means 22 composed of the above-mentioned net compiler or the like, and the net data as shown in FIG. 15 is created,
It is stored in the net data storage means 24. The completion of the net data creation is notified to the critical path extraction means 25. Upon receiving this notification, the critical path extraction means 25 stores it in the cell data storage means 26 on the basis of the path extraction condition information which is input from the input means 21 or which is the delay time of the signal in the path set in the system. With respect to the information related to the existing gate, the net data in the net data storage means 24 is searched and the path corresponding to the above condition is extracted.

FIG. 4 shows the information about the gate stored in the cell data storage means 26. That is, the cell data storage means 26 stores the gate name (macro cell name).
For each time, the switching time (for example, nanoseconds) of the gate itself is associated with the coefficient of charging time (for example, nanoseconds) with respect to the load capacity centered on the number of ways (fanout number). Remembered In this embodiment, the delay due to the read is included in the number of ways assuming that the read length between the gates is predetermined. Therefore,
In another embodiment corresponding to the design of the logic circuit in which the lead length between the gates is different, the delay time corresponding to the lead length for each predetermined gate is stored as cell data. Based on the information (cell data) related to the gate stored in the cell data storage means 26, the delay time of the path is the sum of the switching times for each gate, and the number of ways of each gate and the load capacity of that gate are charged. It is calculated by adding the product of time and the coefficient.

Critical path data extracted by the critical path extraction means 25 (path number, gate name included in path, switching time of the gate,
The coefficient of the charging time with respect to the load capacity, the number of ways, and the path delay time) are stored in the critical path data storage means 27. The critical path extraction means 25 notifies the gate information extraction means 28 of the completion of extraction of the critical path.
The gate information extracting means 28 is provided with critical path data stored in the critical path data storage means 27 (path number, gate name included in path, switching time of the gate, coefficient of charging time with respect to load capacity, number of ways, path delay). Time) is used to calculate the total delay time for each gate, and the gates to be changed are ranked from the input means 21 or the gates to be changed based on a predetermined rule set in the system. Alternatively, the gate information including the gate name, the switching time of the gate, the coefficient of the charging time with respect to the load capacity, the number of ways, and the total delay time up to the order set in the system (of course, all may be used) Storage means 2
Store in 9.

In this embodiment, the path number, the gate name included in the path, the switching time of the gate, the coefficient of the charging time with respect to the load capacity, the number of ways, and the path delay time are stored as the critical path data. Therefore, the gate information is extracted using this. In another embodiment, the path number, the gate name included in the path, and the number of ways are stored as the critical path data, and the gate information extracting unit 28 calculates the switching time of the gate and the coefficient of the charging time with respect to the load capacity. Gate information is extracted from the cell data storage means 26 as indicated by the broken line. Even in this way, the gate information is similarly extracted.

When the extraction of the gate information is completed, the gate information extracting means 28 notifies the edit command creating means 30 of the completion. Editing command creating means 3 that received this notification
0 is the delay of the path for the gate having the gate name stored in the gate information storage means 29, which is based on the information stored in the change rule storage means 31, for the gates to be changed from the top of the rank to a predetermined position. Select a gate rule that has information about the new gate that corresponds to the time condition.

FIG. 5 shows the change rules stored in the change rule storage means 31. The change rule is
Corresponding to the gate name of the gate to be changed, the delay time, the number of ways, a new gate or a change rule composed of a set of a gate and a buffer is stored. Here, in the delay time and the number of ways, a description such as "60-80" indicates 60 to 80, "-16" indicates up to 16, and "16-" indicates higher than 16. Explaining the change rule, the third change rule of "NOR1" is to improve the charging speed with respect to the load capacity by connecting two buffers BUF1 in parallel to the output of NOR1 as shown in FIG. This shows that load balancing is achieved. In addition, as shown in FIG. 7, the third “OR1” is replaced with OR1 and the output of NOR1 is converted into the inverter I.
By connecting two NV2s in parallel, it is shown that the charging speed with respect to the load capacity is increased and the load is distributed.

Further, FIGS. 8 to 12 show examples of general change rules, which are not described in the change rules shown in FIG. That is, in FIG. 8, in the case where the gate drive capacity is low with respect to the load capacity, the gate GS is changed to a gate GG having a large drive capacity with the same logic (a small charging time coefficient with respect to the load capacity). It is shown. FIG. 9 shows an example in which the buffer BUF is connected to the output without changing the gate to enhance the drive capability with respect to the load capacitance. Figure 10
To change the AND logic gate to a cascade connection circuit of the NAND logic gate and the inverter INV,
An example in which the delay time is shortened by the drive capability of V is shown. FIG. 11 shows that the load LD to be driven is large, so that the load LD is configured by two loads L1 and the load G is connected to and driven by the gate G. . Further, FIG. 12 shows an example in which the composite logic gate is replaced with another composite logic gate including a faster logic gate.

The edit command creating means 30 refers to the change rule storage means 31 in which the change rules configured in consideration of the above are stored, and the gate information storage means 29 up to a preset predetermined order is stored. Against the gate of
Select a change rule that matches the gate name and applies the delay time and the number of ways, and enter the command to instruct that the corresponding gate of the path containing the changed gate should be changed to the gate corresponding to the change rule. It is edited and sent to the net data creating means 22. In this embodiment, the change rule itself is composed of commands, and the edit command creating means 30 performs a process of simply selecting the change rule, designating the pass number, and transmitting the pass number.

The net data creating means 22 that has received the command creates new net data corresponding to the command and stores it in the net data storing means 24. The completion of the creation of new net data is notified to the critical path extraction means 25. Upon receiving this notification, the critical path extraction means 25 receives from the input means 21 or path extraction condition information consisting of the signal delay time in the path set in the system, and the path is stored in the cell data storage means 26 according to this condition. Based on the information about the gate stored in
The net data in the net data storage means 24 is searched and extracted. Thereafter, the same processing as described above is repeated, and the timing of the logic circuit is tuned according to the change rule.

The logic circuit designing method executed by the logic circuit designing apparatus of this embodiment is realized by the steps (steps) shown in FIG. That is, a net data creating step (STEP 1) for creating net data (a) representing the logic circuits to be used and the input / output relationship of these logic circuits based on the design information of the logic circuits input from the keyboard input device 2, Extracting a path corresponding to the path extraction condition (b), that is, a critical path based on the signal condition (path extraction condition) in the path between the two registers in the net data (a) and the net data (a) ( STEP 2) and the information regarding the delay time regarding the gate are used to detect the gate to be changed among the gates included in the path extracted in the step (STEP 2) for extracting the critical path, and the information regarding the gate ( Step (SETP3) of extracting d) and ranking the gates to be changed based on a predetermined rule
And the gate change rule (e) in which the information about the gate to be changed and the information about the gate to be changed are associated with each other, the path extraction condition (b) is set for the extracted gate (d) to be changed. ) Performing a process of selecting a gate having information about a corresponding new gate for gates having a high order to a predetermined number (S)
TEP4) and a step of giving an instruction to change the gate to be changed to the selected new gate, that is, sending a net edit command (f) (STEP5)
And the net data (a) is replaced with new net data (a1) in response to the net edit command (f) which is the above instruction.
(STEP6), and the logic circuit is designed by repeating the above steps.

Further, the apparatus of this embodiment has a change rule managing means 32 as shown in FIG. 1, and the change rule used when designing a logic circuit is so-called by learning, so that the change rule can be executed more accurately and at a high speed. Change so that timing tuning is performed. That is, the change rule managing means 32 takes in the critical path data extracted by the critical path extracting means 25 and the rule selected by the edit command creating means 30 and holds them as history information. The rule selected by the edit command creating means 30 is fed back, the net data creating means 22 creates new net data, and the critical path extracting means 25 is thereby created.
Extracts the critical path data, the new critical path data is taken in to detect whether the previous critical path has been improved, and the rule stored in the change rule storage means 31 is reflected so that the improvement result is reflected. The rank (the rank of the change rule corresponding to the gate name shown in FIG. 5) is changed. Further, the order is changed and the change rule itself is changed, deleted, or added in accordance with an instruction from the input means 21.

The display control means 3 is provided in the logic circuit design device.
3-1, output control means 33 composed of print control means 33-2, and output control means composed of display control means 34-1 and print control means 34-2 for displaying and printing under this control. 34 is provided, and the input information of the input means 21, the net data stored in the net data storage means 24, the critical path data stored in the critical path data storage means 27, and the gate information storage according to the instruction of the input means 21. Both the gate information stored in the means 29 and the data in the change rule storage means 31 can be displayed or printed out. The data in the change rule storage unit 31 is displayed by the change rule management unit 32 or is printed. Further, the edit command creating means 30 refers to the change rule storage means 31, and the gates match the gates up to a preset predetermined order of the gate information storage means 29, and the delay time and the number of ways are applied. In the case of the operation of selecting a change rule, when the corresponding change rule does not exist, alarm information is sent to the output control means 33 and the information of the gate for which the corresponding change rule does not exist is displayed (the corresponding one in the gate information. May be a special display.), And an alarm is generated from the alarm generator (FIG. 3) 17. Further, in the above description, when the critical path is displayed, it is possible to instruct which of the critical paths is to be gate-changed from the input means 21 to create the gate information.

Next, the operation of the logic circuit designing apparatus according to the embodiment of the present invention configured as described above will be described. When the design information of the logic circuit in the hardware description language shown in FIG. 14 is input from the input means 21, the net data creating means 22 receives this and creates the net data as shown in FIG. The critical path extracting means 25 is notified of the completion of the net data creation as well as the storage in the storage means 24. The critical path extracting means 25 that has received this notification inputs the path to the cell data storage means 26 according to the path extraction condition information that is input from the input means 21 or that is set in advance in the system and that includes the signal delay time in the path. Based on the stored information about the gate, the net data in the net data storage means 24 is searched and extracted, and the critical path data storage means 27 is searched.
Then, the gate information extracting means 28 is notified of the completion of the critical path extraction.

17 and 18 show examples of the configuration of critical path data stored in the critical path data storage means 27. FIG. 17 shows one pass number column. Corresponding to the pass number, the gate name included in this pass, the delay time of the gate itself and the delay time due to the load (coefficient of charging time with respect to load capacity). And the number of ways), the total delay time, and the number of ways corresponding to the gate are stored. FIG. 18 shows the critical path data storage means 27 in which actual numerical values are stored. In this way, referring to the critical path data in the critical path data storage means 27, the delay time related to the path extraction condition information (for example, 100 nanoseconds)
Path name that does not fit in and the gate name included in this path,
The delay time of the gate itself and the delay time due to the load (the product of the coefficient of the charging time with respect to the load capacity and the number of ways), the total delay time, and the number of ways corresponding to the gate are obvious.

The path 1 of the critical path data of the critical path data storage means 27 of FIG. 18 corresponds to the logic circuit of FIG. 15 corresponding to the net data of FIG.
As shown in FIG. 9, the path between the register R1 and the register R7 is defined as path 1, and the gates are NOR1, AND1, and O.
The delay time of the NOR1 gate itself is 25 nanoseconds, and the delay time of the AND1 gate itself is 2
0 nanoseconds, delay time of OR1 gate itself is 30 nanoseconds
sec, delay time due to load of NOR1 (product of charge time coefficient to load capacity and number of ways) is 40 (20 x 2)
Nano sec, delay time due to AND1 load is 10 nanose
c, shows that the delay time due to the load of OR1 is 10 nanoseconds. The number of ways is AND1, OR1
There is no branch for "1", but for NOR1, it is "2" because there is a branch to OR1 (T3). The total delay time is 135 nanoseconds, which is the sum of the delay times of the gates, and is extracted according to the delay time (eg, 100 nanoseconds) related to the path extraction condition information.

Further, the path 2 of the critical path data of the critical path data storage means 27 of FIG.
For the logic circuit of FIG. 15 corresponding to the net data of No. 6, as shown in FIG.
The path between 7 and 7 is called path 2, and the gates are AND1 and AN.
It is composed of D1 and OR1, and the delay time of the gate of each AND1 is 20 nanoseconds, the delay time of the gate of OR1 itself is 30 nanoseconds, and the delay time due to the load of the first AND1 is 20 (10 × 2) nanoseconds. sec, the second AND1
It is shown that the delay time due to the load of 10 nanoseconds and the delay time due to the load of OR1 are 10 nanoseconds.
The number of ways is "1" for the second AND1 and OR1 without branching, but is "2" for the first AND1 because there is a branch to OR1 (T3). The total delay time is 110 nanoseconds, which is the total delay time of each gate, and is extracted according to the delay time (eg, 100 nanoseconds) related to the path extraction condition information.

The gate information extraction means 28 which has received the notification of the completion of the extraction of the critical path, as shown in FIG.
With respect to the gates included in the paths of the critical path data storage means 27, the delay amount detecting unit 41 for obtaining the total delay time determined by the delay time of the gate itself and the charging time for the load capacitance, and the delay amount detecting unit 41. A gate and a comparison order assigning unit 42 for ordering information related to the gate are provided in the order of the gate having the largest total delay time.

That is, in the example of FIG. 18, assuming that the paths 1 and 2 ... Are extracted as critical paths, the delay amount detecting section 41 determines each of the paths 1 and 2 as shown in FIG. At the gate, the sum of the delay time of the gate itself and the delay time due to the load (the product of the coefficient of the charging time with respect to the load capacity and the number of ways) is calculated and stored in the register indicated by "total". When the sums are obtained for all the critical paths, the comparison rank assigning unit 42 compares the total delay times of the registers indicated by "total", assigns ranks in descending order of delay time, and stores them in the register "rank".
Further, the comparison rank assigning unit 42 sorts the data of the register “rank”, and as shown in FIG.
Gate names are arranged in descending order of delay time, and the pass number, delay time of the gate itself, delay time due to load (product of coefficient of charging time with respect to load capacity and number of ways), delay time due to gate itself and delay time due to load And the number of ways are associated and stored in the gate information storage means 29. Note that the number to be stored is up to the set rank. It is based on the fact that only the changed portion needs to be stored. In another embodiment, only the critical paths are stored. This is because either the stored data is selected to be changed or all are changed. Also, sorting on the gate information is not always necessary. That is, in another embodiment, by changing the number of gates up to a predetermined number according to the rank of the unsorted gate information, the same effect as in the case of being sorted can be obtained. Other examples of this sorting also hold for the following examples.

When the extraction of the gate information is completed, the gate information extracting means 28 notifies the edit command creating means 30 of the completion. Editing command creating means 3 that received this notification
0 is the delay of the path for the gate having the gate name stored in the gate information storage means 29, which is based on the information stored in the change rule storage means 31, for the gates to be changed from the top of the rank to a predetermined position. Select a gate rule that has information about the new gate that corresponds to the time condition. The edit command creating means 30 creates a command according to the procedure shown in FIG. That is, CPU
7 executes processing according to the program of the flowchart of FIG.

Specifically, when the edit command creating process is started, the edit command creating means 30 loads the gate information for the change target of the information stored in the gate information storage means 29 (61), and the step Loop processing is performed to refer to all rules so that steps 62 to 63 are executed. That is, for example, the rule is loaded from the magnetic disk storage device 6 to the main memory 8 (64), and it is detected whether the gate to be changed and the gate name match (65). Change rule storage means 31
As shown in FIG. 5, the change rule of is associated with the gate name, the delay time, the number of ways, and the change rule.
Search for the gate name that matches the gate name (of the gate information) before the change. When a change rule with a matching gate name is detected by the loop processing, it is detected whether there is a change rule with a matching delay time in this change rule group (6
6). The delay time here is for the gate information. When a change rule having a matching delay time is detected by the loop processing, it is detected whether the number of ways matches (67).
When a change rule in which the number of ways matches is detected by the loop processing, the detected change rule is selected and a conversion command is created (68). In this embodiment, since the change rule itself is a command, embedding processing is performed in the command so as to indicate which path. On the other hand, if the gate name, the delay time, and the number of ways are not matched in spite of the loop processing for all the change rules, the processing without the corresponding rule is performed (69). In the processing without the applicable rule, information on the gate for which the applicable change rule does not exist is displayed as described above (the applicable information in the gate information may be displayed specially).
The alarm generator 17 (FIG. 3) generates an alarm.

The processing of FIG. 27 is processing for one gate to be changed. On the other hand, FIG. 28 shows a process of detecting whether or not the process for the set number of change target gates has been executed. The process of FIG. 28 is a process of detecting whether the process of FIG. 27 has been performed by the set number of changes. That is, the set change number n is set in the register (71), and the process of FIG. 27 is executed (72). Since the maximum value of the number of gates that can be used in the logic circuit is input and set by the input means 21, it is detected whether the value is within the maximum value as a result of the change by the change rule (73), and it is within the maximum value. Sometimes the change is confirmed (74) and the number of changes in the register is decremented by "1" (7
6) It is detected whether or not the number of changes is zero (77), and if it is not zero, the process returns to step 72 and the process is continued in order to execute the process of further changes. Also, in step 73,
When it is detected that the number of gates does not reach the predetermined number, the change is canceled (75) and the process proceeds to step 77 to continue the process. When the processing for the number of changes set in this way ends, the process ends.

When NOR1 which is the first gate of the gate information of FIG. 26 is changed according to the change rule of FIG. 5, the gate name is NOR1, the delay time is 65 nanoseconds, and the number of ways is 1. Therefore, the change rule of the first line in the column of gate name NOR1 in FIG. 5 is applicable. When this is selected and changed, the total delay time for path 1 is changed from 135 nanoseconds to 12 nanoseconds as shown in FIG.
Reduced to 5 nanoseconds. Change rules are commands,
When the command is embedded to indicate the change of the path 1, a command having the content shown in FIG. 30 is completed and is output to the net data creating means 22. When the net data creating means 22 receives such a command, it creates new net data based on the command.
That is, the command of FIG. 30 corrects the net data of the corresponding portion of the path 1, and the net data of the corresponding portion of the corresponding path is similarly corrected each time the remaining command arrives. The creation of new net data (end of modification) is notified to the critical path extracting means 25, and the processing is repeated in the same manner as above. In this example, the modified 125
Since nano-sec does not correspond to the delay time (for example, 100 nano-sec) related to the path extraction condition information, path 1 will be extracted again as a critical path.

In this first embodiment, for example, as shown in FIG.
Assuming that the number of changes n in 8 is "5", changes are made to the gates at 5 locations. In the case of the present embodiment, it is unlikely that a plurality of gates will be extracted as gate information for the same critical path from among the critical paths, and one gate of some critical paths will be changed so that some of the critical paths will be changed. There is a high probability that the path will not meet the path extraction conditions. That is, with one critical path,
It is not necessary to change two or more gates so that one critical path does not meet the path extraction condition and one critical path does not meet the path extraction condition as a result. In the present embodiment, in a plurality of critical paths, usually one gate is changed to simultaneously increase the number of paths that do not meet the path extraction condition, and timing tuning is performed in good balance as a whole. For critical paths that have not been met the path extraction condition once, the gate information is extracted and the gate is changed again by repeating the above process. In this embodiment, there is a possibility that a plurality of gates will be changed and extracted from the same critical path. Therefore, in another embodiment, when a plurality of gates are extracted from the same critical path as a target to be changed, one of the gates with a lower rank is excluded from the target and the gate with the next rank of another critical path is changed. Subject to. According to such an embodiment,
More surely, the timing tuning is performed with good balance.

FIG. 22 is a block diagram of the gate information extracting means 28 employed in the logic circuit designing apparatus according to the second embodiment. That is, the gate information extraction means 28
Is a path priority detection unit 43 for detecting priority information given in advance to the critical path extracted by the critical path extraction unit 25, and this path priority detection unit 4
The comparison rank assigning unit 44 that ranks the paths according to the priority detected by 3 and the gates included in the paths for each of the paths ranked by the comparison rank assigning unit 44.
The delay amount detecting unit 4 for obtaining the total delay time determined by the delay time of the gate itself and the charging time for the load capacitance.
5, a gate in order of the gate having the longest total delay time obtained by the delay amount detecting section 45, and an in-path data rank assigning section 46 for ranking information related to this gate in the path. .

That is, in the example of FIG. 18, if the path 3 and the like other than the paths 1 and 2 are extracted as critical paths, the path priority detection unit 43 causes the priorities ( For example, when a signal is sequentially propagated through a plurality of registers, a high priority is given to a path on the upstream side). This priority information is input together with the design information from the input means 21, stored in the net data storage means 24, and further stored in the critical path information storage means 27 as critical path data. The path priority detection unit 43 detects the order of paths based on the above priority. That is, which path is higher is checked, and the result is given to the comparison order giving unit 44. The comparison rank giving unit 44 gives ranks to the critical paths. This Figure 3
1 shows a part of the critical path information given the rank in this way. In the example of FIG. 31, an example in which the critical path information is rearranged according to the priority order is shown for the sake of clarity, but it is only necessary to give the order shown by order 1, order 2, etc.

As shown in FIG. 31, the delay amount detecting section 45 delays the gate itself and the delay time due to the load (coefficient of the charging time with respect to the load capacitance) for each of the paths 3, 1 ... The product of the number of ways) and
Store in the register indicated by "total". When the sum is obtained for all the critical paths, the in-path data rank assigning unit 46 compares the total delay time of the registers indicated by “total” for each of the paths 3, 1 ... A rank is given and stored in the register "rank". Furthermore, the in-path data rank assigning unit 46 is configured to compare the rank assigning unit 44.
Sorting is performed according to the rank of the critical path given by and the data of the register "rank". As a result, as shown in FIG. 32, among the critical paths, the gate name with the longest delay time is extracted and arranged for each critical path from the path with the highest priority. The time, the delay time due to the load (the product of the coefficient of the charging time with respect to the load capacity and the number of ways), the sum of the delay time of the gate itself and the delay time due to the load, and the number of ways are associated with each other, and these are associated with each other.
Store in 9. Note that the number to be stored is up to the set rank. It is based on the fact that only the changed portion needs to be stored. In another embodiment, only the critical paths are stored. This is because either the stored data is selected to be changed or all are changed.

The subsequent processing is the same as in the case of the first embodiment. For example, if the number of changes n in FIG. 28 is "5", changes are made to the gates at five locations. In the case of this embodiment, a plurality of gates are not extracted as gate information for the same critical path among the critical paths. It is highly probable that one of the critical paths will be changed from the high priority path and some of the critical paths will not meet the path extraction condition. That is, it is not necessary to change two or more gates in one critical path and sequentially make one critical path not satisfy the path extraction condition. In this embodiment, one gate is changed for each of a plurality of critical paths to increase the number of paths that do not meet the path extraction condition at the same time, and timing tuning is performed with good balance as a whole. With respect to the critical path that does not meet the path extraction condition once, the gate information is extracted in the order of priority by repeating the above processing, and the gate is changed again. In this embodiment, although the priority is taken into consideration, the change target gate of 1 is extracted from the critical path of 1 so that the timing tuning is performed with good balance as a whole. Two or more change target gates are extracted from one critical path. With this configuration, the gates to be changed tend to be concentrated in the critical path having a higher priority than in the second embodiment. However, by increasing the number of gates to be changed, timing tuning can be performed in good balance as a whole. It is possible to secure the advantage of being made.

FIG. 23 is a block diagram of the gate information extracting means 28 employed in the logic circuit designing apparatus according to the third embodiment. That is, the gate information extraction means 28
In the critical path, the delay amount detection unit 47 calculates the total delay time determined by the delay time of the gate itself and the charging time with respect to the load capacitance of the gate included in the path extracted by the critical path extraction means 25. The total number of gates corresponding to the usage frequency detected by the usage frequency detection unit 48 and the usage frequency detection unit 48 for detecting the usage frequency of the same gate having the same total delay time obtained by the delay amount detection unit 47. A weight calculation unit 49 for obtaining a product of delay times, and a comparison order assigning unit 50 for ranking gates and information about the gates in descending order of weight calculated by the weight calculation unit 49.

That is, in the example of FIG. 18, if the path 3 and the like other than the paths 1 and 2 are extracted as the critical paths, the delay amount detecting section 47 causes the path 1, path 3 ... As shown in FIG. For, for each gate, find the sum of the delay time of the gate itself and the delay time due to the load (the product of the coefficient of the charging time for the load capacity and the number of ways),
Store in the register indicated by "total". When the sum is obtained for all critical paths, the usage frequency detection unit 48
Shows the frequency with which the gate name and the number of ways are equal, and thus the sum is equal, is used to detect the frequency used in the critical path, and to fill the frequency used as part of the table data as shown in FIG. To do. Next, the weight calculator 49
Calculates the product of the sum of the delay time of the gate itself and the delay time of the load at each gate and the usage frequency, and stores the product in the weight column of the table data in FIG. The comparison order giving unit 50
Ranks are assigned in descending order of the amount of data stored in the weight column of the table data in FIG. As a result, as shown in FIG. 35, the frequency of use is high in the critical path, and
Gates with large delay time are extracted beyond the path frame,
They are arranged in order of weight, and the pass number (generally plural in this embodiment), the delay time of the gate itself, the delay time due to the load (the product of the coefficient of the charging time with respect to the load capacity and the number of ways), and the gate itself. The sum of the delay time and the delay time due to the load and the number of ways are associated and stored in the gate information storage means 29. Note that the number to be stored is up to the set rank. It is based on the fact that only the changed portion needs to be stored. In another embodiment, only all of them are stored. This is for selecting from the stored data and making the change target or all the change targets.

The subsequent processing is basically the same as in the case of the first embodiment. For example, if the number of changes n in FIG. 28 is “5”, changes are made at once for a plurality of passes for five gates having the same gate name and the same number of ways. That is, a plurality of command paths (PATH) in FIG. 30 are embedded. In the case of the present embodiment, the changes are made at once by a plurality of passes. That is, one critical path is used in the same state by a plurality of critical paths, instead of sequentially changing two or more gates to make all the critical paths not satisfy the path extraction condition. The gates are changed all at once, and at the same time, the number of paths that do not meet the path extraction conditions is increased, and overall, well-balanced and high-speed timing tuning is performed. For critical paths that have not been met the path extraction condition once, the gate information is extracted and the gate is changed again by repeating the above process.

FIG. 24 is a block diagram of the gate information extracting means 28 employed in the logic circuit designing apparatus according to the fourth embodiment. That is, the gate information extraction means 28
Is a delay amount detection unit 51 for obtaining a total delay time determined by the delay time of the gate itself and the charging time with respect to the load capacitance of the gate included in the path extracted by the critical path extraction unit 25, and the critical path extraction. Corresponding to the path priority detection unit 52 that detects the priority information given to the path extracted by the means 25, the priority detected by this path priority detection unit, and the priority detected by the delay amount detection unit. A weight calculation unit 53 that calculates a product of the information and the information to be processed, and a comparison order assigning unit 54 that ranks the gates in order of the weight calculated by the weight calculation unit 53 and the information related to the gates.

That is, in the example of FIG. 18, if the path 3 and the like other than the paths 1 and 2 are extracted as the critical paths, the delay amount detecting section 51 causes the path 1, path 3 ... As shown in FIG. For, for each gate, find the sum of the delay time of the gate itself and the delay time due to the load (the product of the coefficient of the charging time with respect to the load capacity and the number of ways),
Store in the register indicated by "total". When the sum is obtained for all critical paths, the path priority detection unit 5
2 refers to priority information given in advance to all paths (for example, when signals are sequentially propagated through a plurality of registers, high priority is given to an upstream path).
This priority information is input together with the design information from the input means 21, stored in the net data storage means 24, and further stored in the critical path information storage means 27 as critical path data. The path priority detection unit 52 detects the order of paths based on the above priority. That is, which path is in the upper rank is checked and a rank is given, and a coefficient corresponding to this rank (for example, when five critical paths are detected, the coefficient from the upper rank is 5,
Give 4, 3, ... ) Is given to the weight calculation unit 53.
The weight calculation unit 53 obtains the product of the sum stored in the register indicated by “total” and the coefficient, and sends the result to the comparison order assigning unit 54. The comparison order assigning unit 54 compares the total delay time of the registers indicated by "total" for each of the paths 3, 1 ..., Assigns the order in descending order of delay time, and stores them in the register "order". . Further, the comparison order assigning unit 54 sorts the order of the critical paths given by the priority detecting unit 52 and the data of the register "order". As a result, as shown in FIG.
Of each critical path, the gate name with the highest product of the priority and the delay time is extracted and arranged for each critical path, and the path number, the delay time of the gate itself, and the delay time due to the load The product of the coefficient of the charging time and the number of ways), the sum of the delay time of the gate itself and the delay time due to the load, and the number of ways are associated and stored in the gate information storage means 29. Note that the number to be stored is up to the set rank. It is based on the fact that only the changed portion needs to be stored. In another embodiment, only the critical paths are stored. This is for selecting from the stored data and making the change target or all the change targets.

The subsequent processing is the same as in the case of the first embodiment. For example, if the number of changes n in FIG. 28 is "5", changes are made to the gates at five locations. In the case of this embodiment, a plurality of gates are not extracted as gate information for the same critical path among the critical paths. It is highly probable that one of the critical paths will be changed from the high priority path and some of the critical paths will not meet the path extraction condition. That is, one critical path does not mean that two or more gates are changed to sequentially make one critical path not satisfy the path extraction condition. In this embodiment, one critical gate is changed in a plurality of critical paths to increase the number of paths that do not meet the path extraction condition at the same time, and timing tuning is performed with good balance as a whole. For critical paths that have not been met the path extraction condition at one time, gate information is extracted in the order of priority of paths by repeating the above processing, and the gate is changed again.

In this embodiment, although the path priority is taken into consideration, the gate to be changed is extracted from the critical path of 1 so that the timing tuning is performed in good balance as a whole. In the embodiment, two or more change target gates are extracted from one critical path. With this configuration, the gates to be changed tend to be concentrated in the critical path having a higher priority than in the fourth embodiment. However, by increasing the number of gates to be changed, timing tuning can be performed in good balance as a whole. It is possible to secure the advantage of being made.

In addition to the above-described first to fourth embodiments, there are an embodiment in which ranks are assigned only based on the frequency of use of gates, and an embodiment in which priority is assigned based on priority of paths and frequency of use of gates. To do. Also according to these embodiments, it is possible to secure the advantage that the timing tuning is performed with good balance as a whole.

Next, the change rule management means 32 will be described in detail. The change rule management means 32 can be added to any of the embodiments described above, and the change rule management means 32 can be omitted. The change rule management means 32 can also be realized by the CPU 7 by a program in the main memory 8 like other means. That is, since it can be realized by the program of the flowcharts shown in FIGS. 38 to 40, this will be described.

When the critical path data is stored in the critical path data storage means 27, the change rule management means 32 fetches and holds the critical path data (71). Also,
The command sent from the edit command creating means 30 is fetched (72), and the command is stored as history information together with the critical path data (73). Next, the command is received by the net data creating means, new corresponding net data is created, and it is detected whether new critical path data is created in response thereto (74). When new critical path data is created, the change rule management means 32 takes in this (75) and searches the history (76) to see if the critical path targeted by the stored command has been improved. That is, it is detected whether the critical path is extracted again (77). If there is an improved critical path, a process for updating the change rule is executed (78), and if there is no improved critical path, the process returns to step 72 and continues the operation.

Two embodiments of the processing for updating the change rule executed in step 78 of FIG. 38 will be described. The first embodiment executes the processing of the flowchart shown in FIG. That is, if a register for storing the number of times of adoption is provided corresponding to each change rule shown in FIG. 5 and there is an improved critical path,
The change rule as the cause of this improvement is detected from the history information, and the value of the corresponding adoption number register is increased by "1" (81).
The change rule for the cause of improvement refers to the one change rule for adoption when the improvement is made once, and all the change rules for adoption when the improvement is made twice or more. Then, the change rule management means 32 includes a register or a timer, and the register detects whether a critical path has been extracted a predetermined number of times or the timer detects whether a predetermined time or more has elapsed (8
2) If the critical path has been extracted a predetermined number of times or if a predetermined time or more has elapsed, the change rules are rearranged for each gate name column in descending order of the number of times of adoption (83). .

On the other hand, in the embodiment shown in FIG. 40, when there is an improved critical path, the change rule that causes the improvement is detected from the history information, and the change rule is ranked higher in the gate name column. It is detected whether another change rule exists, and if another change rule exists in the higher rank, the change rule causing the improvement is arranged in one or more stages in the upper rank (85).

Thus, the change rule in the change rule storage means 31 is moved up and down for each gate name column. For this reason, between the plurality of change rules in which the delay time and the number of ways are overlapped, the effective change rule is arranged in a higher order to ensure quick timing tuning.

In the above embodiment, the case where the path delay time is large with respect to the path extraction condition has been described. However, when the path delay time is too small with respect to the path extraction condition, another change rule is used. Similarly, timing tuning is performed using. Furthermore, the configuration of the system may be changed as necessary, such as a system in which each unit and each unit are connected by a network other than the embodiment shown in FIGS. 2 and 3.

[0079]

As described above in detail, according to the invention described in claim 1 of the present application, by inputting the design information of the logic circuit, the net data is automatically created and the path corresponding to the condition is automatically created. Extraction, detection of gate to be changed and extraction of information related to this gate, selection of gate having information regarding new gate corresponding to condition, instruction to change to new selected gate, change to new net data Is repeated, the timing of the logic circuit is tuned according to the signal conditions in the path.

As described in detail above, claim 2 of the present application
According to the invention described in (1), in the detection of the gate to be changed and the extraction of the information related to this gate, the gates to be changed are ranked, and the gates having a higher order are changed to a predetermined number of gates. Therefore, by appropriately setting the predetermined rule of ranking, it is ensured that the timing tuning is performed in a well-balanced manner in consideration of the whole even in the case of a large-scale logic circuit.

As described in detail above, claim 3 of the present application
According to the invention described in (1), the path between the two registers corresponding to the signal delay time condition is appropriately extracted, and for this path, detection of the gate to be changed, extraction of information related to this gate, and condition correspondence are performed. The selection of the gate having the information related to the new gate, the instruction to change to the selected new gate, and the change to the new net data are repeated, so that the path has a delay time within an appropriate delay time. Timing tuning is done.

As described in detail above, claim 4 of the present application
According to the invention described in (4), even in the case of a large-scale logic circuit, considering the whole, from a particularly problematic gate portion, or from a path portion particularly important in the logic circuit, or a gate that is often used. It becomes possible to perform timing tuning in a well-balanced manner either from the part or by a combination of these.

As described in detail above, claim 5 of the present application
According to the invention described in (1), by inputting the design information of the logic circuit, the net data is automatically created, the path corresponding to the condition is extracted, the gate to be changed is detected, and the information related to this gate is extracted, The selection of the gate having the information regarding the new gate corresponding to the condition, the instruction to change to the selected new gate, the change to the new net data are repeated,
The timing of the logic circuit is tuned according to the signal conditions in the path.

As described in detail above, claim 6 of the present application
According to the invention described in (1), in the detection of the gate to be changed and the extraction of the information related to this gate, the gates to be changed are ranked, and a predetermined number of gates are changed from the gate with the higher order. Therefore, by appropriately setting the predetermined rule of ranking, it is ensured that the timing tuning is performed in a well-balanced manner in consideration of the whole even in the case of a large-scale logic circuit.

As described in detail above, claim 7 of the present application
According to the invention described in (1), the gates and the information related to the gates are ranked in the order of the gate having the longest total delay time, and the gates from the highest rank to a predetermined number of gates are changed. Therefore, even in the case of a large-scale logic circuit, it is ensured that the gate having a large total delay time is subjected to timing tuning in good balance in consideration of the whole.

As described in detail above, claim 8 of the present application
According to the invention described in (3), the gates and the information related to the gates are ranked in the order of the gate having the longest delay time in the path according to the path priority, and the gates from the high order gate to the predetermined number are gated. Be changed. Therefore, even in the case of a large-scale logic circuit, it is possible to ensure that the timing tuning is performed in a well-balanced manner for the gate having a high path priority and a large total delay time in consideration of the whole.

As described in detail above, claim 9 of the present application
According to the invention described in (1), the gates and the information related to the gates are ranked by weighting the product of the usage frequency and the total delay time of the corresponding gates. To be done. For this reason,
Even in the case of a large-scale logic circuit, it is possible to ensure that the timing tuning is performed in a well-balanced manner with respect to the gate that has a large weight due to the total number of delay times of the gate corresponding to the frequency of use in consideration of the whole.

As described in detail above, claim 1 of the present application
According to the invention described in 0, the product of the path priority and the total delay time is used as a weight, and the gates and the information related to the gates are ranked for each critical path in descending order of the weight. A predetermined number of gates are changed depending on the frequency. Therefore, even in the case of a large-scale logic circuit, it is possible to ensure that well-balanced timing tuning is performed in consideration of the weight of the product of the path priority and the total delay time and the path priority in consideration of the whole.

As described in detail above, claim 1 of the present application
According to the invention described in item 1, the order of the rules stored in the change rule storage means is changed based on the history information of the critical path data and the change rule adopted when changing the gate. That is, according to the success or failure of the timing tuning of the logic circuit based on the rule, the order of the change rules is changed so that the appropriate rule is selected, and the speed of the tuning process is increased.

As described in detail above, claim 1 of the present application
According to the invention described in 2, the path between the two registers corresponding to the condition of the signal delay time is appropriately extracted, and for this path, detection of a gate to be changed, extraction of information related to this gate, and condition correspondence. Selection of the gate having the information related to the new gate, the instruction to change to the selected new gate, and the change to the new net data are repeated, so that the path has a delay time within an appropriate delay time. The timing tuning is done.

As described in detail above, claim 1 of the present application
According to the invention described in 3, the change rule matching the gate name, the delay time, and the number of ways of the change rule storage means is selected for the gate extracted by the gate information extraction means, and the signal between the both ends of the path is selected. The logic is appropriate, and a path configuration with a new gate that matches the number of branches (the number of ways) in the middle of the path is secured. That is, the timing of the logic circuit is automatically tuned according to the signal conditions in the path.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a logic circuit design device according to an embodiment of the present invention.

FIG. 2 is a perspective view showing an example of a computer system that constitutes a logic circuit designing apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram of an example of a computer system that configures a logic circuit designing device according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of stored contents of cell data storage means employed in the logic circuit designing apparatus according to the embodiment of the present invention.

FIG. 5 is a diagram showing an example of stored contents of a change rule storage means adopted in the logic circuit designing apparatus according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a change rule adopted in the logic circuit designing device according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a change rule adopted in the logic circuit designing device according to the embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of a change rule adopted in the logic circuit design device according to the embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of a change rule adopted in the logic circuit designing device according to the embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of a change rule adopted in the logic circuit designing device according to the embodiment of the present invention.

FIG. 11 is a diagram illustrating an example of a change rule adopted in the logic circuit designing device according to the embodiment of the present invention.

FIG. 12 is a diagram for explaining an example of a change rule adopted in the logic circuit designing device according to the embodiment of the present invention.

FIG. 13 is a flowchart illustrating a method for designing a logic circuit according to an embodiment of the present invention.

FIG. 14 is a diagram showing an example of design information input to a logic circuit designing apparatus according to an embodiment of the present invention.

FIG. 15 is a circuit diagram of a logic circuit designed by a logic circuit designing apparatus according to an embodiment of the present invention.

FIG. 16 is a diagram showing an example of net data created corresponding to design information input to a logic circuit designing apparatus according to an embodiment of the present invention.

FIG. 17 is a diagram for explaining the configuration of critical path data extracted in the logic circuit design device according to the embodiment of the present invention.

FIG. 18 is a diagram showing an example of critical path data extracted in the logic circuit design device according to the embodiment of the present invention.

FIG. 19 is a diagram showing an example of a circuit configuration of a critical path extracted in the logic circuit designing apparatus according to the embodiment of the present invention.

FIG. 20 is a diagram showing an example of a circuit configuration of a critical path extracted in the logic circuit designing apparatus according to the embodiment of the present invention.

FIG. 21 is a block diagram of an essential part of a logic circuit designing apparatus according to an embodiment of the present invention, which is a block diagram of the first embodiment.

FIG. 22 is a block diagram of an essential part of a logic circuit designing apparatus according to an embodiment of the present invention, and is a block diagram of a second embodiment.

FIG. 23 is a block diagram of essential parts of a logic circuit designing apparatus according to an embodiment of the present invention, and is a block diagram of a third embodiment.

FIG. 24 is a block diagram of an essential part of a logic circuit designing apparatus according to an embodiment of the present invention, which is a block diagram of a fourth embodiment.

FIG. 25 is a diagram for explaining ranking according to the first embodiment of FIG. 21.

FIG. 26 is a diagram showing an example of gate information extracted by the first embodiment of FIG. 21.

FIG. 27 is a flowchart illustrating a gate changing process in the logic circuit designing device according to the embodiment of the present invention.

FIG. 28 is a flowchart illustrating a gate changing process in the logic circuit designing device according to the embodiment of the present invention.

FIG. 29 is a diagram showing a delay time in a path after undergoing gate change processing by the logic circuit designing device according to the example of the present invention.

FIG. 30 is a diagram showing an example of a command for requesting gate change which is fed back by the logic circuit designing device according to the embodiment of the present invention.

FIG. 31 is a diagram for explaining ranking according to the second embodiment of FIG. 22.

FIG. 32 is a diagram showing an example of gate information extracted by the second embodiment of FIG. 22.

FIG. 33 is a diagram for explaining ranking according to the third embodiment of FIG. 23.

FIG. 34 is a diagram for explaining ranking according to the third embodiment of FIG. 23.

FIG. 35 is a diagram showing an example of gate information extracted according to the third embodiment of FIG. 23.

FIG. 36 is a diagram for explaining ranking according to the fourth embodiment of FIG. 24.

FIG. 37 is a diagram showing an example of gate information extracted by the fourth embodiment of FIG. 24.

FIG. 38 is a flowchart illustrating a change rule management operation in the logic circuit design device according to the embodiment of the present invention.

FIG. 39 is a flowchart illustrating in detail a main part of a change rule management operation in the logic circuit designing device according to the embodiment of the present invention.

FIG. 40 is a flowchart illustrating in detail a main part of a change rule management operation in a logic circuit designing device according to another embodiment of the present invention.

[Explanation of symbols]

1 Main Body 2 Keyboard Input Device 3 CRT Display Device 4 Printer Device 5 Mouse 6 Magnetic Disk Storage Device 7 CPU 8 Main Memory 9 Bus 10-14 Interface 21 Input Means 22 Net Data Creation Means 24 Net Data Storage Means 25 Critical Path Extraction Means 26 Cell data storage means 27 Critical path data storage means 28 Gate information extraction means 29 Gate information storage means 30 Edit command creation means 31 Change rule storage means 32 Change rule management means 33 Output control means 34 Output means 41, 45, 4
7, 51 Delay amount detecting unit 42, 44, 50, 54 Comparison order assigning unit 43 Path priority detecting unit 46 In-path data rank assigning unit 48 Usage frequency detecting unit 49, 53 Weight calculating unit 52 Priority detecting unit

Claims (13)

[Claims] 1. A step of creating net data representing a gate and a register to be used based on input design information of a logic circuit and a relationship between input / output of signals to and from the gate and the register, and information on delay time related to the gate The step of extracting a path based on the condition of the signal in the path between the two registers in the net data and the net data, and the information on the delay time regarding the gate are referred to, and the path extracted in the step is referred to. Based on the change rule in which the gate to be changed is detected and the information related to this gate is extracted, and the information related to the gate to be changed and the information related to the gate to be changed are associated with each other. , Regarding the extracted gate to be changed, information regarding a new gate corresponding to the condition is included. Selecting a gate to be changed, giving an instruction to change the gate to be changed to the new gate selected in the step, and changing the net data to a new net data in response to the instruction. The method of designing a logic circuit is characterized in that the logic circuit is designed by repeating the above steps. 2. A step of creating net data representing a gate and a register to be used on the basis of design information of a logic circuit to be input and an input / output relationship of signals to and from the gate and the register, and information on a delay time regarding the gate The step of extracting a path based on the condition of the signal in the path between the two registers in the net data and the net data, and the information on the delay time regarding the gate are referred to, and the path extracted in the step is referred to. For the included gates, a step of detecting a gate to be changed, extracting information on the gate, and ranking the gates to be changed based on a predetermined rule, information on the gate to be changed, and an object to be changed Based on the change rule associated with the information related to the gate to be changed, the extracted change target A gate having information relating to a new gate corresponding to the condition is performed for a predetermined number of gates from the gates having a higher order, and the gate to be changed is selected in the step. A step of giving an instruction to change to a new gate, and a step of changing the net data to new net data in response to the instruction, and designing a logic circuit by repeating the steps. A method of designing a logic circuit characterized by. 3. The signal condition is a signal delay time in a path between two registers.
Alternatively, the logic circuit designing method according to claim 2. 4. The predetermined rule is that the total delay time determined by the delay time of the gate itself and the charging time with respect to the load capacitance is large, the priority of the path is high, and the number of used paths in the extracted path. 4. The method for designing a logic circuit according to claim 2, wherein the gate is a large gate, or a combination thereof. 5. Input means for inputting information, gates and registers to be used based on design information of a logic circuit inputted from the input means, and net data representing input / output relations of signals to and from these gates and registers. Net data creating means to be created, cell data storing means in which information about delay time regarding the gate is stored, information stored in this cell data storing means and signals in a path between two registers in the net data Based on the condition, the critical path extracting means for extracting the path according to the condition from the net data created by the net data creating means, and the information related to the delay time regarding the gate are extracted by the critical path extracting means. For gates included in the specified path, the gate that should be changed is detected and this gate is Gate information extraction means for extracting information related to the gate, change rule storage means for storing change rule information in which information related to the gate to be changed and information related to the gate to be changed are stored, Edit command creating means for selecting a rule relating to a gate having information relating to the new gate corresponding to the condition for the gate to be changed extracted by the gate extracting means, based on the information stored in the change rule storing means, A logic circuit designing device, wherein the net data creating means creates net data for changing to a new gate based on the rule selected by the edit command creating means. 6. Input means for inputting information, gates and registers used on the basis of design information of a logic circuit input from the input means, and net data representing input / output relations of signals to and from these gates and registers. Net data creation means to be created, cell data storage means in which information on delay time regarding the gate is stored, and information stored in the cell data storage means and signals in a path between two registers in the net data. Based on the condition, the critical path extracting means for extracting the path according to the condition from the net data created by the net data creating means, and the information related to the delay time regarding the gate are extracted by the critical path extracting means. For gates included in the specified path, the gate that should be changed is detected and this gate is Information related to the gate to be changed, and the gate information extraction means for ranking the gate to be changed based on a predetermined rule, and the information related to the gate to be changed and the information related to the gate to be changed are associated with each other. Based on the information stored in the change rule storage means, the change rule storage means in which the information of the obtained change rule is stored, and from the top of the order to the predetermined number among the gates ranked by the gate information extraction means. Edit command creating means for selecting a rule relating to a gate having information relating to the new gate corresponding to the condition for the gate to be changed, and the net data creating means applies the rule selected by the edit command creating means to the net data creating means. An apparatus for designing a logic circuit, characterized in that net data is created based on the change to a new gate. 7. The gate information extraction means obtains a total delay time of gates included in the paths extracted by the critical path extraction means, the total delay time being determined by the delay time of the gate itself and the charging time with respect to the load capacitance. 6. A detection unit, and a comparison order assigning unit that ranks the gates and the information related to the gates in the order of the gate having the largest total delay time obtained by the delay amount detection unit. A device for designing a logic circuit according to claim 6. 8. The gate information extracting means includes a path priority detecting section for detecting priority information given to a path of net data, and a critical path extraction according to the priority detected by the path priority detecting section. The comparison rank assigning unit that ranks the paths extracted by the means, and for each of the paths ranked by the comparison rank assigning unit, the delay time of the gate itself and the charging time for the load capacitance for the gates included in the path. The delay amount detecting unit for obtaining the total delay time determined by the above, and the gate and the information related to this gate are ranked in the path in the order of the gate having the large total delay time obtained by this delay amount detecting unit. 7. The device for designing a logic circuit according to claim 5, further comprising an in-path data rank assigning unit. 9. The gate information extraction means delays for a gate included in the critical path extracted by the critical path extraction means to obtain a total delay time determined by the delay time of the gate itself and the charging time with respect to the load capacitance. Quantity detection unit, a usage frequency detection unit that detects the usage frequency of the same gate having the same total delay time and the number of ways obtained by the delay amount detection unit in the critical path, and the usage frequency detection unit. Weight calculation means for calculating the product of the number of times of use and the total delay time of the corresponding gate, and a comparison order assigning part for ranking the gates and information related to the gates in descending order of weight calculated by the weight calculation means. 7. The logic circuit design apparatus according to claim 5, further comprising: 10. The gate information extraction means delays for a gate included in the critical path extracted by the critical path extraction means to obtain a total delay time determined by the delay time of the gate itself and the charging time with respect to the load capacitance. An amount detection unit, a path priority detection unit that detects priority information of the critical path based on priority information given to the net data path, and priority information detected by the path priority detection unit. Weight calculation means for calculating the product of the total delay time detected by the delay amount detection part, and a gate and information related to the gate for each critical path in descending order of weight calculated by the weight calculation means. 7. The apparatus for designing a logic circuit according to claim 5, further comprising: 11. The net data created by the net data creating means based on the design information of the logic circuit or in response to the edit command, the critical path data extracted by the critical path extracting means, and the rule selected by the edit command creating means. 11. A change rule management unit that captures and holds the rule and changes the order of the rules stored in the change rule storage unit based on the critical path data and the rule. A device for designing a logic circuit according to claim 1. 12. The logic circuit designing apparatus according to claim 5, wherein the signal condition is a signal delay time in a path between two registers. 13. The change rule storage means stores a change rule determined by the delay time and the number of ways in association with the gate name, and the edit command creating means is stored by the gate information extracting means. 6. A change rule associated with a gate name, a delay time, a gate name that matches the number of ways, a delay time, and the number of ways of the extracted gate is selected from the change rule storage means. Item 13. A logic circuit design device according to any one of items 12.