JPH07262087A - Processor - Google Patents

Abstract

PURPOSE:To provide a processor which controls a register bank in order to enable the mapping area of general-purpose register to keep out of saving area of a control register and can improve the register-using efficiency and the program-executing speed. CONSTITUTION:This processor is provided with a state control part 1 which generates a bank RAM address with a current bank pointer and the bank size and performs the bank switch control when true mapping (saving/returning) of data is performed between a RAM and a register, a latch circuit L31 which stores the saving area vague of the RAM of a control register, and an address generating part 7 which changes the bank RAM address when the saving area value is coincident with the bank RAM address and generates a new bank RAM address to change the mapping area of the bank RAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a RAM (random
The present invention relates to a processor having a register bank which is configured to connect the access memory) and a general-purpose register via a bus, and which is configured to match the contents of the RAM indicated by the current bank pointer with the contents of the general-purpose register and which is switch-controlled.

[0002]

2. Description of the Related Art General-purpose registers and bank RAMs (hereinafter RA
(Referred to as M) by a high-speed bus to match the contents of the RAM indicated by the bank pointer with the contents of the general-purpose register. By designating the bank pointer (CBP), as shown in FIG. 6, the data of the general-purpose register is the RAM of the address given by the original CBP (old CBP).
Saving the area, rewriting the CBP, restoring the data from the RAM area at the address given by the rewritten CBP to the general-purpose register, and switching the bank to perform bank mapping (saving / restoring) and task change. In this case, the register data is automatically saved / restored via the bank bus.

Such control of the register bank is performed by, for example, a register bank controller shown in FIG. 7 provided in the processor.

In FIG. 7, for example, when the general-purpose register is 16 bits × 16, four registers are one bank, and the save area of the control register is (CBP-1), the state control unit 1 has an arithmetic control unit (FIG. C given by (not shown)
In response to the BP rewrite control signal (CBPC) and the bank size (BS) designated by the bank size designation register, the read / write signal (R / W), the bank address (BNK)
A) is generated, and the generated bank address is taken into the state controller 1 in synchronization with the clock signal (CLK2). Further, this bank address is added by CBP and the adder 2 to generate the latch circuit L62 (hereinafter, the numeral 1 or 2 at the end of the code of the latch circuit is the clock signal CLK1 or C).
(Indicating that it is synchronized with LK2), RA
It is output as an M address (RAMAD). The state controller 1 controls switching of four banks as shown in the state transition of FIG.

Specifically, when the instruction decoding unit decodes the instruction code and finds that the instruction involves rewriting of the CBP, the arithmetic control unit outputs a CBP rewriting control signal (CBPC) to the 16-bit register. X16
In the general-purpose register of this configuration, if four registers are set as one bank, registers R0 to R3 (bank 1), R4
To R7 (bank 2), R8 to R11 (bank 3), R1
2 to R15 (bank 4) are each one bank, and data transfer between the general-purpose register and the RAM is performed one bank at a time through the bank bus in units of 64 bits.

Next, the saving / restoring operation of the general-purpose register will be described.

The data of the general purpose register is transferred from the bank 1 to the bank (BS + 1) indicated by the bank size of the bank size designation register in order from the general purpose register to the RAM area of the address (CBP × 8). That is, banks 1 to 4 are CBP × 8 and (CBP +
1) × 8, (CBP + 2) × 8, (CBP + 3) × 8. Then, in the cycle in which the transfer from the general-purpose register to the RAM ends, C
The write request signal of BP is latched, and CBP is written from the data register via the internal bus. From the next cycle, data transfer from the (new CBP × 8) RAM area to bank 1 is started. Below, Bank 2
4 are similarly transferred.

Next, the operation of the bank controller during the CBP rewriting control will be described.

In the bank controller, the bank address and RA
M addresses are generated, and read / write control is performed for each. The bank address at the time of CBP transfer is, for example, 2 bits and corresponds to 00 (bank 1), 01 (bank 2), 10 (bank 3), and 11 (bank 4). Therefore, the bank address is set to "00" at the start of rewriting of the CBP and incremented by one for each clock. RAM address is CBP
And the bank address are added, and the value is obtained by shifting left by 3 bits. In this way, since the bank address is calculated by incrementing, consecutive (BS + 1) banks are saved / restored when the CBP is rewritten.

In such a bank switching operation,
When the CBP is rewritten so that the mapping area of the general purpose register of the old CBP and the mapping area of the general purpose register of the new CBP (new CBP) are rewritten, the parameter can be passed.

The transfer of parameters by bank change is performed by subtracting CBP as a result.
When the general-purpose register has, for example, a 4-bank configuration, CBP can be designated as the destination of an arbitrary instruction, and the parameter can be passed when the operation result is within the bank size (BS) and smaller than the current CBP.

On the other hand, the RAM is also used for saving / restoring general purpose registers when an interrupt occurs. Therefore, in the task using the RAM, the RAM area of (CBP-1) × 8 is set as the save area for the control register such as the program counter and the processor status word, and the control register is saved in this area when an interrupt occurs. To be done.

However, in the register bank configuration as described above, the save area of the control register divides the data area of the general-purpose register into 1 to 4 banks, so that the parameters are transferred by superimposing the mapping areas of the general-purpose register. It may be an obstacle.

In the case of passing parameters at the time of subroutine call, there is no particular problem because the area other than the passed variables is the work area. However, if the variables handled by the program are larger than the number of general-purpose registers, it may be desirable to perform bank switching to minimize memory access. However, since non-maskable interrupts (NMI) cannot be prohibited, parameters cannot be made resident in the save area for control registers.

For example, when CBP is subtracted by "2" and two banks are used for passing parameters, among the two banks which can be newly used as a data area, the registers R4 to R4.
Since the RAM area corresponding to R7 is used for saving the control register when an interrupt occurs in the old CBP, the CBP
Can be used only as an intermediate variable after rewriting.

For this reason, when it is desired to use the registers R4 to R7 as a data area, it is necessary to load necessary data from another data area into a general-purpose register by an instruction and store the CBP before writing it back. Therefore, memory access becomes necessary and the execution time becomes long.

[0017]

As described above,
In the conventional bank switching control, the result of shifting the value obtained by adding the bank address and CBP to the left by 3 bits is used as the RAM address of the mapping area of the bank.
The RAM in the mapping area of the general-purpose register is continuous (BS +
1) It corresponded to the bank.

Therefore, the bank address and the RAM address cannot be controlled independently, the use efficiency of the register is deteriorated, and the execution speed of the program is lowered.

In addition, the interrupt save area sometimes overlaps with the data area of the general-purpose register, which causes a problem that the program is restricted to avoid this.

Therefore, the present invention has been made in view of the above, and a first object thereof is to control a register bank so that a mapping area of a general-purpose register avoids a saving area of a control register, It is to provide a processor with improved register usage efficiency and increased program execution speed.

A second object is to provide a processor with a high degree of programming freedom by avoiding duplication of the control register save area and the general register data area at the time of interruption. .

[0022]

In order to achieve the above object, the invention according to claim 1 is such that when data mapping (saving / restoring) is performed between a banked RAM and a register, A state control unit that controls a bank switching by generating a bank RAM address that is a bank address and a RAM access address by receiving a current bank pointer (CBP) and a bank size, and a register data mapping area on the RAM. When the CBPs are rewritten so as to overlap, a save area value indicating the save area on the RAM of the control register is calculated and stored until the mapping ends, and when the save area value and the bank RAM address match. From the address changing unit that changes the RAM address and generates a new bank RAM address that changes the mapping area of the RAM It is made.

According to a second aspect of the present invention, in the first aspect of the invention, the address changing unit is a new CBP and an old CB.
When P and P are held and CBP is rewritten so that the mapping areas of the register data on the RAM overlap,
A discriminating unit that discriminates an increase / decrease of the current bank pointer by comparing the stored values, and a save region value indicating a save region on the RAM of the control register from the old CBP held by the discriminating unit, and the calculated save A storage unit that captures an area value based on the determination result of the determination unit and stores the data until the mapping of data is completed, a save area value stored in the storage unit, and a bank RAM generated by the state control unit
The address is compared with each other, and when the two match, the comparison unit that outputs the skip value of the preset bank RAM address, and the bank RAM address generated by the state control unit to the skip value output from the comparison unit Add RA
And an address generation unit that generates a new bank RAM address that changes the M address and changes the mapping area of the bank RAM.

According to the invention of claim 3, in the invention of claim 2, when the CBP is rewritten by an instruction, the CBP is changed.
After the instruction is decoded for the instruction whose relative increase / decrease is found from the decoding result, the save area of the control register and the new CB
The instruction decoding unit is provided with a discriminating circuit for discriminating whether or not the mapping areas of the register indicated by P overlap each other, and the memory circuit is configured to fetch and store the save area value according to the discrimination result of the discriminating circuit.

According to a fourth aspect of the invention, in the invention according to the second or third aspect, the plurality of storage units, the plurality of comparison units provided respectively corresponding to the plurality of storage units, and the storage unit are provided. It is composed of a demultiplexer for controlling the storage area to be stored in each storage unit, and a logic gate for giving a logical sum of comparison results of a plurality of comparison units to the address generation unit.

[0026]

In the above structure, the invention according to claim 1 or 2 is a control register when a bank change is performed by rewriting a CBP by an instruction, particularly when parameter mapping is performed by superimposing register mapping areas. The register bank is controlled so as to avoid the save area and become the mapping area of the general-purpose register.

According to the third aspect of the present invention, the instruction decoding unit determines whether or not the save area and the mapping area of the register indicated by the new CBP overlap immediately after the instruction is decoded.

According to a fourth aspect of the present invention, a plurality of save areas after the execution of the program are stored so that the parameters can be transferred in multiple ways.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a processor according to an embodiment of the invention described in claim 1 or 2. In the embodiment shown in FIG. 1, the save / restore area of the general-purpose register skips the save area of the control register at the time of interrupt, and the RAM address can be controlled independently.

In FIG. 1, a register bank control unit for controlling register bank switching includes a state control unit 1 and an adder 2 similar to those shown in FIG. 7, a latch circuit L12 for receiving and latching a new CBP, and a CBP. Latch circuit L22 for latching and latching the old CBP by inputting the rewriting signal (CBPC) of the latch circuit L12, L22
The new CBP-old CBP is subtracted from the CPB held in the table, and the two are compared. When the comparison result becomes negative, the negative CBP rewrite signal (NCBPC) is output.
Of the old CB held in the latch circuit L22 and the discriminator composed of the subtractor 3 for discriminating the increase / decrease (rewriting direction) of the CBP.
The second subtracter 4 which subtracts "1" from P (old CBP-1) to calculate the save area of the control register of the old CBP in the RAM, and the calculated content is latched to control the control register of the old CBP. A save area calculation storage unit including a latch circuit L31 serving as a storage circuit for storing the save area, the content latched by the latch circuit L31, and the output of the adder 2 (ADD
OUT) and a match detection signal (HIT) of "1" level when they match, a latch circuit L42 for latching the HIT signal, and a state control section 1
Latch circuit L42 when the state of the bank is received in the idle state (IDLE) or the state of the bank 1 or the HIT signal is at 1 level by receiving the bank address from
Timing circuit 6 for instructing latching, and latch circuit L52 for latching RAM address
42, L52, and a RAM address generation unit including an adder 7 that calculates the RAM address (RAMAD) of the third bit and thereafter by adding the latched contents to the determination unit and the save area calculation storage. The unit, the comparator 5, the timing circuit 6, and the RAM address generation unit constitute an address changing unit that changes the RAM address.

The comparison between the old and new CBP is made based on the subtraction of (new CBP-old CBP).
The NCBPC signal may be output when the subtraction result becomes positive by subtraction of (new CBP).

In this configuration, in this embodiment, when the output of the adder 2 and the (old CBP-1) are equal to each other, they are equal to each other, a "1" is added to the third bit of the RAMAD to determine the RAM address. It is calculated and the mapping area of the general-purpose register is changed as shown in FIG.
The specific operation will be described below.

First, the old and new CBPs are compared to determine whether the CBP is rewritten in the positive or negative direction. The new CBP is latched by CLK2 (clock signal), the old CBP is latched only when the CBPC signal is input to the latch circuit L22, and the result of (new CBP-old CBP) is negative (or the result of old CBP-new CBP). Becomes positive, a negative CBP rewrite signal (NCBPC) is output.

Also, "1" is subtracted from the old CBP,
(Old CBP-1) is generated. This content is NCBPC
It is latched on CLK1 (clock signal) only when the signal becomes active. (Formerly CBP-1) and C
Output of 8-bit adder 2 synchronized with LK1 (ADDO
UT) is compared, and if they match, a HIT signal of "1" level is output. The HIT signal is latched by CLK2 when the state state of the bank is IDLE, bank 1 or "1" level.

Therefore, HIT = 1, which is a kip value, is added to all the RAM addresses for saving / restoring after the bank where the HIT signal becomes active. When the saving / restoring of the bank (BS + 1) is completed, the HIT signal is reset again. As a result, when the latched output of the HIT signal and ADDOUT latched by CLK2 are added, the third bit or more of RAMAD can be obtained.

Since the general-purpose registers are saved / restored based on the RAM address calculated in this way,
The general-purpose register save / restore area can skip the control register save area at the time of interrupt, and RA
The M address can be controlled independently of the bank address. Therefore, when performing a bank change by rewriting the CBP with an instruction, especially when passing the parameters by overlapping the mapping areas of the registers, avoid the save area of the control register to become the mapping area of the general-purpose register. It becomes possible to control the register bank.

As a result, the use efficiency of the register is improved, the program execution speed is improved, the interrupt save area does not overlap with the data area of the general-purpose register, and the degree of freedom in programming can be increased.

FIG. 3 is a diagram showing a configuration of a processor according to an embodiment of the present invention. The feature of the embodiment shown in FIG. 3 is that a decision circuit (CHKCBP) 31 for deciding whether or not the save area of the control register and the mapping area of the general-purpose register overlap is provided in the instruction decoding unit (DEC) of the processor. The other configuration is the same as that of the embodiment shown in FIG.

In FIG. 3, the bus interface (B
The instruction code fetched by the IU)
EC) to generate a micro address. The control of each block is determined by the microcode obtained according to the microaddress. Instructions to the arithmetic destination and arithmetic unit (ALU) are also obtained here.

Therefore, in the case of an instruction such as addition / subtraction in which the relative increase / decrease in CBP is clear, it is possible to determine the possibility that the mapping area of the general-purpose register and the save area of the control register overlap at this point. For example, if the save area of the control register is (C
In the case of BP + 4), overlap occurs in the case of old CBP + 5-BS <new CBP <old CBP + 5. A discriminating circuit (CHKCB) for discriminating whether or not duplication of general-purpose registers occurs based on the above equation.
P) 31 is provided in the DEC, and a region overlap signal (BNKCNF) is output to the register bank control unit (BNKC) 32 according to the determination result.

By this signal BNKCNF, as shown in the register bank controller (BNKC) 32 of FIG.
The contents of (old CBP-1) are latched by the latch circuit L31 similar to that shown in FIG. 1, and the operation thereafter is the same as that of the embodiment shown in FIG.

Therefore, also in such an embodiment, the same effect as the above embodiment can be obtained, and
Latch circuit L1 forming a comparison unit in the bank control unit
2 and the subtractor 3 are unnecessary, and the structure can be downsized. .

FIG. 5 is a diagram showing the configuration of a processor according to an embodiment of the present invention. The feature of the embodiment shown in FIG. 5 is that it can be applied even in the case where the parameters are transferred in multiples.

The above-described embodiment is effective only when the parameters are exchanged by switching the banks and when the parameters are not multiplexed. When multiple parameters are passed or when an unspecified CBP is changed by a transfer instruction or the like twice or more, only one set of the latch circuit L31 stores the save area of the control register. It is not possible to detect the overlap between the save area of the control register and the mapping area of the general-purpose register.

In this embodiment, the number of latches serving as a memory circuit for storing the save area of the control register is increased so that a plurality of values can be held.

The storage capacity of the storage circuit for storing the save area of the control register may be any size, and various structures and storage methods of the storage circuit are conceivable.

However, as an embodiment in which there is no waste in execution time, as shown in FIG. 5, a plurality of latch circuits L31 shown in the above-mentioned embodiment are provided in parallel and used by the program up to that time (old CBP- By holding the values of 1) in order, whether or not the mapping area of the general-purpose register and the held contents match is compared at the same time by the comparator 51 provided corresponding to the latch circuit L31, Either one
If there is any match, the HIT signal output from the corresponding comparator 51 via the OR gate 52 is set to "1" and added to ADDOUT. The content given to and latched by each latch circuit L31 is the signal C
Based on the output of the counter 53, which is incremented by 1 each time the BPC becomes active, the demultiplexer 5
4 supplied. The subsequent operation is similar to that of the embodiment shown in FIG.

Therefore, in such an embodiment, it is possible to obtain the same effect as that of the above-mentioned embodiment, and it is possible to pass the parameters in a multiple manner. It is effective when used.

[0050]

As described above, according to the first or second aspect of the invention, when a bank change is realized by rewriting the CBP with an instruction, the mapping areas of the registers are overlapped and the parameters are passed. In this case, the register bank is controlled so as to avoid the save area of the control register and become the mapping area of the general-purpose register, so that the register usage efficiency is improved, the program execution speed is increased, and the interrupt The save area does not overlap with the data area of the general-purpose register, and the degree of freedom in programming can be increased.

According to the third aspect of the present invention, since the discriminating circuit for discriminating whether or not the save area and the mapping area of the general-purpose register overlap is provided in the instruction decoding section, the configuration of the address changing section is small. Can be converted.

According to the invention as set forth in claim 4, since a plurality of save areas are stored, it becomes possible to pass and receive parameters in a multiplexed manner, and the frequency of bank changes is high and a large number of general-purpose registers are used. It will be effective if.

[Brief description of drawings]

FIG. 1 is a diagram showing a main part configuration of a processor according to an embodiment of the invention described in claim 1 or 2;

FIG. 2 is a diagram showing a state of mapping in a register bank of the present invention.

FIG. 3 is a diagram showing a main configuration of a processor according to an embodiment of the invention as set forth in claim 3;

FIG. 4 is a diagram showing a configuration of a bank controller shown in FIG.

FIG. 5 is a diagram showing a main configuration of a processor according to an embodiment of the invention as set forth in claim 4;

FIG. 6 is a diagram showing a state of mapping in a conventional register bank.

FIG. 7 is a diagram showing a configuration of a bank controller in a conventional processor.

8 is a diagram showing state transitions of banks controlled by the bank control unit shown in FIG.

[Explanation of symbols]

 1 State Control Unit 2,7 Adder 3,4 Subtractor 5,51 Comparator 6 Timing Circuit 31 Discrimination Circuit 32 Bank Control Unit 52 Logic Gate 53 Counter 54 Demultiplexer L12 to L82 Latch Circuit

Claims (4)

[Claims] 1. A current bank pointer (CBP) and a bank size are received when data mapping (saving / restoring) is performed between a banked RAM and a register,
When the CBP is rewritten so that the bank address and the bank RAM address, which is the access address of the RAM, are generated and the bank switching control is performed, and the mapping area of the register data on the RAM overlaps. The save area value indicating the save area on the RAM is stored and stored until the mapping ends, and the save area value and the bank RAM are stored.
If the address matches, change the RAM address,
An address changing unit for generating a new bank RAM address for changing a mapping area of the RAM. 2. The address changing unit holds the new CBP and the old CBP, and compares the held values when the CBP is rewritten so that the mapping areas of the register data on the RAM overlap. A discriminator that discriminates whether the current bank pointer is increased or decreased, and a save area value indicating a save area on the RAM of the control register is calculated from the old CBP held by the determiner.
A storage unit that captures the calculated save area value based on the determination result of the determination unit and stores the data until the mapping of data is completed, the save area value stored in the storage unit, and the bank RAM address generated by the state control unit. When the two match, the comparison unit that outputs the skip value of the preset bank RAM address and the bank RAM address generated by the state control unit are added to the skip value output from the comparison unit. 2. The processor according to claim 1, further comprising: an address generation unit that changes a RAM address to change a mapping area of the bank RAM and generates a new bank RAM address. 3. When rewriting the CBP with an instruction, the CB
After the instruction is decoded for the instruction whose relative increase or decrease of P is found by the decoding result, the save area of the control register and the new C
The instruction decoding unit is provided with a discriminating circuit for discriminating whether or not the mapping areas of the register indicated by BP overlap, and the storage circuit captures and stores the save area value according to the discrimination result of the discriminating circuit. The processor according to claim 2, 4. A demultiplexer for controlling distribution of the plurality of storage units, the plurality of comparison units respectively provided corresponding to the plurality of storage units, and the save areas stored in the storage units to the respective storage units. 4. The processor according to claim 2, further comprising: a logic gate that gives a logical sum of comparison results of a plurality of comparison units to the address generation unit.