JPH07261711A - Liquid crystal driving method - Google Patents

Abstract

PURPOSE:To provide a liquid crystal driving method for driving various liquid crystal display panels having scanning lines and signal lines smaller in number than the output pins of a driving circuit in one and the same driving circuit. CONSTITUTION:A liquid crystal display panel 20 is provided with 480 pieces of segment lines and 146 pieces of common lines, segment drivers 18A, 18B and 18C are respectively provided with 180 pieces of output pins and common drivers 19A and 19B are respectively provided with 110 pieces of output pins. 160 pieces of segment lines are respectively connected to the segment drivers 18A, 18B and 18C in sequence from the first output pin and segment line start pulses STa, STb and STc are inputted to the action timing of the first segment line. 73 pieces of common lines are respectively connected to the common drivers 19A and 19B in sequence from the first output pin and scanning line start pulses DTa and DTb are inputted to the scanning timing of the first common line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving method.

[0002]

2. Description of the Related Art A conventional liquid crystal display device, for example, as shown in FIG. 6, outputs scanning drive signals from two scanning side drive circuits 2A and 2B to a liquid crystal display panel 1 to drive three segment side drives. The segment drive signals are output from the circuits 3A, 3B, 3C to drive the liquid crystal display panel 1 for display.

In the liquid crystal display panel 1, a plurality of segment lines and a plurality of scanning lines are formed, and a display element made of liquid crystal is formed at the intersection of each segment line and the scanning line.

In the conventional liquid crystal display device, according to the number of scanning lines and segment lines of the liquid crystal display panel 1, the scanning side driving circuits 2A, 2B and the segment side driving which correspond to the number of scanning lines and segment lines are provided. Circuit 3
A, 3B, 3C are manufactured and mounted, and the scan line is connected to each output pin of the scan side drive circuits 2A, 2B, and the segment line is connected to each output pin of the segment side drive circuits 3A, 3B, 3C. There is. That is, the scanning side drive circuit 2
All the output pins of A and 2B are connected to the scanning line, and all the output pins of the segment side drive circuits 3A, 3B and 3C are connected to the segment line.

The scanning side drive circuit 2 at the head in the scanning direction
A scan start signal is input to A from a control circuit (not shown),
The scanning side drive circuit 2A receives the scanning start signal,
The scanning drive signal is sequentially output from the output pin on the leading side in the scanning direction to the scanning line connected to the output pin. The scanning side drive circuit 2A outputs a scanning start signal to the scanning side drive circuit 2B when the scanning drive signal is sequentially output to the output pin at the end, and the scanning side drive circuit 2B receives the scanning start signal from the scanning side drive circuit 2A. When input, similarly to the scan side drive circuit 2A, the scan drive signal is sequentially output from the output pin on the leading side in the sequential scan direction to the scan line connected to the output pin.

A sampling start signal is input from a control circuit (not shown) to the segment side drive circuit 3A on the operation direction head side, and the segment side drive circuit 3A receives the sampling start signal on the operation direction head side. The display data is sequentially sampled from the side, and segment drive signals corresponding to the display data are simultaneously output to the segment lines connected to the output pins. Segment side drive circuit 3A
Outputs the sampling start signal to the segment side drive circuit 3B when the sampling start signal is sequentially shifted to the terminal output pin, and the segment side drive circuit 3B receives the sampling start signal from the segment side drive circuit 3A. Similarly to the segment side drive circuit 3A, the display data is sequentially sampled from the leading side in the operation direction and output to the segment line connected to each output pin. The segment side drive circuit 3B outputs the sampling start signal to the segment side drive circuit 3C when the sampling start signal is sequentially shifted to the output pin at the terminal end, and the segment side drive circuit 3C changes the segment side drive circuit 3B.
When a segment line start pulse is input from
Similar to the segment side drive circuit 3A, the display data is sequentially sampled from the leading side in the operation direction and the segment drive signal is output to the segment line.

In the liquid crystal display panel 1, when the segment drive signals are supplied from the segment drive circuits 3A, 3B and 3C to the scan lines to which the scan drive signals are supplied from the scan drive circuits 2A and 2B, The display element at the position where the scan line and the segment line intersect is driven for display corresponding to the display data.

The number of segment lines and scanning lines is not limited in the liquid crystal display panel 1 that is driven for display as described above. Depending on the size of the liquid crystal display panel 1, the number of segment lines and scanning lines may be different. The number of lines is, for example, 720 × 220, 540 × 220
Books, or 360 × 220, 480 × 146
There are books etc.

In the conventional liquid crystal display device, the segment side drive dedicated to the liquid crystal display panel having the number of output pins corresponding to the number of the segment lines and the scanning lines is provided according to the number of the segment lines and the scanning lines. Circuit 3
A, 3B, 3C and scan side drive circuits 2A, 2B are manufactured and mounted.

[0010]

However, in such a conventional liquid crystal display device, the number of the segment lines and the scanning lines corresponds to the number of the segment lines and the scanning lines of the liquid crystal display panel. Since the dedicated segment side driving circuit and scanning side driving circuit having the number of output pins were manufactured and attached, each time the number of segment lines and scanning lines of the liquid crystal display panel was different, It is necessary to develop and manufacture a segment side driving circuit and a scanning side driving circuit, which causes a problem that the cost of the liquid crystal display device is high and the usability of the segment side driving circuit and the scanning side driving circuit is poor.

Therefore, the present invention has been made in view of the above circumstances, and effectively uses a segment side driving circuit or a scanning side driving circuit having a larger number of pins than the number of segment lines or scanning lines of a liquid crystal display panel. It is an object of the present invention to provide a liquid crystal driving method capable of providing an inexpensive liquid crystal display device by utilizing the liquid crystal display device.

[0012]

A liquid crystal driving method of the present invention includes a plurality of scanning lines connected to output pins of a plurality of scanning side drive circuits and a plurality of scanning lines connected to output pins of a plurality of signal side drive circuits. A liquid crystal driving method for driving a liquid crystal display panel in which display elements are arranged in a matrix at each intersection of signal lines by the plurality of scanning side driving circuits and the plurality of signal side driving circuits, wherein the scanning lines are Appropriately allocated according to the number of scanning lines and the number of output pins of each scanning side drive circuit, connected to the output pins of each scanning side drive circuit, A scan line start pulse for starting scanning is input to each scan side drive circuit at a timing corresponding to the scan timing of the scan line, and the signal lines are connected to the number of the signal lines and each signal side. Timing corresponding to the operation timing of the signal line at the head of the operation direction connected to the output pin of each signal side drive circuit and appropriately allocated according to the number of output pins of the drive circuit By inputting a segment line start pulse for starting the operation to each signal side drive circuit, the above object is achieved.

In this case, for example, when the scan lines are appropriately allocated and connected to the scan side drive circuits, the scan lines connected to the scan side drive circuits are headed in the scanning direction. From the scanning line to the output pin of the scanning side driving circuit in order according to the shift direction of the scanning side driving circuit, and when connecting the signal lines by appropriately allocating and connecting the signal lines to the respective signal side driving circuits. The signal line connected to the side driving circuit may be sequentially connected to the output pin of the signal side driving circuit in accordance with the shift direction of the signal side driving circuit from the leading signal line in the operation direction.

[0014]

According to the liquid crystal driving method of the present invention, when the number of scanning lines and signal lines of the liquid crystal display panel is equal to or less than the total number of output pins of the scanning side driving circuit and the signal side driving circuit, respectively,
The scanning lines are appropriately allocated according to the number of scanning lines and the number of output pins of each scanning side drive circuit, are connected to the output pins of each scanning side drive circuit, and the scanning direction connected to each scanning side drive circuit. A scanning line start pulse for starting scanning is input to each scanning side drive circuit at a timing corresponding to the scanning timing of the leading scanning line. Further, the signal lines are appropriately allocated according to the number of the signal lines and the number of output pins of the signal side drive circuits, and are connected to the output pins of the signal side drive circuits and connected to the signal side drive circuits. A segment line start pulse for starting the operation is input to each signal side drive circuit at a timing corresponding to the operation timing of the signal line at the head of the operation direction.

Therefore, the number of scanning lines and signal lines of the liquid crystal display panel is the same as the number of scanning lines and signal lines of the liquid crystal display panel without manufacturing a dedicated scanning side driving circuit or signal side driving circuit. The same scan side drive circuit and signal side drive circuit can be applied to the liquid crystal display panel with the number of output pins of the drive circuit or signal side drive circuit or less, and the signal side drive circuit or scan side drive circuit can be effectively used. Thus, the liquid crystal display device can be manufactured at low cost.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

1 to 5 are views showing an embodiment of the liquid crystal driving method of the present invention, and this embodiment is applied to a liquid crystal television device.

First, the structure of this embodiment will be described.

In FIG. 1, the liquid crystal television device 10 includes an antenna 11, a receiving circuit 12, a control circuit 13, an interface circuit 14, an A / D conversion circuit 15, a data conversion circuit 16, a mode selection switch 17, a segment driver (signal side). A driving circuit) 18, a common driver (scanning side driving circuit) 19, a liquid crystal display panel 20 and the like are provided.

The liquid crystal display panel 20 has a plurality of segment lines (signal lines) and a plurality of common lines (scan lines) formed in a matrix, and a display element made of liquid crystal at each intersection of the segment lines and the common lines. Are formed.

The liquid crystal display panel 20 can be of various sizes, and there are various numbers of segment lines and common lines. For example, the liquid crystal display panel 20 has a number of segment lines and common lines of 720 × 220, 540 × 220, 360 × 220, or 480 × 146. There are items such as 480 in this embodiment.
146 are used.

Each segment line of the liquid crystal display panel 20 is connected to an output pin of the segment driver 18, and a segment drive signal is supplied from the segment driver 18 to each segment line of the liquid crystal display panel 20.

Each common line of the liquid crystal display panel 20 is connected to an output pin of the common driver 19, and a common drive signal is supplied from the common driver 19 to each common line of the liquid crystal display panel 20.

The liquid crystal display panel 20, the segment driver 18 and the common driver 19 are constructed as shown in FIG.

That is, the segment driver 18 is
It is composed of three segment drivers 18A, 18B and 18C. In this embodiment, the segment driver 18 is manufactured for a liquid crystal display panel having 540 segment lines, that is, the total number of output pins is 54.
Zero ones are used. Therefore, each segment driver 18A, 18B, 18C
Equipped with 0 output pins, segment driver 18A,
It is a segment driver in which the total number of output pins of 18B and 18C is 540.

However, the liquid crystal display panel 20 of the present embodiment.
Has 48 segment lines, as described above.
0, segment drivers 18A, 18B, 1
The number is smaller than the total number of 8C output pins.

Therefore, in the present embodiment, the segment drivers 18A, 18B are provided with 160 segment lines each.
The output pins of the segment drivers 18A, 18B, and 18C are connected to the output pins of the 18C, and at this time, the output pins of the segment drivers 18A, 18B, and 18C from the left end output pin to the right in FIG. To each segment driver 18A, 18B, 1
The other output pin of 8C is in an unconnected state, that is, an open state.

The method of connecting the segment lines to the output pins of the segment drivers 18A, 18B and 18C is as follows.
Although the number of segment lines connected to 8B and 18C is evenly distributed, the number of segment lines is not limited to this. For example, the liquid crystal display panel 20 and the segment driver 18
From the relationship with A, 18B, and 18C, the wiring may be easily assigned. At this time, the segment line start pulses STa, STb, STc input to each segment driver 18A, 18B, 18C described later are output in accordance with the operation timing of the first segment line connected to the segment driver 18A, 18B, 18C. .

The common driver 19 is composed of two common drivers 19A and 19B. In this embodiment, the common driver 19 has two common lines.
The one manufactured for 20 liquid crystal display panels, that is, the one having a total of 220 output pins is used.

Therefore, each common driver 19A,
Reference numeral 19B is a segment driver that has 110 output pins each and the total number of output pins of the common drivers 19A and 19B is 220.

However, the liquid crystal display panel 20 of the present embodiment.
The number of common lines is 146 and the total number of output pins of the common drivers 19A and 19B is 220.
It is less than the number of books.

Therefore, in this embodiment, the common line is 7
Three of them are connected to each output pin of the common drivers 19A and 19B. At this time, the common drivers 19A and 19B are connected.
The output pin at the head of the operation direction of B, the output pin at the upper end in FIG. 2, is sequentially connected to the output pins of the common drivers 19A and 19B in the downward direction, and the common drivers 19A and 19B are connected.
The other output pins of are not connected, that is, open.

The common driver 1 for the common line
In the present embodiment, the number of common lines connected to the common drivers 19A and 19B is evenly distributed, but the number of common lines connected to the output pins of 9A and 19B is not limited to this. Wiring may be easily assigned based on the relationship between the panel 20 and the common drivers 19A and 19B. At this time, scan line start pulses DTa and DTb input to common drivers 19A and 19B, which will be described later, are applied to the common drivers 19A and 19B.
It is output at the scanning start timing of the leading common line connected to 19B.

Further, each segment driver 18A, 1
8B and 18C are the segment line start pulse ST from the interface circuit 14 shown in FIG. 1, respectively.
a, STb, STc and a horizontal control signal (not shown) such as an SNB signal (segment control signal) or a basic clock signal, display data is input from the data conversion circuit 16, and each segment driver 18 is input.
When segment line start pulses STa, STb, STc are input, A, 18B, 18C start sampling the display data based on the basic clock signal, and when the display data is sampled, the data latch signal is sent by the SNB signal. A segment drive signal having a size corresponding to the created and stored display data is output to each segment line.

The common drivers 19A and 19B are provided with scanning line start pulses DTa and DTb for determining the scanning start timing and common line selection width of the common drivers 19A and 19B from the interface circuit 14 shown in FIG. 1, respectively. A vertical control signal such as a CNB signal for sequentially shifting the scan line start pulses DTa and DTb in the common drivers 19A and 19B and a CFB signal which is a data inversion signal for AC driving the liquid crystal display panel 20 are input. When the scan line start pulses DTa and DTb are input to the common drivers 19A and 19B, the CNBs are input.
The scanning drive signal is output to each of the connected common lines while sequentially shifting based on the signal.

Referring again to FIG. 1, the antenna 11
Receives the television broadcast radio wave and outputs the received television broadcast radio wave to the receiving circuit 12.

The receiving circuit 12 is provided with a tuner and an intermediate frequency amplifying circuit, a video detecting circuit, a video amplifying circuit, an AFT detecting circuit, etc., and the receiving circuit 12 is a tuner, and a predetermined one of the television broadcast radio waves received by the antenna 11 is received. Broadcast system, in the present embodiment, NTSC system television broadcast radio waves are converted into intermediate frequency signals and output to the control circuit 13, and
After the intermediate frequency signal converted by the tuner is amplified by the intermediate frequency amplification circuit, the AFT detection circuit performs AFT detection, the image detection circuit performs image detection to extract an image signal, and the image detection circuit outputs it. R,
After the video signals of G and B are amplified by the video amplifier circuit, A
It outputs to the / D conversion circuit 15.

The control circuit 13 controls various synchronizing signals such as a horizontal synchronizing signal and a vertical synchronizing signal from the intermediate frequency signal input from the receiving circuit 12, the CNB signal, the CFB signal and the SNB.
Signal and basic clock signal and the like, and based on the mode signal Sm from the mode selection switch 17, the segment line start pulses STa, STb, S
Tc and scan line start pulses DTa and DTb are generated and output to the segment drivers 18A, 18B and 18C and common drivers 19A and 19B via the interface circuit 14.

The mode selection switch 17 is a mode of the liquid crystal display panel 20, that is, the number of segment lines and the number of common lines of the liquid crystal display panel 20, and the total number of output pins of the segment drivers 18A, 18B and 18C and the common driver 19A. , 19B is a switch for designating the liquid crystal drive mode set by the relationship with the total number of output pins of the segment driver 18B.
A, 18B, 18C and common driver 19A, 19B
Has 540 and 220 output pins. When the number of segment lines and common lines is 720 × 220, mode 1 is 540 × 220, mode 2 is in this embodiment. As described above, when 480 lines × 146 lines are set to the mode 3, the mode selection switch 17 selects the mode 3 in this embodiment. When the mode is selected, the mode selection switch 17 outputs a mode signal Sm indicating the selected mode to the control circuit 13.

Main parts of the control circuit 13 and the interface circuit 14 are constructed as shown in FIG.

That is, the control circuit 13 includes the cut pulse determination circuit 31, the reset signal generation circuits 32 and 33, the scanning line counters 34 and 35, the scanning line signal generation circuits 36 and 3.
7, signal line counters 38, 39, 40, display signal generation circuits 41, 42, 43, etc., and the interface circuit 14 includes a scanning line signal selection circuit 51, a display signal selection circuit 52, etc.

The control circuit 13 inputs the vertical synchronizing signal to the cut pulse determining circuit 31 and the reset signal generating circuit 33, and inputs the horizontal synchronizing signal to the scanning line counters 34 and 35 and the signal line counters 38, 39 and 40. . Also, the mode signal Sm output from the mode selection switch 17 is output.
Is input to the scanning line signal generation circuits 36 and 37 and the display signal generation circuits 41, 42 and 43, and the control circuit 1
3 is input to the scanning line signal selection circuit 51 and the display signal selection circuit 52 of the interface circuit 14.

As shown in FIGS. 5 and 6, the television broadcast radio wave has a vertical blanking period, and the cut pulse determination circuit 31 determines the vertical blanking period from the input vertical synchronizing signal. The head pulse of the vertical synchronizing signal is detected and the detection signal is output to the reset signal generating circuit 32.

When the detection signal is input from the cut pulse determination circuit 31, the reset signal generation circuit 32 outputs a reset signal to the scanning line counter 34 and the scanning line counter 35, and the scanning line counter 34 and the scanning line counter 35. After clearing zero to the horizontal sync signal, the scanning line counter 3
4 and the scanning line counter 35 to start counting operations of the scanning line counter 34 and the scanning line counter 35 as described later.

Scan line counter 34 and scan line counter 3
The reference numeral 5 sequentially counts up the input horizontal synchronizing signal, and when each counts up to a preset count value, outputs a count-up signal to the corresponding scanning line signal generating circuit 36 and scanning line signal generating circuit 37.
The target count values of the scanning line counter 34 and the scanning line counter 35 are set as the timing at which the common drivers 19A and 19B start operating.

When the count-up signals are input from the scanning line counter 34 and the scanning line counter 35, the scanning line signal generating circuit 36 and the scanning line signal generating circuit 37 are based on the input mode signal Sm. Scan line start pulse DTa corresponding to the mode indicated by Sm
And a scan line start pulse DTb are created and output to the scan line signal selection circuit 51 of the interface circuit 14. The scanning line start pulses DTa and DTb will be described later.

The reset signal generating circuit 33 outputs a reset signal to the signal line counters 38, 39 and 40 for each vertical synchronizing signal to clear the signal line counters 38, 39 and 40 to zero and then to the horizontal synchronizing signal. Is output to each of the signal line counters 38, 39, 40, and the counting operation of the signal line counters 38, 39, 40 is started as described later.

The signal line counters 38, 39 and 40 sequentially count up the input horizontal synchronizing signals, and when they count up to the preset count values respectively,
A display signal generation circuit 41 corresponding to the count-up signal,
It outputs to 42 and 43. This signal line counter 38, 3
The target count values of 9 and 40 are set as the timing for causing the segment drivers 18A, 18B and 18C to start the operation.

When the count-up signals are inputted from the scanning line counters 38, 39, 40, the display signal producing circuits 41, 42, 43 receive the mode signal S inputted at that time.
Based on m, segment line start pulses STa, STb, S corresponding to the mode indicated by the mode signal Sm.
Tc is created and output to the display signal selection circuit 52 of the interface circuit 14. The segment line start pulses STa, STb, STc will be described later.

The scanning line signal selection circuit 51 of the interface circuit 14 is composed of, for example, a multiplexer, and is input from the scanning line signal generation circuit 36 and the scanning line signal generation circuit 37 based on the mode signal Sm input at that time. The scanning line start pulse DTa and the scanning line start pulse DTb are selected and output to the common drivers 19A and 19B shown in FIGS.

The display signal selection circuit 52 of the interface circuit 14 is composed of, for example, a multiplexer, and the segment line start pulse input from the display signal generation circuits 41, 42, 43 based on the mode signal Sm input at that time. Select STa, STb, STc to select the segment driver 18A shown in FIGS. 1 and 2.
Output to 18B and 18C.

Returning to FIG. 1 again, the A / D conversion circuit 15
Is synchronized with the synchronization signal input from the control circuit 13,
The video signal input from the reception circuit 12 is converted into a predetermined digital video signal and output to the data conversion circuit 16.

The data conversion circuit 16 is the A / D conversion circuit 1
When the digital video signal input from 5 is taken in for one line, it is converted into a gradation signal corresponding to the video signal and the segment driver 18A, 1
Output to 8B and 18C.

Next, the operation of this embodiment will be described.

The liquid crystal television device 10 includes a liquid crystal display panel 2
It is possible to attach various sizes having different numbers of segment lines and common lines as 0. Regardless of the size of the liquid crystal display panel 20, the same segment driver 18 and common driver 19 are used. I can do it. However, if the number of segment lines is the segment drivers 18A, 18B, 18
It is necessary that the total number of output pins of C18 is less than or equal to, and the number of common lines is less than or equal to the total number of output pins of common drivers 19A and 19B.

Then, the number of segment lines of the liquid crystal display panel 20 and the segment drivers 18A, 18B,
When the total number of output pins of 18C is the same and the number of common lines is the same as the total number of output pins of common drivers 19A and 19B, all segment lines and common lines are segment drivers 18A, 18B and 18C.
And the output pins of the common drivers 19A and 19B may be sequentially connected. However, when the number of segment lines is less than the total number of output pins of the segment drivers 18A, 18B and 18C, or when the number of common lines is the common driver 19A, When the number of output pins of 19B is less than the total number of output pins, a plurality of segment drivers 18 are provided.
A, 18B, 18C and common drivers 19A, 19B
According to the number of output pins of, the segment line and the common line are appropriately distributed, and the segment driver 18A,
18B and 18C output pins and common driver 19A,
Connect to the output pin of 19B.

In this embodiment, each of the segment drivers 18A, 18B, and 18C has 180 output pins and a total of 540 output pins, and the common drivers 19A and 19B each have 11 output pins.
It has a total of 220 output pins, each of which is 0.
The liquid crystal display panel 20 has 480 segment lines and 146 common lines.

Therefore, in this embodiment, the segment driver 18 having 180 output pins each is provided.
160 (160 = 480/3) segment lines are connected to the output pins of A, 18B, and 18C, and the output pins of common drivers 19A and 19B, which have 110 output pins each, have 73 Book (73 = 14
6 ÷ 2) Connect each common line.

At this time, the segment driver 18A,
On the 18B and 18C sides, each segment line is sequentially connected from the head segment line (the left segment line in FIG. 2) by 160 lines from the head output pin (the left output pin in FIG. 2) of the segment driver 18A in the operating direction. Then, the remaining output pins of the segment driver 18A are set as unconnected open pins, and then similarly, the next 160 segment lines are sequentially connected to the output pins of the segment driver 18B from the output pin at the head in the operation direction. , The remaining output pins of the segment driver 18B are open pins. And the remaining 160 segment lines are 18
The output pins of the segment driver 18C having 0 output pins are sequentially connected from the output pin at the head of the operation direction, and the remaining output pins are open pins.

Then, each segment driver 18A,
18B and 18C have segment line start pulses STa, STb and S from the interface 14, respectively.
Tc is input, and each segment driver 18A, 18
B and 18C are the segment line start pulse S
When sampling of the display data input from the data conversion circuit 16 is started based on Ta, STb, and STc and the sampling of the display data is completed, a data latch signal is created based on the SNB signal input from the interface circuit 14. Then, a segment drive signal having a magnitude corresponding to the latched display data is output to each segment line.

On the side of the common drivers 19A and 19B, the common driver 19A having 73 output terminals, each having 73 output lines from the top common line (the upper common line in FIG. 2), is output at the top in the scanning direction. Common driver 19B having the output pins on the upper side in FIG. 2 connected in sequence, the remaining output pins of common driver 19A as unconnected open pins, and the next 73 common lines having 110 output pins Are sequentially connected from the first output pin in the scanning direction, and the remaining output pins of the common driver 19B are left unconnected pins.

Then, each common driver 19A, 19
The scan line start pulses DTa and DTb are input from the interface circuit 14 to B, and the common line drivers 19A and 19B receive the scan line start pulse DT.
When a and DTb are input, the sequential scan drive signal is output to each common line while sequentially shifting the sequential scan line start pulses DTa and DTb based on the CNB signal.

Then, in this way, the liquid crystal display panel 2
When 0 is attached, the driving method corresponding to the size of the liquid crystal display panel 20 is selected by the mode selection switch 17,
The mode selection switch 17 outputs a mode signal Sm corresponding to the selected drive mode to the control circuit 13.

Then, the liquid crystal television set 10 of the present embodiment.
Receives the television broadcast radio wave by the antenna 11 and takes it into the receiving circuit 12. The receiving circuit 12 converts the television broadcast radio wave of the NTSC system among the television broadcast radio waves received by the antenna 11 into an intermediate frequency signal and controls the control circuit. Output to 13,
Also, by extracting the image signal from the intermediate frequency signal, R,
The G and B video signals are amplified and then output to the A / D conversion circuit 15.

The A / D conversion circuit 15 converts the video signal input from the reception circuit 12 into a predetermined digital video signal in synchronization with the synchronization signal input from the control circuit 13.
The data is output to the data conversion circuit 16.

The data conversion circuit 16 is the A / D conversion circuit 1
When one line of the digital video signal input from 5 is fetched, it is converted into a gradation signal corresponding to the video signal and output as display data to the segment drivers 18A, 18B and 18C.

The control circuit 13 controls the horizontal and vertical display control signals corresponding to the drive mode indicated by the mode signal Sm, particularly the segment line start pulses STa, STb ,.
STc and scan line start pulses DTa, DTb are generated, and these segment line start pulses STa,
STb, STc and scan line start pulse DTa,
Of DTb, segment line start pulses STa, STb corresponding to the drive mode indicated by the mode signal Sm,
STc and scan line start pulses DTa and DTb are selected by the interface circuit 14, and the segment drivers 18A, 18B and 18C and the common driver 1 are selected.
Output to 9A and 19B.

Segment drivers 18A, 18B, 1
8C and the common drivers 19A and 19B drive the liquid crystal display panel 20 based on the segment line start pulses STa, STb and STc and the scan line start pulses DTa and DTb as described above, and the size of the liquid crystal display panel 20 is increased. It is possible to perform driving suitable for the size.

That is, as shown in FIGS. 3, 4, and 5, the control circuit 13 includes the cut pulse determining circuit 31.
Thus, the head pulse of the vertical synchronizing signal in the vertical blanking period is detected and the detection signal is output to the reset signal generating circuit 32.

When the detection signal is input from the cut pulse determination circuit 31, the reset signal generation circuit 32 outputs a reset signal to the scanning line counter 34 and the scanning line counter 35, and the scanning line counter 34 and the scanning line counter 35. After clearing zero to the horizontal sync signal, the scanning line counter 3
4 and the scanning line counter 35 to output the scanning line counter 3
4 and the scanning line counter 35 sequentially count up the horizontal synchronizing signal when the horizontal synchronizing signal is input, and when the horizontal synchronizing signal is counted up to a preset count value, the count-up signal corresponds to the scanning line signal generating circuit. 36 and the scanning line signal generation circuit 37.

When the count-up signals are input from the scanning line counter 34 and the scanning line counter 35, the scanning line signal generating circuit 36 and the scanning line signal generating circuit 37 change the mode signal Sm input from the mode selection switch 17 into the mode signal Sm. Based on this, the scan line start pulse DTa and the scan line start pulse DTb corresponding to the mode indicated by the mode signal Sm are created and output to the scan line signal selection circuit 51 of the interface circuit 14.

In this embodiment, the segment driver 18
A, 18B, 18C and common driver 19A, 19B
The total number of output pins is 540 × 220, the number of segment lines and common lines is 480 × 146, and the drive mode corresponding to the number of output pins and lines is selected by the mode selection switch 17. Then, the mode signal Sm indicating this drive mode is input to the control circuit 13.

As described above, the liquid crystal television device 10 receives the television broadcast wave of the NTSC system. In the NTSC system, the number of scanning lines in one field is 525 divided by 2. Although it is 262.5, the actual number of scanning lines is about 220 after subtracting about 40 which is the number of vertical blanking periods.

When displaying this NTSC system image,
If the number of common lines of the liquid crystal display panel 20 is 220, it is not necessary to thin out the liquid crystal display panel 20.
Since there are 146 common lines now,
It is necessary to perform thinning scanning for 74 scanning lines obtained by subtracting 146 from 220 lines.

Therefore, in the present embodiment, as described for the case of 480 segment lines in FIGS. 4 and 5, the scanning line start pulse DTa for three line widths,
By applying DTb and supplying a CNB signal that shifts the common line for two of them, 3
The common line of the lines is driven, and one of the lines is thinned out, and 220 scanning lines is 2/3 of that line.
Drive six.

The control circuit 13 outputs the scan line start pulses DTa and DTb thus generated to the scan line signal generating circuit 51 of the interface circuit 14, and the scan line signal generating circuit 51 responds to the mode signal Sm. , Scan line start pulses DTa and DTb are selected and output to the common driver 19A and the common driver 19B.

Therefore, the common driver 19A is
As described above, based on this scan line start pulse DTa, a scan drive signal is sequentially output to the common line connected to the common driver 19A, and when scanning is performed to the end of the common line connected to the common driver 19A, the common driver is detected. The scan line start pulse DTb is input to 19B, and the common driver 19B similarly outputs a scan drive signal to the common lines connected to the common driver 19B based on the scan line start pulse DTb.

Further, in the control circuit 13, the reset signal generating circuit 33 resets the scanning line counters 38, 39 and 40 and then starts the counting operation, and the scanning line counter 3
8, 39, 40 sequentially count up the horizontal synchronizing signals, and when they count up to the preset count values, respectively, output the count-up signals to the corresponding display signal generating circuits 41, 42, 43.

When the count-up signal is inputted from the scanning line signal producing circuit, the display signal producing circuits 41, 42 and 43 receive the segment line start pulse corresponding to the mode signal Sm inputted from the mode selection switch 17 at that time. STa, STb, STc are generated and output to the display signal selection circuit 52 of the interface circuit 14.

This segment line start pulse ST
a, STb, and STc are each 3 as shown in FIG.
The segment drivers 18A, 18B, and 18C are input to the segment drivers 18A, 18B, and 18C at the operation start timing of the first segment line connected to the segment drivers 18A, 18B, and 18C, that is, at the timing corresponding to the sampling start timing of the display signal. .

The display signal selection circuit 52 uses the mode signal Sm.
Based on the segment line start pulse STa, S
Select Tb, STc, and segment driver 18
Output to A, 18B and 18C.

Segment drivers 18A, 18B, 1
As shown in FIG. 5, 8C starts sampling the display data input from the data conversion circuit 16 when the segment line start pulses STa, STb, and STc are input, and displays when the display data sampling is completed. A segment drive signal having a magnitude corresponding to the data is output to each segment line.

Therefore, the common drivers 19A, 1
9B has 220 output pins, and the liquid crystal display panel 20
When there are 146 common lines, as shown in FIG.
At the time of the 26th horizontal synchronizing signal, the scan line start pulse DTa is output, and as shown in FIG. 5, the output of the scan line start pulse DTa to the 136th, that is, 110 scan lines is started. The scanning line start pulse DTb is output at the time of the 136th horizontal synchronizing signal obtained by adding the above 26.

Then, the scanning line start pulse D
As described above, Ta and DTb have a width of three scanning lines, and one of them is thinned out.
× 2 ÷ 3 = drives about 73 common lines.

As a result, it is possible to drive the liquid crystal display panel 20 having 146 common lines by the common drivers 19A and 19B having a total of 220 output pins.

Also, three segment drivers 18
When A, 18B, and 18C have a total of 540 output pins, and the liquid crystal display panel 20 has 480 segment lines, as shown in FIG.
The segment line start pulses STa, STb, STc are input at the operation start timing of the segment lines connected to 8A, 18B, 18C, the display data is sampled, and the segment drive signal corresponding to the sampled display data is displayed on the liquid crystal. It can be output to the segment line of the display panel 20.

As a result, the segment drivers 18A, 18B and 18C having a total of 540 output pins are used to display the liquid crystal display panel 20 of 480 segment lines.
Can be driven for display.

Although the liquid crystal display panel 20 has 146 common lines and 480 segment lines in the above embodiment, the liquid crystal display panel 20 has 220 common lines and 540 segment lines. When there are two segment lines, the total number of output pins of the common drivers 19A and 19B is equal to the number of common lines.
Since the total number of output pins of A, 18B, and 18C and the number of segment lines match, all common lines are connected to all output pins of common drivers 19A and 19B, and all segment lines are segment driver 18A. , 18B, 18C are connected to all output pins.

Further, the segment drivers 18A, 1
8B and 18C, as in the conventional case, the output end of the segment line start pulse of the segment driver 18A is the input end of the segment line start pulse of the segment driver 18B, and the output end of the sampling start signal of the segment driver 18B is the segment driver 18
After the segment line start pulse STa input to the segment driver 18A is sequentially shifted, the segment line start pulse STa is connected to the input terminals of the sampling start signal of C, respectively.
It is input to the segment driver 18B and further input to the segment driver 18C.

Also, common drivers 19A and 19B
Also, as in the conventional case, the common driver 19A, 19B
The output end of the scan line start pulse DTa of is connected to the input end of the scan line start pulse DTb of the common driver 19B, the scan line start pulse DTa input to the common driver 19A is sequentially shifted, and then input to the common driver 19B. To be done.

Then, in the control circuit 13 and the interface circuit 14, as shown in FIGS. 4 and 5, the scanning line start pulse D generated by the scanning line signal generating circuit 36.
Only Ta is output to the common driver 19A, and only the segment line start pulse STa created by the display signal creation circuit 41 is output to the segment driver 18A.

As a result, when the liquid crystal display panel 20 has 220 common lines and 540 segment lines, the liquid crystal display panel 20 can be driven by a driving method similar to the conventional one.

In the above description, the liquid crystal display panel 20 is used.
Has 220 common lines and 540 segment lines, the segment drivers 18A, 1
8B, 18C segment line start pulse ST
The input / output terminals of a, STb, and STc are sequentially connected by the segment drivers 18A, 18B, and 18C, and the scan line start pulse D of the common drivers 19A and 19B is connected.
Input / output terminals of Ta and DTb are connected to the common driver 19A,
19B connect with each other, but not limited to this, the segment line start pulse STa, STb, ST of each segment driver 18A, 18B, 18C
The input terminal of c and the input terminals of the scan line start pulses DTa and DTb of the common drivers 19A and 19B are respectively connected to the interface circuit 14, and the scan line signal selection circuit 51 and the display signal selection circuit 52 are connected to the segment drivers 18A, 18B and 18C. Alternatively, the segment line start pulses STa, STb, STc and the scan line start pulses DTa, DTb may be output at the respective operation timings of the common drivers 19A, 19B.

Therefore, the liquid crystal television device 1 of the present embodiment.
According to 0, the number of common lines and segment lines of the liquid crystal display panel 10 is the common driver 19A,
19B and segment drivers 18A, 18B, 18C
When the total number of output pins is less than or equal to, the common lines are appropriately allocated according to the number of common lines and the output pins of the common drivers 19A and 19B, and are connected to the output pins of the common drivers 19A and 19B. , Scan line start pulses DTa and DTb for starting scanning to the common drivers 19A and 19B are input at timings corresponding to the scan timing of the common line at the head in the scanning direction connected to the common drivers 19A and 19B, and segment lines are connected. , The segment drivers 18A, 18B, 18C are appropriately allocated according to the number of the segment lines and the output pins of the segment drivers 18A, 18B, 18C, and are connected to the output pins of the segment drivers 18A, 18B, 18C. The first cell in the direction of movement connected to 18C. Each segment driver 18A at a timing corresponding to the operation timing of the reinforcement line, 1
Segment line start pulses STa, STb, and STc for starting the operation are input to 8B and 18C.

As a result, the dedicated common drivers 19A and 19B and the segment drivers 18A, which correspond to the number of common lines and segment lines of the liquid crystal display panel 20,
Liquid crystal display panel 2 without manufacturing 18B and 18C
The number of common lines and segment lines of 0 are common drivers 19A, 19B and segment drivers 18A,
If the number of output pins of 18B and 18C is less than or equal to, the same common driver 19 can be used for any liquid crystal display panel 20.
A, 19B and segment drivers 18A, 18B, 1
8C can be applied.

As a result, the segment driver 18A,
A liquid crystal television device 1 as a liquid crystal display device by effectively utilizing 18B, 18C and common drivers 19A, 19B.
0 can be manufactured at low cost.

Although the invention made by the present inventor has been specifically described based on the preferred embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above embodiment, the case where the total number of output pins of the segment drivers 18A, 18B and 18C is 540 and the total number of output pins of the common drivers 19A and 19B is 220 has been described. The total number of output pins of the common driver is not limited to the above case. For example, even if the total number of output pins of the segment driver is 720 and the total number of output pins of the common driver is 220. Good.

In the above embodiment, the case where the number of segment drivers is 3 and the number of common drivers is 2 has been described. However, the numbers of segment drivers and common drivers are the same as those shown in the above embodiment. Needless to say, it is not limited to.

[0100]

According to the present invention, when the number of scanning lines or signal lines of the liquid crystal display panel is less than or equal to the total number of output pins of the scanning side driving circuit or the signal side driving circuit, the scanning line is set to the scanning line. According to the number of scan lines and the number of output pins of each scan side drive circuit, connect to the output pin of each scan side drive circuit, and the scan timing of the first scan line in the scan direction connected to each scan side drive circuit. A scan line start pulse for starting scanning is input to each scanning side drive circuit at a timing corresponding to. Further, the signal lines are appropriately allocated according to the number of the signal lines and the number of output pins of the signal side drive circuits, and are connected to the output pins of the signal side drive circuits and connected to the signal side drive circuits. A segment line start pulse for starting the operation is input to each signal side drive circuit at a timing corresponding to the operation timing of the signal line at the head of the operation direction.

Therefore, the number of scan lines and signal lines of the liquid crystal display panel can be adjusted to the number of scan lines and signal lines of the liquid crystal display panel without manufacturing a dedicated scan side drive circuit or signal side drive circuit. The same scanning side driving circuit and signal side driving circuit can be applied to a liquid crystal display panel having the number of output pins of the driving circuit or the signal side driving circuit or less.

As a result, the liquid crystal display device can be manufactured at low cost by effectively utilizing the signal side driving circuit and the scanning side driving circuit.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a liquid crystal television device to which an embodiment of a liquid crystal driving method of the present invention is applied.

FIG. 2 is a detailed circuit block diagram of a liquid crystal display panel, a segment driver and a common driver portion of FIG.

3 is a detailed circuit block diagram of a main part of a control circuit and an interface circuit of FIG.

FIG. 4 shows 480 video signals and 54 segment lines.
The timing chart of various control signals in the case of 0 lines.

5 is a timing diagram of control signals showing a continuation of FIG. 4;

FIG. 6 is a block diagram showing a liquid crystal display panel and a driving circuit thereof according to a conventional liquid crystal driving method.

[Explanation of symbols]

 10 liquid crystal television device 11 antenna 12 reception circuit 13 control circuit 14 interface circuit 15 A / D conversion circuit 16 data conversion circuit 17 mode selection switch 18 segment driver 18A, 18B, 18C segment driver 19 common driver 19A, 19B common driver 20 liquid crystal display Panel 31 Cutting pulse determination circuit 32, 33 Reset signal creation circuit 34, 35 Scan line counter 36, 37 Scan line signal creation circuit 38, 39, 40 Signal line counter 41, 42, 43 Display signal creation circuit 51 Scan line signal selection circuit 52 Display signal selection circuit

Claims (2)

[Claims] 1. Display elements are arranged in a matrix at intersections of a plurality of scanning lines connected to output pins of a plurality of scanning side drive circuits and a plurality of signal lines connected to output pins of a plurality of signal side drive circuits. A liquid crystal drive method for driving an arranged liquid crystal display panel by the plurality of scan side drive circuits and the plurality of signal side drive circuits, wherein the scan lines are the number of the scan lines and the scan side drive circuits. Each scan is appropriately allocated according to the number of output pins and connected to the output pin of each scanning side drive circuit, and each scan is performed at a timing corresponding to the scanning timing of the leading scanning line in the scanning direction connected to each scanning side drive circuit. A scan line start pulse for starting scanning is input to the side drive circuit, and the signal lines are appropriately divided according to the number of the signal lines and the number of output pins of each signal side drive circuit. Then, each signal side drive circuit is connected to the output pin of each signal side drive circuit, and each signal side drive circuit starts operation at the timing corresponding to the operation timing of the signal line at the head of the operation direction connected to each signal side drive circuit. A liquid crystal driving method characterized by inputting a segment line start pulse. 2. When the scan lines are appropriately allocated and connected to the respective scan side drive circuits, the scan lines connected to the respective scan side drive circuits are shifted from the head scan line in the scan direction to the shift direction of the scan side drive circuits. In order to connect the signal lines to the output pins of the scanning side drive circuit in order, and to connect the signal lines to the signal side drive circuits by appropriately allocating the signal lines to the signal side drive circuits 2. The liquid crystal driving method according to claim 1, wherein the signal lines are sequentially connected to the output pins of the signal side drive circuit in accordance with the shift direction of the signal side drive circuit.