JPH07254703A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress sucking up of a poly Si film below a W silicide film by, relating to crystallization of a WSi film of gate electrode material made of a W polycide electrode and production of thin mask SiO2 film an Si substrate at ion implantation, increasing thickness ratio of the WSi film against the W polycide film and making the poly Si film thinner as much as possible, so that the W polycide film is not oxidized. CONSTITUTION:Crystallization of a high melting point metal silicide film 4 of high melting point metal polycide gate electrode 5 on a semiconductar substrate 1 is performed by heat treatment in decompressed inert gas atmosphere, and an insulation film 6, to be used as a mask far ion implanting, is formed by CVD method. Further, reflowing of a reflow insulation film is done in decompressed inert gas atmosphere.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a crystallization treatment of a refractory metal silicide film of a gate electrode material using a refractory metal polycide structure and an insulation treatment of its surface.

With the recent trend toward higher integration and miniaturization of semiconductor devices, it is required to reduce the resistance and thickness of the gate electrode wiring and also to improve the reliability of the gate wiring.

[0003]

2. Description of the Related Art FIG. 7 is an explanatory view of a conventional example. In the figure, 40 is a Si substrate, 41 is a gate SiO ₂ film, 42 is a poly-Si film, 43
Is a WSi film, 43 'is a WSi film (crystallized), 44 is a W polycide gate electrode, 45 is a SiO ₂ film, 46 is an impurity ion, and 47 is a source / drain diffusion layer.

In order to reduce the resistance of the gate electrode material, in recent years, instead of the polycrystalline silicon (poly Si) gate electrode, the structure shown in FIG.
As shown in (a), a tungsten (W) polycide gate electrode 44 has been mainly used. Poly Si
If an attempt is made to obtain a resistance value equivalent to that of the poly-Si gate electrode by using the W polycide gate electrode 44 composed of the film 42 and the W silicide (WSi) film 43, the gate silicon dioxide (SiO ₂ )
The film 41 can be thinned and can be flattened.

However, as shown in FIG. 4C, after forming the W polycide gate electrode 44, the source / drain diffusion layer is formed.
Impurity ions 46 are ion-implanted into the silicon (Si) substrate 40 in the region where 47 is formed. However, direct ion-implantation has a problem such as damage to the Si substrate 40. As shown in FIG.
Si as a mask for ion implantation on the substrate 40
Impurity ions 46 are formed after the O ₂ film 45 is formed by a thermal oxidation method or the like.
However, the poly-Si film 42 under the WSi film 43 is sucked up and becomes thin.

For this reason, if the poly-Si film 42 of the W polycide gate electrode 44 is made too thin, the WSi film 43 will directly form the gate Si film.
It may come into contact with the O ₂ film 27. Also, the WSi film 43
Since the resistance does not decrease unless it is crystallized, as shown in FIG. 4B, the WSi film 43 is crystallized simultaneously with the formation process of the SiO ₂ film 45 as a mask for ion implantation, and the crystallized WSi film is formed. Had formed a 43 '.

[0007]

Therefore, as described above, the WSi film 43 ′ is in direct contact with the gate SiO ₂ film 41, so that W contamination (contamination), deterioration of the gate breakdown voltage, and adhesion of the gate electrode material are caused. It causes problems such as poor sex.

Therefore, it has been difficult to reduce the thickness of the gate electrode material and reduce its resistance. In view of the above points, the present invention increases the ratio of the thickness of the WSi film 43 in the W polycide gate electrode 44 and makes the polySi film 42 as thin as possible. Do not oxidize, WSi
It is provided for the purpose of suppressing the siphoning of the poly-Si film 42 under the film 43.

[0009]

1 and 2 are explanatory views of the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a poly-Si film or α-Si film, 4 is a refractory metal silicide film, 4'is a refractory metal silicide film (crystallization), and 5 is a refractory metal. A metal polycide gate electrode, 6 is an insulating film, 7 is an impurity ion, 8 is a source / drain diffusion layer, 9 is an interlayer insulating film, 10 is a source / drain electrode, and 11 is a reflow insulating film.

The above problems can be solved by annealing an inert gas such as nitrogen (N ₂ ) in a vacuum and forming an insulating film by a CVD method. That is, an object of the present invention is to provide a semiconductor device using a refractory metal polycide electrode as a gate electrode on a semiconductor substrate 1 having a gate insulating film 2 deposited thereon.
A step of forming a refractory metal polycide gate electrode 5 by sequentially laminating a Si film or an amorphous silicon (α-Si) film 3 and a refractory metal silicide film 4 and patterning the semiconductor substrate 1 under reduced pressure. A step of crystallizing the refractory metal silicide film 4 by heat treatment in an inert gas atmosphere, and a step of subsequently forming an insulating film 6 by a CVD method so as to cover the refractory metal polycide gate electrode 5; And a step of implanting impurity ions 7 through the insulating film 6 into the semiconductor substrate 1 using the refractory metal polycide gate electrode 5 as a mask to form a source / drain diffusion layer 8. In the semiconductor device using the reflowable insulating film as a flattening film on the interlayer insulating film, the reflow heating of the reflow insulating film 11 should be performed in an inert gas atmosphere under reduced pressure. It is achieved by.

[0011]

In the present invention, the refractory metal silicide film of the refractory metal polycide electrode is heat-treated in order to reduce the resistance and is crystallized. In the present invention, this heat treatment is performed by heating in an inert gas atmosphere under reduced pressure. The formation of the oxide film before the ion implantation is performed by the CVD method at a relatively low temperature, so that the oxidation of the metal silicide film and the accompanying siphoning of the poly-Si film can be suppressed.

Further, since the reflow treatment of the interlayer insulating film after the electrode formation is also carried out by heating in an inert gas atmosphere under reduced pressure, the refractory metal silicide film is oxidized and the poly-Si film is sucked up in the same manner as described above. The refractory metal silicide film according to the present invention can be heated at a relatively high temperature without worrying about oxidation of the refractory metal silicide film, and the semiconductor device can be planarized by complete reflow of the planarization film. .

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 3 to 6 are explanatory views of an embodiment of the present invention. In the figure, 12 is a Si substrate, 13 is a field SiO ₂ film,
14 is a gate SiO ₂ film, 15 is a poly Si film, 16 is a WSi film, 16 'is a WSi film (crystallized), 17 is a W polycide gate electrode, and 18 is
SiO ₂ film, 19 is impurity ion, 20 is source / drain diffusion layer, 21 is PSG film, 22 is poly-Si electrode, 23 is SiO ₂ film, 24 is BPSG film, 25 is Si substrate, 26 is field SiO ₂ film , 27
Is a gate SiO ₂ film, 28 is an α-Si film, 29 is SiO ₂ / Si ₃ N ₄ / Si
O ₂ film, 30 α-Si film, 31 WSi film, 31 ′ WSi film (crystallized), 32 W polycide gate electrode, 33 SiO ₂ film, 34
Is impurity ions, 35 is a source / drain diffusion layer, and 36 is P
SG film, 37 is a poly-Si electrode, 38 is a SiO ₂ film, and 39 is a BPSG film.

In the embodiment of the present invention, the high melting point metal silicide film is the WSi film which is most popular because of its good adhesion and film forming property, and the flattening film has good reflow characteristics. A BPSG film is used.

A first embodiment in which the present invention is applied to a D-RAM of a MOS type semiconductor device having a W polycide gate electrode will be described with reference to FIGS. First, as shown in FIG. 3 (a), a gate SiO ₂ film is formed on a device formation region defined by a field SiO ₂ film 13 on a Si substrate 12 by hydrochloric acid oxidation at 1,050 ° C.
The film 14 is formed to a thickness of 150 Å.

Then, a poly-Si film 15 is formed at a thickness of 200 Å at 650 ° C. by the CVD method. In this case, instead of the poly-Si film 15, the film formation temperature may be changed to 450 ° C. to form the α-Si film.

Then, the WSi film 16 is formed at a substrate temperature of 400.degree.
Laminate to a thickness of 00Å to form a W polycide film. Next, as shown in FIG. 3B, at a temperature of about 400 ° C., 0.1
While reducing the pressure to -1 Torr and flowing only nitrogen (N ₂ ) gas at a rate of 1 l / min, at 30 ° C at 800 ° C in a non-oxidizing gas atmosphere.
Thermal annealing is performed for a minute to promote crystallization of the WSi film 16. In this case, since oxygen does not exist, the WSi film 16 is not oxidized and the Si of the poly-Si film 15 is not eaten.

Next, the WSi film 16, the poly-Si film 15 and the gate SiO ₂ film 14 are patterned using the resist film (not shown) as a mask to form a W polycide gate electrode 17.
Then, as shown in FIG. 3C, the SiO ₂ film 18 for the II mask is coated by the CVD method at a substrate temperature of 400 ° C.

Then, as shown in FIG.
Boron (B) is implanted as impurity ions 19 by ion implantation into the source / drain formation region through the O ₂ film 18 to form the source / drain diffusion layer 20.

The vacuum annealing may be performed after patterning the gate. Further, the vacuum annealing and the growth of the oxide film by the CVD method may be performed in a continuous sequence. After that, as shown in FIG. 4 (e), a PSG film 21 is deposited on the Si substrate as a protective film to a thickness of 3,000 Å, and after opening a through hole, a poly-Si electrode 22 for source / drain is formed as a poly-Si electrode 22.
A Si film is formed to a thickness of 1,000 Å by the CVD method and patterned.

Then, as shown in FIG. 4 (f), an SiO ₂ film 23 is grown as an interlayer insulating film by the CVD method to a thickness of about 1,000 Å, and a BPSG film 24 is further coated to a thickness of 3,000 Å, followed by reflow. Therefore, heat treatment is performed to flatten the surface.

At this time, B for reflow as a flattening film
A heat treatment of about 700 ° C. is used for the purpose of preventing moisture absorption of the PSG film 24 and baking, and a heat treatment of about 900 ° C. is used for the purpose of reflow. It is preferable to use a heat treatment in an inert gas such as N ₂ .

Finally, although not shown, the sputtering method is used.
An Al film is vapor-deposited and patterned using a resist as a mask to complete a DRAM chip of a MOS semiconductor device. The present invention relates to a stack gate (double gate) type EPRO of a MOS type semiconductor device in which a floating gate electrode and a control gate electrode are stacked with an insulating film interposed therebetween.
A second embodiment applied to M will be described with reference to FIGS.

First, as shown in FIG. 5A, the Si substrate 25
In the element formation region defined by the upper field SiO ₂ film 26,
A gate SiO ₂ film 27 is formed to a thickness of 150 Å by hydrochloric acid oxidation at 050 ° C., and then an α-Si film 28 is formed to a thickness of 1,000 Å at 500 ° C. by a CVD method. In this case, the poly-Si film may be formed by changing the film forming temperature to 600 ° C. instead of the α-Si film 28.

Then, a SiO ₂ film was formed at 1,050 ° C. by hydrochloric acid oxidation.
The thickness of 100 Å and the Si ₃ N ₄ film 10 on it by CVD method.
The thickness of 0 Å and the SiO ₂ film 10
A three-layer insulating film composed of the SiO ₂ / Si ₃ N ₄ / SiO ₂ film 29 is formed with a thickness of 0 Å.

Again, the α-Si film 30 is coated at a thickness of 1,000Å at 500 ° C. by the CVD method to a thickness of 500Å, and then WSi is applied.
The film 31 is laminated at a substrate temperature of 400 ° C. to a thickness of 1,000 Å. Then, using the resist film (not shown) as a mask, the laminated film is patterned to form a floating gate electrode composed of the α-Si film 28 and a control electrode composed of the W polycide gate electrode 32 as SiO ₂ / Si ₃ N ₄ / SiO _2. Formed on the stack gate through a three-layer insulating film made of the film 29.

Next, as shown in FIG. 5 (b), the pressure is reduced to 0.1 to 1 Torr at a temperature of about 400 ° C., and only 1 N / g of N ₂ gas is added.
800 min in a non-oxidizing gas atmosphere while flowing at a rate of min.
Thermal annealing is performed at 30 ° C. for 30 minutes to promote crystallization of the WSi film 31. In this case, since oxygen does not exist, the WSi film 31 is not oxidized and Si of the α-Si film 30 is not eaten.

Then, as shown in FIG. 5C, CVD is performed.
Method is used to cover the SiO ₂ film 33 as a mask for ion implantation at a substrate temperature of 400 ° C. Then, as shown in FIG. 5D, boron (B) is implanted as impurity ions 34 by ion implantation into the source / drain formation region through the SiO ₂ film 33 to form the source / drain diffusion layer 20. .

Then, as shown in FIG. 6 (e), the Si substrate
A PSG film 36 is deposited on the 25 as a protective film to a thickness of 3,000 Å. After opening a through hole, a polysilicon for source / drain is formed.
A poly-Si film is formed as the Si electrode 37 to a thickness of 1,000 Å by the CVD method and patterned.

Subsequently, as shown in FIG. 6F, an SiO ₂ film 38 is grown as an interlayer insulating film by the CVD method to a thickness of about 1,000 Å, and a BPSG film 39 is further used as a flattening film for the interlayer insulating film.
To a thickness of 3,000 Å and heat treated for reflow to flatten the surface.

At this time, for the purpose of preventing moisture absorption of the BPSG film 39, heat treatment at around 700 ° C., and reflow,
Heat treatment at around 00 ℃ is used, but W
In order to prevent the oxidation of the Si film 31, heat treatment in an inert gas such as N ₂ under reduced pressure may be used.

Finally, although not shown, the sputtering method is used.
An Al film is vapor-deposited and patterned using a resist as a mask to complete an EPROM chip of a MOS type semiconductor device. In addition, the present invention can be effectively used for a stack gate type semiconductor device such as an EEPROM or a flash memory.

In the above embodiment, W is selected as the refractory metal, but in addition to this, cobalt (Co), titanium (Ti), tantalum (T
It is also possible to use other refractory metals such as a).

[0034]

As described above, according to the present invention,
In order to crystallize the WSi film after coating the WSi film with the SiO ₂ film, the WSi film of the W polycide gate electrode is not oxidized, and the polySi film under the WSi film or the α-Si film is removed. Si sucks up.

Therefore, the poly-Si of the W polycide gate electrode is
The thickness of the film or the α-Si film can be made as thin as possible. To that extent, the WSi film can be made thicker to reduce the resistance of the gate electrode, or the film thickness of the WSi film can be left as it is, and the gate electrode itself. Can be thinned.

Also, a reflow BPSG film for flattening the interlayer insulating film, etc. is formed by WSi in the reflow atmosphere of the present invention.
The film can be heated at a relatively high temperature without worrying about the oxidation of the film, the semiconductor device can be flattened more, and it greatly contributes to the performance improvement and the high integration of the semiconductor device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention (No. 1)

FIG. 2 is an explanatory diagram of the principle of the present invention (No. 2)

3A to 3D are schematic cross-sectional views in order of the processes of the first embodiment of the present invention (No. 1)

4A to 4C are schematic cross-sectional views in order of the processes of the first embodiment of the present invention (No. 2)

5A to 5C are schematic cross-sectional views in order of the steps of the second embodiment of the present invention (No. 1)

FIG. 6 is a schematic cross-sectional view in order of the steps of the second embodiment of the present invention (No. 2)

FIG. 7 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1 semiconductor substrate 2 gate insulating film 3 poly Si film or α-Si film 4 refractory metal silicide film 4 ′ refractory metal silicide film (crystallization) 5 refractory metal polycide gate electrode 6 insulating film 7 impurity ion 8 source Drain diffusion layer 9 Interlayer insulation film 10 Source / drain electrode 11 Reflow insulation film 12 Si substrate 13 Field SiO ₂ film 14 Gate SiO ₂ film 15 Poly Si film 16 WSi film 16 'WSi film (crystallization) 17 W Polycide gate electrode 18 SiO ₂ film 19 Impurity ion 20 Source / drain diffusion layer 21 PSG film 22 Poly Si electrode 23 SiO ₂ film 24 BPSG film 25 Si substrate 26 Field SiO ₂ film 27 Gate SiO ₂ film 28 α-Si film 29 SiO ₂ / Si ₃ N ₄ / SiO ₂ film 30 α-Si film 31 WSi film 31 ′ WSi film (crystallization) 32 W polycide gate electrode 33 SiO ₂ film 34 impurity ion 35 source / drain diffusion layer 36 PSG film 37 poly Si electrode 38 SiO ₂ film 39 BPSG film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 29/43 H01L 29/62 G

Claims (2)

[Claims] 1. A semiconductor device using a refractory metal polycide electrode as a gate electrode, comprising: a polycrystalline silicon (poly Si) film or an amorphous silicon (α-Si) film on a gate insulating film (2) of a semiconductor substrate (1). )
The film (3) and the refractory metal silicide film (4) are sequentially laminated,
Patterned refractory metal polycide gate electrode (5)
And a step of crystallizing the refractory metal silicide film (4) by heat-treating the semiconductor substrate (1) in an inert gas atmosphere under reduced pressure, and subsequently, refractory metal poly The insulating film (6) is formed in the semiconductor substrate (1) using the step of forming the insulating film (6) by a CVD method so as to cover the side gate electrode (5) and the refractory metal polyside gate electrode (5) as a mask. 6) through the impurity ions
(7) is injected to form a source / drain diffusion layer (8). 2. The semiconductor device using a reflowable insulating film as a flattening film on an interlayer insulating film, wherein the reflow heating of the reflow insulating film (11) is performed in an inert gas atmosphere under reduced pressure. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is manufactured.