JPH07254602A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To resolve a problem, such as a wiring short circuit by thermally treating and removing a by-product generated at a dry type etching stage at a temperature higher than the boiling point of the by-product. CONSTITUTION: A gate oxide film 31, a polysilicon layer 32, a WSi2 layer 33, a first HTO layer 34 and a photoresist film (not shown) are laminated successively on a semiconductor substrate 30, and patterned, the first HTO layer is etched by a dry type, while using the resist film as an etching mask and a resist pattern is removed. The WSi2 layer 33 and the polysilicon layer 32 are successively etched by the dry type while using a first HTO pattern 34a as the etching mask, and a gate having a polycide structure consisting of a polysilicon layer pattern 32a and a WSi2 layer pattern 33a is formed as shown in Fig. D. When heat treatment is conducted at a temperature higher than the boiling point of a by-product formed at the time of etching in a non-oxidizing atmosphere, a leakage current between the gate and pad polysilicon formed in a succeeding process can be minimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a polycide (Policide) dry-etching formed by laminating refractory metal silicide on polysilicon. The present invention relates to a method for removing by-products generated at the time of cutting.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor devices increases,
The importance of low resistance wiring is increasing, and recently, the polycide structure, which is a structure in which refractory metal silicide is formed on polysilicon as a wiring structure that replaces polysilicon, is used as a low resistance wiring material such as bit lines and gates. Widely used in. In a semiconductor manufacturing process, such patterning of polycide structure is usually performed by a dry etching method such as plasma etching or RIE (Reactive Ion Etching) method.

[0003]

However, when a large number of etching byproducts are generated in the process of performing the dry etching process, and the subsequent process is performed without removing the etching byproducts, the wiring of the subsequent wiring is not formed. A number of problems occur, such as the occurrence of shorts. Hereinafter, in order to explain a problem caused by a by-product generated in a process of dry-etching a polycide structure, a gate forming process in which the polycide structure is widely adopted will be described.

1A to 1E are sectional views showing a conventional method of forming a gate having a WSi ₂ / polysilicon structure. As shown in FIG. 1A, a gate oxide film 11, a polysilicon layer 12, a WSi ₂ layer 13 and an HTO (High Tempe) are formed on a semiconductor substrate 10.
(rature oxide) layer 14 is sequentially formed.

Next, as shown in FIG. 1B, the HTO layer 14
A photoresist is applied on the top and patterned to form a photoresist pattern 15. Then, as shown in FIG. 1C, the photoresist pattern 15 is used as an etching mask.
After etching the HTO layer 14 until the WSi ₂ layer 13 is exposed, the photoresist pattern 15 is stripped and removed to form an HTO pattern 14a.

Obtained at the dry etching stage.
As shown in FIG. 3, the WSi ₂ layer 13 and the polysilicon layer 12 are dry-etched using the HTO pattern 14a as an etching mask to obtain a gate having a polycide structure including the WSi ₂ layer pattern 13a and the polysilicon layer pattern 12a. Next, as shown in FIG. 1E, a conventional low pressure chemical vapor deposition (LPCV) process is performed on the resultant product obtained by the dry etching process.
After HTO is vapor-deposited by the method D), the entire surface is anisotropically etched to form the HTO spacer 17.

According to the conventional gate forming method as described above, in the dry etching process of the WSi ₂ layer 13 and the polysilicon layer 12, as shown in FIG. 1D, the WSi ₂ layer pattern 13a and the polysilicon layer pattern are formed. Etching by-product 16 on the side wall of the gate of polycide structure composed of 12a
Are adsorbed. 2A to 2C are views for explaining a problem caused by a by-product generated in an etching process when forming a gate by the conventional method.

FIG. 2A is an SEM photograph of the HTO spacer shown in FIG. 1E, which is observed in a top view. It can be seen that there is a hump phenomenon in which the spacer profile is full. The inventor
In order to clarify the cause of such hump phenomenon, Suprem
Using the e 4 (Ver5.1 System) program, the profile of the HTO spacer when a by-product was present on the sidewall of the WSi ₂ layer was simulated.

FIG. 2B is a diagram showing the simulation result. As shown in FIG. 2B, it was confirmed that the presence of the by-product 22 on the sidewall of the WSi ₂ layer 21 causes a hump phenomenon in which the profile of the HTO spacer 23 becomes full. FIG. 2C is a diagram illustrating a problem in a subsequent process that may occur due to the hump phenomenon. When the HTO spacer 23 is formed in a state where the by-product formed in the dry etching process of the gate is adsorbed to the side wall of the gate, the hump phenomenon that the profile of the spacer 23 pops out as described above occurs, and the subsequent process When a cleaning process is performed before the pad polysilicon 24 forming process, the by-product is etched and a slit 25 is formed at a portion where the by-product is adsorbed. When the pad polysilicon 24 is formed in this state, a short circuit occurs between the gate and the pad polysilicon 24.

As described above, unless the by-products generated during the dry etching process of polycide are removed, the reliability of the subsequent process is lowered and the yield of semiconductor devices is lowered. The problem of removing the by-product generated in such a dry etching process is not limited to the etching of the polycide structure, but also at the time of etching the polysilicon layer or on the lower conductive layer made of Al or an alloy layer containing Al. By-products are also generated when over-etching the insulating layer. It is also necessary to efficiently remove these byproducts.

An object of the present invention is to provide a method of manufacturing a semiconductor device for effectively removing a by-product generated during dry etching in any structure of the semiconductor device.
Another object of the present invention is to provide a method for effectively removing by-products generated during the dry etching of polycide. Yet another object of the present invention is to provide a method for effectively removing etching by-products generated in a dry etching process of polycide having a WSi ₂ layer / polysilicon structure.

Still another object of the present invention is to effectively remove the etching by-product generated in the process of dry-etching the polycide having the WSi ₂ layer / polysilicon structure to form an HTO spacer having a stable structure. Another object is to provide a method for forming a gate.

[0013]

In order to solve the above-mentioned problems, the present invention comprises a dry etching step of dry-etching a first substance layer composed of an arbitrary first substance, and a dry-etching step. A heat treatment step of heat-treating the resultant product at a temperature higher than the boiling point of the by-product to remove the generated by-product. Here, the heat treatment stage is a rapid thermal processing method or a high vacuum method.
(High Vacuum) It is performed by the annealing method.

In order to achieve another object of the present invention, the present invention provides a step of forming a polysilicon layer on an arbitrary lower structure on a semiconductor substrate, and a refractory metal silicide layer on the polysilicon layer. And a dry etching step of dry-etching the polysilicon layer and the refractory metal silicide layer to form a polysilicon layer pattern and a refractory metal silicide layer pattern, and the dry etching step. A heat treatment step of heat-treating the resultant obtained in the dry etching step to remove at least one by-product.

According to one embodiment of the method of manufacturing a semiconductor device of the present invention, the heat treatment step is performed at a temperature higher than a boiling point of the by-product generated in the dry etching step. According to another specific example of the method of manufacturing a semiconductor device according to the present invention, the heat treatment step is performed in a non-oxidizing atmosphere, that is, in an oxygen-free atmosphere, by a rapid thermal annealing method, or by a high vacuum annealing method.

According to still another specific example of the method for manufacturing a semiconductor device of the present invention, the refractory metal silicide layer is formed of a WSi _x layer, a TiSi _x layer, a MoSi _x layer, a TaSi _x layer, or a CoSi _x layer. It is characterized in that it is any one layer selected from the group consisting of. In the etching process for patterning polycide, a refractory metal silicide etching process and a polysilicon etching process are sequentially performed. The refractory metal silicide etching process is generally performed with fluorine (F) and chlorine. Dry etching is performed using a gas containing (Cl), for example, a gas containing SF ₆ and Cl _2, and the etching step of the polysilicon is other than the gas containing fluorine (F) and chlorine (Cl). Also dry etching using various types of plasma. The type of etching by-product that can be formed at this time can be predicted according to the type of silicide, the etching method, and the type of gas used for etching, and the characteristics such as the melting point and boiling point of such by-products are known materials. You can easily find out from. Not limited to the dry etching of polycide, when dry etching any material layer, if the type of gas used for etching, the etching method, the type of material layer to be etched, etc. are taken into consideration The types of by-products that can be formed during the etching process can be predicted and their properties can be investigated.

The heat treatment temperature is determined by the kind of by-product expected to be generated in the dry etching process and the boiling point of the by-product.
Here, the concept of a temperature higher than the boiling point of the by-product does not simply mean a temperature above the boiling point of the by-product having the highest boiling point among the by-products. This temperature should be determined considering the characteristics of the individual process. For example, by-products containing the expected substances A, B, C, D and E with boiling point order A
When>B>C>D> E, the by-product with the highest boiling point is actually A, but the possibility that A will be formed is extremely low, or heat treatment at a temperature above the boiling point of A can be performed. If it is difficult or if it is experimentally proved that the problem of by-products can be solved in the subsequent step even if the heat treatment is performed at a temperature lower than the boiling point of A, the boiling point of B or C can be changed. The heat treatment temperature can be set as a reference. Therefore, it is desirable to set the temperature higher than the boiling point of the majority of the solid by-products that are expected to be generated as the heat treatment temperature. Since this concept of "majority" cannot be expressed in a uniform percentage, the above-mentioned numerous factors should be properly considered in determining the heat treatment temperature.

In order to achieve another object of the present invention, the present invention comprises forming a polysilicon layer on an arbitrary substructure on a semiconductor substrate, and forming the polysilicon layer on the polysilicon layer.
Stacking a WSi ₂ layer, forming an HTO layer on the WSi ₂ layer, and photoetching the HTO layer to form an HTO layer.
Forming a pattern; a dry etching step of dry-etching the WSi ₂ layer and the polysilicon layer using the HTO pattern as an etching mask to form a WSi ₂ layer pattern and a polysilicon layer pattern; A heat treatment step of heat-treating a resultant obtained in the dry etching step at a temperature higher than a boiling point of the by-product generated in the dry etching step to remove at least one by-product generated in the etching step. A method for manufacturing a device is provided.

According to a specific example of a method for manufacturing a semiconductor device according to the present invention, the dry etching step includes a food containing any one selected from the group consisting of SF ₆ , Cl ₂ and a mixture thereof. comprising the steps of using the time gas etching the WSi ₂ layer, that using Cl _2, HB _r, gas the He-O ₂ is contained and a step of etching the polysilicon layer Characterize.

According to another embodiment of the method of manufacturing a semiconductor device according to the present invention, the heat treatment step is performed in a non-oxidizing atmosphere by a rapid heat treatment method or a high vacuum annealing method. . More specifically, the rapid thermal treatment method is performed in a temperature range of 500 ° C. to 800 ° C.
₂ , heat treatment is performed in an inert gas atmosphere selected from the group consisting of _Ar and a mixture thereof for 10 seconds to 30 seconds, and the high vacuum annealing method is performed at 500
The heat treatment is performed for 1 minute to 5 minutes in an inert gas atmosphere selected from the group consisting of N ₂ , _Ar and a mixture thereof within a temperature range of ℃ to 700 ℃.

According to another aspect of the present invention, there is provided a step of sequentially forming a gate oxide film, a polysilicon layer, a WSi ₂ layer and a first HTO layer on a semiconductor substrate, and the first HTO. Photolithography the layer to form a first HTO pattern, and using the first HTO pattern as an etching mask until the gate oxide layer is exposed.
Dry etching the WSi ₂ layer and the polysilicon layer
A dry etching step of forming a _two- layer pattern and a polysilicon layer pattern, and the dry etching step at a temperature higher than a boiling point of the by-product generated in the dry etching step to remove a by-product generated in the dry etching step. And a second HTO layer is formed on the entire surface of the resultant obtained by the heat treatment step.
And a step of forming an HTO spacer on a side surface of the first HTO pattern, the WSi ₂ layer pattern and the polysilicon layer pattern by anisotropically etching the HTO layer.

[0022]

It is possible to effectively remove by-products generated in the process of dry-etching any structure of a semiconductor device, especially polycide, so that the reliability of the subsequent process is improved and the yield of the semiconductor device is improved. It is possible to effectively remove the by-products generated during the dry etching of polycide, which has a WSi ₂ layer / polysilicon structure, and has a good profile of H.
A gate with TO spacers can be obtained.

[0023]

The present invention will be described in detail below with reference to the accompanying drawings. The concept of the present invention will be described more clearly by taking as an example a method of removing an etching by-product generated when dry etching a gate having a WSi ₂ / polysilicon structure. 3A to 3E are manufacturing process diagrams showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.

As shown in FIG. 3A, after the gate oxide film 31 was formed on the semiconductor substrate 30, a polysilicon layer 32 was formed on the gate oxide film 31 to a thickness of 1000 Å. Then, a WSi ₂ layer 33 is formed on the polysilicon layer 32 by 1000
After being formed to a thickness of Å, the first HTO layer 34 was formed to a thickness of 1500 Å on the WSi ₂ layer 33 by a normal low pressure chemical vapor deposition method.

Next, as shown in FIG. 3B, a photoresist film is deposited on the first HTO layer 34 to form a photoresist film (not shown), and the photoresist film is patterned to form a photoresist pattern 35. Formed. Then, as shown in FIG. 3C, a photoresist pattern 35 is formed.
The first HTO layer 34 was dry-etched by using the above as an etching mask to form the first HTO pattern 34a, and then the photoresist pattern 35 was removed.

Subsequently, as shown in FIG. 3D, the first HTO
Using the pattern 34a as an etching mask, the WSi ₂ layer 33 and the polysilicon layer 32 were sequentially dry-etched to form a gate having a polycide structure composed of the polysilicon layer pattern 32a and the WSi ₂ layer pattern 33a. At this time, WSi ₂
Layer 33 was etched using SF _6, Cl ₂ and any one of the mixtures selected from the group consisting of is-containing gas, the polysilicon layer 32 is _{Cl 2, HB r, He-} O 2 and Etching was performed using a gas containing any one selected from the group consisting of the mixture.

Next, in order to remove the by-products generated in the dry etching process of the WSi ₂ layer 33 and the polysilicon layer 32, the results obtained in the dry etching process at a temperature higher than the boiling point of the expected by-products. The article was heat treated. Table 1 shows the by-products that can be formed when the WSi ₂ layer 33 and the polysilicon layer 32 are etched to form a WSi ₂ / polysilicon structure gate by the method described above.

[0028]

[Table 1] As shown in Table 1, among the expected byproducts, the product having the highest boiling point is WH ₂ O ₄ , but other than that, WCl _x , W
Most by-products formed of solids such as Br _x , WOBr _x , and WOCl _{4 have} a boiling point of 350 ° C. or lower. Therefore, it is appropriate to perform the heat treatment at a temperature of 350 ° C. or higher.

In this embodiment, the heat treatment is performed in a non-oxidizing atmosphere, that is, oxygen is not contained (Oxyzen fre).
e) In atmosphere, rapid thermal processing method or high vacuum annealing method was used. Specifically, in the case of the rapid thermal treatment method, N in the temperature range of 500 ° C. to 800 ° C.
₂ , 500 ° C. when heat-treated in an inert gas atmosphere selected from the group consisting of Ar and a mixture thereof for 10 seconds to 30 seconds and using a high vacuum (≈10 ⁻⁸ Torr) annealing method. N _{2 in} the temperature range of up to 700 ° C.,
The heat treatment was performed for 1 to 5 minutes in an inert gas atmosphere selected from the group consisting of Ar and a mixture thereof.

After performing the heat treatment for removing the etching by-products, as shown in FIG. 3E, the resultant product obtained by the heat treatment using SiH ₄ and N ₂ O gas by the low pressure chemical vapor deposition method. A second HTO layer (not shown) is formed on the entire surface of the first and the second HTO layer is anisotropically etched to form a first HT.
The HTO spacer 36 is formed on the side surface of the O pattern 34a, the polysilicon layer pattern 32a, and the WSi ₂ layer pattern 33a.
Was formed.

FIG. 4 is an SEM photograph of the top view of the HTO spacer obtained in this example. By completely removing the by-product generated in the dry etching process by heat treatment, a good HTO spacer profile showing no hump phenomenon was obtained. FIG. 5 is a graph comparing leakage current (Leakage Current) between the gate and the pad polysilicon in the case of performing the heat treatment as in the present invention and in the case of not performing the heat treatment as in the prior art in the gate forming process. is there. In FIG. 5, the horizontal axis represents leakage current and the vertical axis represents cumulative distribution. According to the method of the present invention, when the heat treatment is performed using the rapid thermal processing method (shown as □ in FIG. 5) or the high vacuum annealing method (shown as Δ in FIG. 5), the conventional method (see FIG. 5) is used. It can be seen that the leakage current is much smaller than that of (○).

Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the embodiments and various modifications can be made within the scope of the present invention.

[0033]

As described above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to effectively remove any structure of the semiconductor device, particularly by-products generated during the dry etching process of polycide. The reliability of the subsequent process can be improved and the yield of the semiconductor device to be manufactured can be increased, and the gate forming process having the WSi ₂ / polysilicon structure can be performed.
By completely removing the by-products generated during the etching process to form the HTO spacer having a good profile, the leakage current between the gate and the pad polysilicon formed in the subsequent process can be minimized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of forming a gate having a conventional WSi ₂ / polysilicon structure.

FIG. 2 is an explanatory view showing a problem caused by a by-product generated in an etching process when a gate is formed by a conventional method.

FIG. 3 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a top view SEM photograph of HTO spacers obtained in an example according to the present invention.

FIG. 5 is a characteristic diagram comparing the leakage current between the gate and the pad polysilicon in the case of performing the heat treatment as in the present invention and in the case of not performing the heat treatment as in the prior art in the gate forming process.

[Explanation of symbols]

10 semiconductor substrate 11 gate oxide film 12 polysilicon layer 12a polysilicon layer pattern 13 WSi ₂ layer 13a WSi ₂ layer pattern 14 HTO layer 14a HTO pattern 15 photoresist pattern 16 etching byproduct 17 HTO spacer 22 byproduct 23 HTO spacer 24 pad poly Silicon 25 Slit 30 Semiconductor substrate 31 Gate oxide film 32 Polysilicon layer 32a Polysilicon layer pattern 33 WSi ₂ layer (refractory metal silicide layer) 33a WSi ₂ layer pattern (refractory metal silicide layer pattern) 34 First HTO layer (HTO layer) ) 34a First HTO pattern (HTO pattern) 35 Photoresist pattern 36 HTO spacer

[Procedure amendment]

[Submission date] March 29, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

FIG. 2 is an explanatory view showing the problems caused by by-products generated in the etching process when forming a gate in a conventional manner Ri, A is HTO scan obtained with the conventional method shown in FIG. 1
Top view SEM photograph of Pacer, B is by-product
Sectional view showing hump phenomenon caused by objects
Show problems in subsequent processes that can be caused by elephants
Ru sectional view der.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kim Yongfu, Republic of Korea, Gyeonggi-do, Suwon City, Suwon-si, Kumun-dong 462 No. 462, Sanhe Apartment, No. 801 (72) Inventor, Wu Yuan, Republic of Korea, Gyeonggi-do, Yongin-gun No. 24, Nori Rui Satoyama

Claims (20)

[Claims] 1. A step of forming a polysilicon layer on an arbitrary lower structure on a semiconductor substrate, a step of forming a refractory metal silicide layer on the polysilicon layer, the polysilicon layer and the high melting point. A dry etching step of dry etching the metal silicide layer to form a polysilicon layer pattern and a refractory metal silicide layer pattern; and heat-treating the resultant material to remove at least one by-product generated in the dry etching step. A method of manufacturing a semiconductor device, comprising: 2. The method of claim 1, wherein the heat treatment step is performed at a temperature higher than a boiling point of the by-product generated in the dry etching step. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is a rapid heat treatment. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is high vacuum annealing. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed in a non-oxidizing atmosphere. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the non-oxidizing atmosphere is made of at least one inert gas. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the inert gas is any one selected from the group consisting of nitrogen, argon and a mixture thereof. 8. The refractory metal silicide layer is WSi _x
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method comprises a layer, a TiSi _x layer, a MoSi _x layer, a TaSi _x layer, and a CoSi _x layer. 9. A step of forming a polysilicon layer on an arbitrary lower structure on a semiconductor substrate, a step of stacking a WSi ₂ layer on the polysilicon layer, and a step of forming an HTO layer on the WSi ₂ layer. Forming the HTO pattern by photo-etching the HTO layer, and dry-etching the WSi ₂ layer and the polysilicon layer using the HTO pattern as an etching mask to form the WSi ₂ layer pattern and the poly. A dry etching step of forming a silicon layer pattern, and a dry etching step at a temperature higher than a boiling point of the by-product generated in the dry etching step to remove a by-product generated in the dry etching step. And a heat treatment step of heat-treating the resultant product. 10. The dry etching step uses the etching gas containing any one selected from the group consisting of SF ₆ , Cl ₂ and a mixture thereof.
Comprising the steps of etching the _second layer, Cl _2, HB _r, etching the the He-O ₂ and the polysilicon layer using any one is contained etching gas selected from the group consisting of a mixture thereof 10. The method of manufacturing a semiconductor device according to claim 9, further comprising: 11. The method of manufacturing a semiconductor device according to claim 9, wherein the heat treatment is a rapid heat treatment. 12. The method of manufacturing a semiconductor device according to claim 9, wherein the heat treatment is high vacuum annealing. 13. The rapid thermal processing is about 500 ° C. to 800 ° C.
12. The method according to claim 11, wherein the temperature range is ° C.
A method for manufacturing a semiconductor device as described above. 14. The method of claim 11, wherein the rapid thermal processing is performed for about 10 seconds to 30 seconds. 15. The high vacuum annealing is performed at 500.degree.
13. The method for manufacturing a semiconductor device according to claim 12, wherein the temperature is 700 [deg.] C. 16. The method according to claim 12, wherein the high vacuum annealing is performed for 1 to 5 minutes. 17. The method of manufacturing a semiconductor device according to claim 9, wherein the heat treatment is performed in a non-oxidizing gas atmosphere. 18. The non-oxidizing gas atmosphere comprises at least one inert gas.
A method for manufacturing a semiconductor device as described above. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the inert gas is any one selected from the group consisting of nitrogen, argon, and a mixture thereof. 20. A step of sequentially forming a gate oxide film, a polysilicon layer, a WSi ₂ layer and a first HTO layer on a semiconductor substrate, and a step of photo-etching the first HTO layer to form a first HTO pattern. , dry etching step of forming the said WSi ₂ layer and the polysilicon layer by dry etching the WSi ₂ layer pattern and the polysilicon layer pattern to the gate oxide film is exposed a second 1HTO pattern as an etch mask A heat treatment step of heat-treating the resultant product obtained in the dry etching step at a temperature higher than the boiling point of the by-product generated in the dry etching step to remove by-products generated in the dry etching step, After the second HTO layer is formed on the entire surface of the resultant obtained in the heat treatment step, the second HTO layer is anisotropically etched to obtain the first HTO pattern and the WSi ₂ layer pattern. A step of forming an HTO spacer on a side surface of the polysilicon layer pattern and a turn, and a method of manufacturing a semiconductor device.