JPH07254558A - Positioning method - Google Patents

Abstract

PURPOSE:To prevent a drop in individual reliability of mark positioning information measured by turning an adjacent shot region into an alternative alignment shot when the mark position measuring accuracy for predetermined shot region has been deteriorated. CONSTITUTION:When accuracy deterioration has occurred in the mark position measurement by laser interferometers 9 and 10, the positional information of the mark for a shot region positioned in the neighborhood of a specific short region where the mark is provided is additionally measured by the movement of a stage 3 and laser interferometers 9 and 10. In this case, mark position information with deteriorated accuracy is ignored, and the moving position of the stage 3 is so determined that each of respective shot regions to be exposed on a photosensitive substrate will be aligned relative to the center of exposure of laser light by using m-number of mark positioning data in total. And the stage 3 is sequentially moved in accordance with the movement positions thus determined and then superimposed together and exposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure apparatus for a semiconductor manufacturing apparatus, and more particularly to an alignment method suitable for an apparatus for exposing a shot area on a sensitive substrate by a step-and-repeat method, and a master for exposure. The present invention relates to a method for performing precise relative alignment between a mask or reticle and a semiconductor wafer to be exposed.

[0002]

2. Description of the Related Art In recent years, semiconductor devices such as ICs and LSIs have been rapidly miniaturized and highly densified, and devices for manufacturing such devices, particularly masks and reticles, have a circuit pattern formed on a circuit pattern formed on a semiconductor wafer. Highly accurate exposure apparatuses are also required to be transferred in superposition. The circuit pattern on the mask and the circuit pattern on the wafer are required to be superimposed with an accuracy of, for example, 0.1 μm or less,
Therefore, at present, such an exposure apparatus exposes a mask circuit pattern to a local region (for example, one chip) on the wafer, and then advances the wafer a certain distance (stepping) to expose the mask circuit pattern again. A so-called step-and-repeat type apparatus, which repeats the above-mentioned steps, in particular, a reduction projection type exposure apparatus (stepper) has become the mainstream.
In this step-and-repeat method, the wafer is placed on a stage that moves two-dimensionally and positioned with respect to the projected image of the circuit pattern of the mask, so that the projected image and each chip on the wafer can be precisely overlapped. it can. Further, in the case of a reduction type exposure apparatus, a through-the-lens that directly observes or detects a mark for alignment provided on a mask or reticle and a mark attached to a chip on a wafer by directly observing or detecting the mark. System alignment method and the off-axis alignment method that sends the wafer directly below the projection lens after aligning the entire wafer using a positioning microscope provided at a fixed distance from the projection lens. There are two methods.

[0003]

Generally, in the through-the-lens method, since alignment is performed for each chip on a wafer, overlay accuracy is high, but there is a problem that the exposure processing time for one wafer becomes long. . In the case of the off-axis method, once the alignment of the entire wafer is completed, the wafer is simply stepped according to the chip arrangement, so the exposure processing time is shortened. However, since alignment is not performed for each chip, satisfactory overlay accuracy cannot always be obtained due to the effects of expansion and contraction of the wafer, rotation error of the wafer on the stage, and orthogonality of movement of the stage itself.

On the other hand, as a positioning method using a projection exposure apparatus having a through-the-lens type alignment system,
For example, in Japanese Unexamined Patent Publication No. 59-54225, some typical chip areas of a plurality of chip areas on a wafer are aligned with a mask in advance, and the alignment result (provided in the chip area is provided. A positioning method has also been proposed in which the characteristics (trends) of the array of chip areas on the wafer are obtained based on the mark detection results) and then the wafer is moved by the step-and-repeat method. With this method, it is not necessary to perform alignment for each chip on the wafer at the time of exposure, and therefore the processing time for one wafer does not become so long.

However, as disclosed in the above publication, when the alignment (mark position detection) is performed only on a typical chip area on the wafer, the accuracy of the mark detection attached to the chip area deteriorates. Then, the array characteristics of the chip area determined thereafter become extremely unreliable. Such deterioration in the accuracy of mark detection occurs accidentally due to the deformation of the mark caused by the wafer processing process, the adhesion of dust to the mark, or the like.

Therefore, the present invention does not perform mark detection for alignment at the exposure position of a pattern image of a mask or the like for all of a plurality of chips (shot areas) arranged on a sensitive substrate such as a wafer, An object of the present invention is to provide a positioning method which detects a mark only in a typical shot area and prevents the accuracy deterioration caused by the mark deformation due to the influence of the process.

[0007]

To achieve this object, the present invention provides a plurality of shot areas (Cn) arranged two-dimensionally according to a predetermined arrangement coordinate system (αβ) and each of the plurality of shot areas. A sensitive substrate (WA) having alignment marks (SXn, SYN) attached thereto is placed on a stage (3) which is two-dimensionally movable, and the stage is exposed by exposure means (R, 1). ) Predetermined exposure center (AX)
The pattern image (Pr) from the exposure means
Is applied to the shot area of the sensitive substrate so as to be overlaid and exposed.

In the present invention, a step of designating four or more m shot areas which are not adjacent to each other among a plurality of shot areas on the sensitive substrate as specific shot areas for alignment, and a predetermined distance from the exposure center of the exposure means. Using mark position measuring means (9, 10, 30 to 38, 41 to 48) that has detection areas (LXS, LYS) at positions separated by a distance and photoelectrically measures the position information of the mark, m The step of instructing the movement of the stage is executed so that the marks attached to each of the specific shot areas are guided to the detection areas one after another in a predetermined order and photoelectrically measured.

Further, according to the present invention, when the accuracy of the mark position measurement by the mark position measuring means deteriorates, the mark of the shot area located next to the specific shot area to which the mark having the accuracy deterioration is attached is detected. There is a step of additionally measuring the position information by the movement of the stage and the mark position measuring means, and when the additional measurement is performed, the mark position information whose accuracy is deteriorated is ignored and a total of m mark position information is used. Determining the movement position of the stage such that each shot area to be exposed on the sensitive substrate is aligned with the exposure center of the exposure means, and the stages are sequentially moved in accordance with the determined movement position to superimpose them. And the step of performing exposure.

[0010]

In the present invention, typical m pieces of a plurality of chip pattern (shot) areas formed on a sensitive substrate such as a wafer are designated in advance, and marks provided in each of the designated shot areas. For the shot area whose measurement accuracy deteriorates when measuring the position of, the mark position measurement is actually performed on the alternative shot area adjacent to the vicinity of the shot area. For this reason, the mark of a typical shot area specified in advance is accidentally deformed due to the influence of the processing process, or dust is accidentally attached to the mark, and the shot cannot be shot with the original measurement accuracy. The characteristics of the array (linear expansion / contraction error, residual rotation error, orthogonality error, offset error) are prevented from being determined, and the characteristic of the shot array can be determined using the mark position information with higher reliability. Become.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a perspective view showing the schematic construction of a reduction projection type exposure apparatus suitable for carrying out the method of the present invention.
The reticle R, which is the projection original plate, is positioned in such a manner that its projection center passes through the optical axis of the projection lens 1 and is mounted on the apparatus. The projection lens 1 reduces the circuit pattern image drawn on the reticle R to 1/5 or 1/10 and projects it onto the wafer WA. The wafer holder 2 is provided so as to vacuum-suck the wafer WA and to be finely rotatable with respect to the stage 3 which is two-dimensionally moved in the x direction and the y direction. The drive motor 4 is fixed on the stage 3 and rotates the wafer holder 2. The movement of the stage 3 in the x direction is performed by driving the motor 5, and the movement of the stage 3 in the y direction is performed by driving the motor 6. A reflection mirror 7 having a reflection plane extending in the y direction and a reflection mirror 8 having a reflection plane extending in the x direction are fixedly provided on two sides of the stage 3 which are orthogonal to each other. A laser light wave interferometer (hereinafter simply referred to as a laser interferometer) 9 projects laser light onto a reflection mirror 8 to detect the position (or movement amount) of the stage 3 in the y direction, and the laser interferometer 10 reflects the laser light. Laser light is projected onto the mirror 7 to detect the position (or movement amount) of the stage 3 in the x direction. Off-axis type wafer alignment microscopes (hereinafter referred to as WAMs) 20 and 21 are provided on the side of the projection lens 1 in order to detect (or observe) alignment marks on the wafer WA. . The WAM 21 is located after the projection lens 1 in FIG. 1 and is not shown. The WAMs 20 and 21 each have an optical axis parallel to the optical axis AX of the projection lens 1,
A band-shaped laser spot light YSP elongated in the x direction,
The image of θSP is formed on the wafer WA. (Spot light YS
P and θSP are not shown in FIG. ) These spot lights Y
SP and θSP are light having a wavelength that does not expose the photosensitive agent (photoresist) on the wafer WA to light, and in the present embodiment, they vibrate in the y direction with a minute amplitude. And WAM 20, 2
Reference numeral 1 denotes a mark having a photoelectric element that receives scattered light or diffracted light from the mark and a circuit that synchronously rectifies the photoelectric signal at the oscillation cycle of the spot light, and is a mark with respect to the vibration center of the spot light θSP (YSP) in the y direction. An alignment signal corresponding to the amount of shift in the y direction is output. Therefore, the WAMs 20 and 21 have the same structure as a so-called spot light vibration scanning type photoelectric microscope.

The apparatus is provided with a laser step alignment (hereinafter referred to as LSA) optical system for detecting a mark on the wafer WA via the projection lens 1. A laser light flux L generated from a laser light source (not shown) and passed through an expander (not shown), a cylindrical lens, etc.
B is light having a wavelength that does not expose the photoresist, and is incident on the beam splitter 30 to be split into two light beams. One of the laser light fluxes is reflected by the mirror 31, passes through the beam splitter 32, and is converged by the imaging lens group 33 so as to be a spot light having a belt-shaped cross section. Then, the reticle R and the projection lens 1 are combined. Between the first folding mirror 34 arranged so as not to block the projection optical path of the circuit pattern.
Incident on. The first folding mirror 34 reflects the laser light beam upward toward the reticle R. The laser light flux is provided below the reticle R and is incident on a mirror 35 having a reflection plane parallel to the surface of the reticle R, and the projection lens 1
Is reflected toward the center of the entrance pupil of. The laser light flux from the mirror 35 is converged by the projection lens 1 and the wafer W
An image is formed on A as strip-shaped spot light LYS elongated in the x direction. The spot light LYS is x on the wafer WA.
It is used to relatively scan a diffraction grating mark extending in the direction in the y direction and detect the position of the mark.
When the spot light LYS illuminates the mark, diffracted light is generated from the mark. The optical information again returns to the projection lens 1, the mirror 35, the mirror 34, the imaging lens group 33, and the beam splitter 32, is reflected by the beam splitter 32, and is an optical element 3 including a condenser lens and a spatial filter.
It is incident on 6. This optical element 36 transmits the diffracted light (first-order diffracted light or second-order diffracted light) from the mark, and specularly reflected light (0
The secondary diffracted light is blocked, and the diffracted light is condensed on the light receiving surface of the photoelectric element 38 via the mirror 37. The photoelectric element 38 outputs a photoelectric signal according to the amount of condensed diffracted light. As described above, the mirror 31, the beam splitter 32, the imaging lens group 33, the mirrors 34 and 35, the optical element 36, the mirror 37,
The photoelectric element 38 constitutes a through-the-lens alignment optical system (hereinafter referred to as a Y-LSA system) that detects the position of the mark on the wafer WA in the y direction.

On the other hand, another laser beam split by the beam splitter 30 is incident on a through-the-lens type alignment optical system (hereinafter referred to as an X-LSA system) for detecting the position of the mark on the wafer WA in the x direction. To do. X-LSA
The system is exactly the same as the Y-LSA system, including a mirror 41, a beam splitter 42, an imaging lens group 43, and mirrors 44, 4.
5, an optical element 46, a mirror 47, and a photoelectric element 48, and forms an image of a strip-shaped spot light LXS elongated in the y direction on the wafer WA.

The main controller 50 inputs the photoelectric signals from the photoelectric elements 38 and 48, the alignment signals from the WAMs 20 and 21, and the position information from the laser interferometers 9 and 10, and performs various calculations for alignment. In addition to performing the processing, it outputs a command for driving the motors 4, 5, and 6. The main controller 50 includes an arithmetic processing unit such as a microcomputer or a minicomputer, and the arithmetic processing unit includes design position information (chip array coordinate values on the wafer WA) of a plurality of chips CP formed on the wafer WA. Etc.) are stored.

FIG. 2 shows the WAMs 20 and 21 and the Y-LSA.
System, spot light θSP, YSP, L by X-LSA system
FIG. 6 is a plan view showing the arrangement relationship on the image plane (the same as the surface of the wafer WA) of the projection lens 1 of YS and LXS. Figure 2
In, when the coordinate system xy with the optical axis AX as the origin is defined, the x-axis and the y-axis represent the moving direction of the stage 3, respectively. In FIG. 2, a circular area centered on the optical axis AX is an image field if, and a rectangular area inside thereof is a projected image Pr of the effective pattern area of the reticle R. The spot light LYS is formed at a position outside the projection image Pr in the image field if and coincides with the x-axis,
The spot light LXS is also formed at a position outside the projection image Pr in the image field if and coincides with the y-axis. On the other hand, the vibration centers of the two spot lights θSP and YSP are aligned on a line segment (parallel to the x-axis) LL separated from the x-axis by the distance Y _{0 in the} y-direction, and the distance Dx in the x-direction is equal to the wafer. It is defined to be a value smaller than the diameter of WA. In this device, spot light θSP, YS
P is arranged symmetrically with respect to the y-axis, and the main controller 50 controls the spot light θSP with respect to the projection point of the optical axis AX,
It stores information about the position of the YSP. Further, main controller 50 controls spot light L with respect to the projection point on optical axis AX.
Center position (distance X1) of YS in the x direction and spot light LX
Information on the center position of S in the y direction (distance Yl) is also stored.

Next, the alignment method according to the present invention using this device will be described with reference to the flowchart of FIG. 3 together with the operation of the device. Note that this alignment is performed on the wafer WA.
Of the wafer W
The chip and the alignment mark are already formed on A. First, in step 100, the wafer WA is roughly positioned by using a pre-alignment device (not shown) so that the linear notch (flat) of the wafer WA faces in a certain direction. The flat of the wafer WA is positioned so as to be parallel to the x-axis as shown in FIG.

Next, in step 101, the wafer WA is transferred onto the wafer holder 2 on the stage 3 and the flat wafer is moved to x.
It is placed on the wafer holder 2 so as to be parallel to the axis,
Vacuum adsorption. On the wafer WA, for example, as shown in FIG. 4, a plurality of chips Cn are formed in a matrix along the orthogonal array coordinates αβ on the wafer WA. The α axis of the array coordinate αβ is substantially parallel to the flat of the wafer WA. In FIG. 4, among the plurality of chips Cn, only the chips C _{0 to} C ₆ that are lined up in a line on the α axis that passes through substantially the center of the wafer WA having the array coordinate αβ are shown as a representative. Each chip C
₀ -C marks for each of the ₆ four alignment G
Y, Gθ, SX, and SY are provided together.

Now, chip C₀~ C₆Chip C in the center of₃
When the center of is the origin of array coordinate αβ, α is on the α-axis.
Diffraction grating mark SY extending linearly in the direction₀~ SY₆
But each chip C₀~ C₆It is provided on the right side of. Well
Chip C₃Linearly in the β direction on the β axis passing through the center of
Extended diffraction grating mark SX₃Is chip C₃Below
Other chip C provided₀, C₁, C₂, C_Four, C_Five,
C₆Also goes through the center of the chip and is parallel to the β axis.
Mark SX on the line₀~ SX₂, SX_Four~ SX ₆Is provided
Has been. These marks SY_n, SX_nAre each
It is detected by the pot lights LYS and LXS.
It

Below the chips C _{0 to} C ₆ , marks GY _{0 to} GY ₆ and Gθ _{0 to} G used to align the entire wafer WA (global alignment).
θ ₆ is provided. These marks GY _n and Gθ _n are formed in a pattern on a diffraction grating linearly extending in the α direction on a line segment parallel to the α axis. Further, of the chips C _{0 to} C ₆ arranged in a line in the α direction, for example, the leftmost chip C _0.
Mark GY ₀ and the mark Gθ ₆ of the rightmost chip C ₆ in the α direction are the spot light θ by the WAMs 20 and 21.
It is set so as to match the interval DX between SP and YSP.

In other words, in this embodiment, the global alignment of the wafer WA is performed by the off-axis method using the marks GY ₀ and the marks Gθ ₆ which are separated from each other. Therefore, the other marks GY _{1 to} GY ₆ and the marks Gθ _{0 to} Gθ ₅ are originally unnecessary and may be omitted. In short, it is sufficient that two marks elongated in the α direction are present on the line segment parallel to (or coincident with) the α-axis of the wafer WA and separated by the distance DX.

Now, the main control unit 50 determines the position information of the stage 3 when the wafer WA is received from the pre-alignment unit, and the marks GY ₀ and Gθ ₆ are W based on the position information.
Information such as the moving direction and the moving amount of the stage 3 until it is positioned within the detection (observation) field of view of the AMs 21 and 20 is stored in advance as constants unique to the apparatus. Then, the next step 102
In, the main controller 50 first drives the motors 5 and 6 to position the stage 3 so that the mark GY ₀ is located within the detection field of view of the WAM 21. After that, main controller 50 controls stage 3 based on the alignment signal from WAM 21 and the position information from laser interferometer 9 so that the center of vibration of spot light YSP coincides with the center of mark GY _{0 in} the y direction. Precise positioning in the direction. When the vibration center of the spot light YSP and the center of the mark GY ₀ coincide with each other, the main controller 50 keeps the state so that the motor 6 is servo (feedback) controlled by the alignment signal from the WAM 21 and the mark Gθ _{6 is} maintained. Is WA
The motor 4 is driven to rotate the wafer holder 2 as detected by the spot light θSP of M20. Furthermore the main control unit 50 so that the center of the y direction of the vibration center of the mark Jishita ₆ spotlight θSP match, WAM2
The motor 4 is servo-controlled by the alignment signal from 0.

With the above series of operations, the spot light YS
P and the mark GY ₀ match, the spot light θSP and the mark Gθ ₆ match, the rotational displacement of the array coordinate αβ of the wafer WA with respect to the moving coordinate system of the stage 3, that is, the coordinate system xy is corrected, and the coordinate system xy is corrected. And y of array coordinate αβ
The association (definition) regarding the position in the direction (β direction) is completed.

Next, the mark SX ₃ of the chip C ₃ located at the center of the wafer WA is the spot light L of the X-LSA system.
After the stage 3 is positioned so as to be scanned by XS, it is moved in the x direction. At this time, the main controller 50 moves the x direction of the wafer WA when the mark SX ₃ coincides with the spot light LXS based on the time-series photoelectric signal from the photoelectric element 48 and the position information from the laser interferometer 10. The position is detected and stored. This completes the association of the coordinate system xy and the position of the array coordinate αβ in the x direction (α direction). Note that this association in the x direction is not necessary when the X-LSA system is used immediately before the exposure operation.

By the above operation, the global alignment of the wafer WA (corresponding the array coordinates αβ to the coordinate system xy) mainly for off-axis alignment is completed. Then, according to the conventional method, the main controller 50 causes the laser interferometer 9 to execute the laser beam based on the array design value of each chip on the wafer WA (the central coordinate value of the chip at the array coordinates αβ).
The projected image P of the reticle R is read by reading the position information from
The stage 3 is positioned (addressing) by the step-and-repeat method so that r overlaps the chip, and then the chip is exposed (printed).

However, by the time the global alignment is completed, the accuracy of the alignment detection system, the setting accuracy of each spot light, or the position detection accuracy due to the optical or geometrical state (influence of the process) of each mark on the wafer WA. Errors occur due to variations, etc., and the wafer WA chips are precisely aligned (addressing) according to the coordinate system xy.
It is not always done. Therefore, in the embodiment of the present invention, it is assumed that the error (hereinafter referred to as shot address error) is caused by the following four factors.

(1) Rotation of wafer: This occurs because the positional relationship between the two spot lights YSP and θSP, which serve as a reference for alignment, is not accurate when the wafer WA is rotationally corrected, for example. It is represented by the residual rotation error amount θ of the array coordinate αβ with respect to the system xy. (2) Orthogonality of the coordinate system xy; this occurs because the feed directions of the motors 5 and 6 of the stage 3 are not exactly orthogonal, and is represented by the orthogonality error amount w.

(3) Linear expansion / contraction of the wafer in the x (α) direction and the y (β) direction; this may cause the entire expansion / contraction of the wafer WA due to the processing process of the wafer WA. For this reason, the actual chip position deviates from the designed array coordinate value of the chip in the α and β directions by a small amount, which is particularly remarkable in the peripheral portion of the wafer WA. The amount of expansion and contraction of the entire wafer is represented by Rx and Ry in the α (x) direction and the β (y) direction, respectively. Where Rx is the ratio of the measured value between the two points in the x direction (α direction) on the wafer WA and the design value, and Ry is the measured value of the distance between the two points in the y direction (β direction) on the wafer WA. And the design value. Therefore,
When both Rx and Ry are 1, there is no expansion / contraction.

(4) Offsets in the x (α) direction and the y (β) direction; this is due to the detection accuracy of the alignment system and the positioning accuracy of the wafer holder 2, etc., so that the wafer WA as a whole is minute in the x and y directions. It is caused by a shift in the amount, and is represented by offset amounts Ox and Oy. In FIG. 4, the residual rotation error amount θ of the wafer WA and the orthogonality error amount w of the stage 3 are exaggerated.

In this case, the Cartesian coordinate system xy is actually an oblique coordinate system xy 'inclined by a small amount w, and the wafer WA is rotated by θ with respect to the Cartesian coordinate system xy. When the error factors (1) to (4) are added, the shot position (Fxn, Fy) to be actually positioned for the shot (chip) at the coordinate position (Dxn, Dyn) in design.
n) is expressed as follows. However, n is an integer and represents a shot (chip) number.

[0030]

[Equation 1]

Here, w is originally a minute amount, and θ is also driven to a minute amount by global alignment. Therefore, when the first-order approximation is performed, formula (1) is expressed by formula (2).

[0032]

[Equation 2]

From this equation (2), the positional deviation (εxn, εyn) from the design value at each shot position can be calculated by the equation (3).
It is represented by.

[0034]

[Equation 3]

By rewriting the equation (2) into a matrix arithmetic expression, the following is obtained.

[0036]

[Formula 4] Fn = A · Dn + O ··· (4)

[0037]

[Equation 5]

[0038]

[Equation 6]

[0039]

[Equation 7]

[0040]

[Equation 8]

Therefore, when the actual shot (chip) position is measured by detecting the mark and the measured value is detected as Hn, the positional deviation from the shot position Fn to be positioned, that is, the address error En (= Hn-Fn). ) To minimize the error parameter A (transform matrix), O
Determine the (offset). If the least squares error is taken as the evaluation function, the address error E is expressed by the equation (9).

[0042]

[Equation 9]

Therefore, the error parameters A and O are determined so as to minimize the address error E. However, in Expression (9), m represents the number of actually measured chips among the plurality of chips on the wafer WA. Now, when obtaining the error parameters A and O,
If the least squares method is used, the amount of calculation is large as it is, so the error parameter O (Ox, Oy) is separately determined in advance. Offset amount (Ox, O
Since y) is a global offset value of the wafer WA, it is advisable to use a value obtained by averaging the address error with respect to the design value (Dxn, Dyn) by the number m of the actually measured chip positions Hn on the wafer WA.

[0044]

[Equation 10]

[0045]

[Equation 11]

By the way, the shot position Fn to be positioned
Of the error En between the measured value Hn and the measured value Hn, the component Exn in the x direction
Is from equation (4) to equation (8),

[0047]

Equation 12] Exn = Hxn-Fxn = Hxn- a 11 Dxn-a 12 Dyn-Ox ·· (12) becomes, y direction component Eyn error En is likewise

[0048]

[Equation 13] Eyn = Hyn-Fyn = Hyn-a ₂₁ Dxn-a ₂₂ Dyn-Oy (13) Therefore, when the error parameter A is determined so as to minimize the error E in the equation (9), the elements a ₁₁ , a ₁₂ , a ₂₁ ,
a ₂₂ is as follows.

[0049]

[Equation 14]

[0050]

[Equation 15]

[0051]

[Equation 16]

[0052]

[Equation 17]

When the elements a ₁₁ , a ₁₂ , a ₂₁ and a ₂₂ are obtained,
From the equation (6), the linear expansion / contraction amounts Rx, Ry, the residual rotation error amount θ, and the orthogonality error amount w can be immediately obtained. Rx = a ₁₁ (18) Ry = a ₂₂ (19) θ = a ₂₁ / Ry = a ₂₁ / a ₂₂ (20) w =-(a ₂₁ / Ry)-(a ₁₂ / Rx) = − (a ₂₁ / a ₂₂ ) − (a ₁₂ / a ₁₁ ) ... (21) Therefore, in order to determine the error parameters A and O, some on the wafer WA after the global alignment is completed. (4
Three or more) chips, the positions of the marks SXn, SYN are measured by using the X-LSA, Y-LSA system to obtain the measured values (Hxn, Hyn), and the measured design values (Dxn, Dyn) of the chips. Using equation (10),
The operations (11), (14) to (17) may be performed. Therefore, returning to the flowchart of FIG. 3, the description of the operation is continued. Main controller 50 measures the positions of a plurality of chips on wafer WA after the global alignment is completed.
First, in step 103, main controller 50 positions stage 3 based on the array design value so that X-LSA spot light LXS is aligned in parallel with mark SX ₀ associated with chip C ₀ at the left end in FIG. After that, the stage 3 is moved (scanned) in the x direction by a certain amount so that the mark SX ₀ crosses the spot light LXS.

During this movement, main controller 50 stores the waveform of the time-series photoelectric signal of photoelectric element 48 in association with the position information in the x direction from laser interferometer 10, and stores it from the waveform state to mark SX _0. The position x ₀ at which the spot light LXS and the spot light LXS match in the x direction is detected. Next, main controller 5
0 is the step 104, and the spot light LYS of the Y-LSA system.
The stage 3 is positioned on the basis of the array design value so that are aligned in parallel with the mark SY ₀ attached to the chip C ₀ . After that, the stage 3 is moved in the y direction by a certain amount so that the mark SY ₀ crosses the spot light LYS.

At this time, the main controller 50 controls the photoelectric element 38
The time-sequential photoelectric signal waveform is displayed in the y direction from the laser interferometer 9.
Stored in association with the position information of the
SY ₀And spot light LYS coincided with each other in the y direction.
Time position y₀To detect. And the main controller 50 is
The same position detection for m chips with step 105
It is judged whether or not it has been performed, and if it is not, step 106
To the other chips on the wafer WA based on the array design value.
Then, move the stage 3 and start again from step 103.
The same position detection operation is repeated.

In this embodiment, for example, as shown in FIG. 5, four chips C ₀ , C ₆ , C ₇ and C ₈ are arranged at substantially equal distances from the center of the wafer WA along the respective axes of the array coordinate αβ.
And for each of the central five single chip chips C ₃ assumed that the position detecting step 103 is performed. Therefore, when it is determined in step 105 that m = 5, the main controller 50 has five measured values (Hxn, Hyn).
Will be remembered. That is, (Hx ₁ , Hy ₁ ) = (x ₀ , y ₀ ) ... Chip C ₀ (Hx ₂ , Hy ₂ ) = (x ₃ , y ₃ ) ... Chip C ₃ (Hx ₃ , Hy _3). ) = (X ₆ , y ₆ ) ... Chip C ₆ (Hx ₄ , Hy ₄ ) = (x ₇ , y ₇ ) ... Chip C ₇ (Hx ₅ , Hy ₅ ) = (x ₈ , y ₈₎ ) ... Five measured values of the chip C ₈ are sequentially detected.

Furthermore, when detecting these five measured values,
The measured value of a certain chip is the design value of that chip (Dxn, D
yn), if the difference is more than twice the positioning accuracy determined by global alignment, the measured value at that chip is ignored, and the mark position on the chip next to that chip is ignored. Is measured. This is because when the mark of the chip to be actually measured happens to be deformed by the processing process, if dust is attached to the mark, the contrast of the optical image of the mark (the generated intensity of diffracted light) is weak, and the S of the photoelectric signal is reduced. This is to compensate for the accuracy deterioration of the position measurement that occurs when the / N ratio is low, and such additional measurement is executed as a characteristic procedure of the present invention.

As a method of compensating for the accuracy deterioration of the position measurement, a total of 9 chips in addition to 6 chips or more, for example, chips located in each of the four quadrants of αβ in the array coordinates in FIG. Position measurement on the chip, part 9
The design value (Dxn, Dy
There is a method of selecting five measured values in the order closest to n), or a method of not using the measured values (Hxn, Hyn) that are greatly different from the design values (Dxn, Dyn) for the subsequent arithmetic processing. .

Next, in step 107, the main control device 50 causes the above equations (10), (11) and equations (14) to (1) to be calculated.
The error parameters A and O are determined based on 7). In making this determination, main controller 50 has preselected five design values for each chip from which the above-mentioned five measured values have been detected.
The design value (Dxn, Dyn) is stored as follows.

(Dx ₁ , Dy ₁ ) = (x ₀ ′, y ₀ ′) chip C ₀ (Dx ₂ , Dy ₂ ) = (x ₃ ′, y ₃ ′) chip C ₃ ( Dx ₃ , Dy ₃ ) = (x ₆ ′, y ₆ ′) chip C ₆ (Dx ₄ , Dy ₄ ) = (x ₇ ′, y ₇ ′) chip C ₇ (Dx ₅ , Dy). ₅ ) = (x ₈ ', y ₈ ') ... Chip C ₈ or 5 prior to the determination of the actual error parameters A, O
Each time position measurement (so-called step alignment) of one chip is completed, for example, while moving the stage 3 in step 106 of FIG. 3, equations (10), (11), (1
It is possible to execute some of the operations 4) to 17) at the same time. That is, equations (10), (11), (14)
In (17), the arithmetic element representing the algebraic sum of the data (measured value, design value) for each chip is sequentially added every time the measurement (step alignment) of one chip is completed. The calculation elements are as follows.

[0061]

[Equation 22]

Further, among these calculation elements, the wafer WA
If the chip to be actually measured is determined in advance and there is no change, steps 103, 104, 105, 1 in FIG. 3 for the calculation element including only the design value (Dxn, Dyn).
It is also possible to calculate it before executing 06. In this way, if some calculations are performed in parallel with the measurement operation of the actual measurement value, the total alignment time will not be so long. Then, at the stage where the five measured values are obtained, the main controller 50 uses the results of the above-described calculation elements to calculate equations (10), (1
After calculating the offset amount (Ox, Oy) in 1), using the offset value and the result of the above-mentioned arithmetic element, the elements a ₁₁ , a ₁₂ , a ₂₁ , a of the array are further expressed by the equations (14) to (17).
Calculate ₂₂ .

Since the error parameters A and O are determined by the above arithmetic operation, the position to be positioned for each chip of the wafer WA is calculated by using the above equation (4) in the next step 108 of the main controller 50. , That is, the shot address (Fxn, Fy corrected by the error parameter
n) is calculated, and a chip array map (shot address table) corrected with respect to the design value (Dxn, Dyn) is created on the storage means (semiconductor memory). This array map is, for example, for the chip C ₀ , the position (Fx ₀ , F
y _0), the position is relative to the chip C ₁ (Fx _1, F
y ₁ ), ..., Each position data is stored corresponding to the chip number.

Next, the main controller 50 uses the step 10 of FIG.
At 9, the stage 3 is positioned (addressing) by the step-and-repeat method according to the stored array map. As a result, the chip on the wafer WA and the projection image Pr of the reticle R are accurately overlapped with each other, and in the next step 110, the projection image Pr is exposed (printed) on the chip.
To do.

When the exposure of all the chips on the wafer WA is not completed in step 111, step 1 is executed again.
Similarly, the step and repeat operation is repeated from 09. If it is determined in step 111 that the exposure of all the chips on the wafer WA has been completed, the wafer WA is unloaded in the next step 112, and the exposure processing for one wafer is completed.

As is clear from the embodiments of the present invention described above, the larger the number of chips to be step-aligned on the wafer WA, the higher the measurement accuracy, but the longer the measurement time. Therefore, it is desirable to select five chips for step alignment as shown in FIG. 5, in order to reduce the measurement time and improve the measurement accuracy. However, when the minimum line width of the circuit pattern for overlay exposure is not so thin (for example, 2 to 5 μm) and it is not necessary to increase the measurement accuracy, the wafer W
Three chips on A (eg C ₀ , C ₆ ,
It is sufficient to perform step alignment (chip position measurement) for C ₇ ) and the measurement time is further shortened.

Further, during the step alignment, instead of detecting both the x-direction and y-direction positions of each chip, each of the marks SXn attached to the plurality of chips to be step-aligned is detected by an X-LSA spot light. LX
After performing relative scanning (stage scan) collectively with S to detect only the position of each chip in the x direction, the marks SYN of each chip are collectively scanned with the spot light LYS of the Y-LSA system to detect each chip. You may make it detect the position of ay direction. With this configuration, when there are a plurality of chips to be measured in the same column or row on the chip array, the position measurement can be performed at a higher speed than the position detection in the x direction and the y direction for each chip. Can be expected.

If the main controller 50 inputs data for arbitrarily selecting which chip on the wafer WA is to be step-aligned from a keyboard device (not shown), it changes depending on the processing conditions of the wafer WA. It is possible to more flexibly cope with the surface condition (particularly the mark shape) that is changed, and it is expected to improve the accuracy of position measurement.

In determining the offset amounts (Ox, Oy) using the equations (10) and (11), for example, only the position measurement result of the chips within the specified range from the center of the wafer WA may be used. Good. The specified range is defined, for example, within a circle having a diameter that is half the diameter of the wafer WA, or the size of the range is set to an exposure apparatus (reduction projection type, unit-size projection, when a chip or mark is formed on the wafer WA). It may be arbitrarily changed according to the accuracy characteristic of a stepper such as proximity.

Further, in this embodiment, the equation (4) is applied to all the chips of the wafer WA to perform the step-and-repeat type addressing.
The expression (4) can be applied in the same manner to so-called block alignment in which the surface of is divided into several regions (blocks) and optimal alignment is performed for each individual block.

For example, in FIG. 5, four chips located in each quadrant of array coordinate αβ and five chips C shown in the figure.
_{0, C 3, C 6,} C 7, perform the steps alignment for a total of nine chips with C _8, after detecting the actual value of the position of each chip, each quadrant every expression array coordinate .alpha..beta (1
The error parameters A and O are determined using 0), (11), (14) to (17), and the position (Fxn, Fyn) is calculated using equation (4).

For example, for the block of the first quadrant of the array coordinates αβ, one chip in the first quadrant and chip C
Equation (4) is determined using the measured values of the four chips, ₃ , C ₆ and C _7, and the second block is determined for the block in the second quadrant.
One chip in the quadrant and four chips C ₀ , C ₃ , C ₇
Equation (4) is determined using the measured values of the two chips. Then, during the actual exposure, the chips on the wafer WA are aligned with the projection image Pr based on the shot position (Fxn, Fyn) from the equation (4) determined for each block.

In this way, it is possible to reduce position detection and alignment defects due to non-linear elements on the wafer, and unlike the conventional block alignment, it is possible to form blocks while leaving the averaging elements. There is an advantage that the overlay accuracy in is almost averaged for all chips. Not only that, but also when used in combination with an exposure apparatus other than the stepper, particularly a mirror projection exposure apparatus, a great advantage can be obtained.

Generally, a chip array of a wafer baked by a mirror projection exposure apparatus is often curved. Therefore, when overlay exposure is performed on the wafer by the stepper (mixed use; mix and match), if the block alignment as described above is performed, the curvature of the chip array in each block becomes so small that it can be ignored. Printing with extremely high overlay accuracy can be performed over the entire surface of the wafer.

As described above, in the exposure apparatus suitable for the embodiment of the present invention, the spot light of the laser is applied to the mark on the wafer WA to detect the position of the mark (chip). By observing (detecting) an alignment system for performing simple vibration or linear scanning at a constant velocity, or a mark on the reticle R and a mark on the wafer WA through a microscope objective lens arranged above the reticle R. An exposure apparatus that uses a so-called die-by-die alignment optical system for performing alignment can be used in exactly the same manner.

In this case, if the reticle R is not finely moved in the x and y directions for alignment during die-by-die alignment, the projected image of the mark on the reticle R is the spot light LXS of this embodiment. , LYS. In the case of the method of slightly moving the reticle R, first, the reticle R is accurately set to the origin position and set. Then, during step alignment (measurement) of a plurality of chips, after the stage is stepped according to the array design value, the reticle R is finely moved so that the mark of the reticle R and the mark of the chip to be measured have a predetermined positional relationship. Then, by detecting the amount of movement of the reticle R in the x and y directions from the origin, it is possible to calculate the actual measurement value (Hxn, Hyn) of the position of the chip.

In this embodiment, the offset amount (Ox, O
Although the calculation process is simplified by separately obtaining y) separately, the error parameters A and O that minimize the address error E in the equation (9) may be calculated by a strict calculation process. Needless to say.

[0078]

As described above, according to the present invention, the alignment error is small on average for all of a plurality of chip patterns on a sensitive substrate such as a wafer, and a non-defective chip that can be obtained from one photosensitive substrate. The number is increased, and the productivity of semiconductor devices can be improved. In addition, avoiding the actual measurement in alignment shots where accuracy is deteriorated due to the influence of the process or the influence of dust, each position of 3 or more m chips (shot areas) on the sensitive substrate is always measured (step alignment). Therefore, the reliability of the determination of the shot area arrangement is improved. In addition, since the position measurement using the mark of the same shape is repeated multiple times, the mechanical and electrical random error of the detection system is reduced, and the variation in the sensitivity of the alignment sensor (microscope) for position detection is statistically analyzed. It will be suppressed by various processes, and the overall alignment accuracy will be improved.

The present invention is not limited to the reduction projection type exposure apparatus, but can be widely applied to a step-and-repeat type exposure apparatus, for example, an equal-magnification projection stepper or proximity type stepper (X-ray exposure apparatus). It is a thing.
In addition to the exposure equipment, it is a device for inspecting semiconductor wafers, photomasks having multiple chip patterns, etc. (defect inspection, prober, etc.) and aligns each chip with the inspection field of view and the reference position of the probe needle etc. by the step-and-repeat method. The present invention can be similarly implemented in the case of the thing.

[Brief description of drawings]

FIG. 1 is a perspective view showing a schematic configuration of a reduction projection type exposure apparatus suitable for an embodiment of the present invention.

FIG. 2 is a plan view showing a positional relationship between respective detection centers of an alignment system in the apparatus shown in FIG.

FIG. 3 is a flowchart showing an overall operation procedure using the alignment method of the present invention.

FIG. 4 is a plan view of a wafer suitable for alignment and exposure using the apparatus of FIG.

FIG. 5 is a plan view of a wafer showing the positions of chips for step alignment.

[Explanation of Signs of Main Parts] WA ... Wafer, CP,
Cn ... Chip, αβ ... Array coordinates, 103, 10
4 ... Actual measurement process by step alignment, 107
... Process of determining error parameter, 108, 10
9, 110, 111 ... Step of positioning by the step-and-repeat method along the corrected actual chip arrangement coordinates.

Claims (3)

[Claims] 1. A two-dimensional movement of a sensitive substrate having a plurality of shot areas arranged two-dimensionally according to a predetermined arrangement coordinate system and alignment marks attached to each of the plurality of shot areas. It is placed on a possible stage, and the stage is moved with respect to a predetermined exposure center of the exposure means so that the pattern image from the exposure means is superposed and exposed on the shot area of the sensitive substrate. In the method, (a) a step of designating four or more m shot areas which are not adjacent to each other among a plurality of shot areas on the sensitive substrate as specific shot areas for alignment; (b) exposure by the exposure means The m specific shot areas are provided by using a mark position measuring unit that has a detection area at a position separated from the center by a predetermined distance and photoelectrically measures the position information of the mark. And (c) instructing the movement of the stage so that the marks attached to each of them are sequentially guided to the detection region in a predetermined order and photoelectrically measured; When the accuracy deterioration occurs in the position measurement, the position information of the mark in the shot area located next to the specific shot area provided with the mark in which the accuracy deterioration occurs is determined by the movement of the stage and the mark position measuring means. (D) When the additional measurement is performed, the mark position information whose accuracy has deteriorated is ignored and a total of m mark position information is used to determine the shot area to be exposed on the sensitive substrate. Determining the movement position of the stage such that each is aligned with the exposure center of the exposure means; and (e) sequentially moving the stage according to the determined movement position. Alignment method which comprises a step of performing the serial superposition exposure. 2. A stage capable of two-dimensionally moving while holding a photosensitive substrate in which a plurality of shot areas are regularly arranged, a projection optical system for projecting a mask pattern image on each of the shot areas, and the projection. Mark detection means for photoelectrically detecting an alignment mark associated with a shot area on the photosensitive substrate through an optical system, and detecting position information of the mark based on the photoelectric signal, and based on the detected mark position information Using a projection exposure apparatus provided with a movement control means for controlling the movement position of the stage based on the coordinate position determined by the coordinate position or a predetermined coordinate position on the design,
In the method of aligning the photosensitive substrate with the pattern image of the mask, (a) out of a plurality of shot regions on the photosensitive substrate, three or more m specific shot regions which are not adjacent to each other are used as alignment shots. (B) Instructing the position control means of the moving position of the stage such that the marks associated with each of the m specific shot areas are sequentially detected by the mark detection means; (c) When the mark detection means photoelectrically detects a mark of the specific shot area and the photoelectric signal is deteriorated in accuracy and the mark position information cannot be acquired correctly, a position next to the specific shot area causing the accuracy deterioration is set. The movement control means determines the movement position of the stage such that the mark in the adjacent shot area is additionally detected by the mark detection means. And (d) based on each mark position information correctly acquired from each of the specific pattern area or the adjacent pattern area, the pattern area to be projected and exposed on the photosensitive substrate is the pattern image of the mask. Calculating the moving position of the stage to be aligned. 3. A photosensitive substrate on which a plurality of shot areas are regularly formed is held on a stage which moves two-dimensionally under a projection optical system for projecting and exposing a circuit pattern image, and some of the photosensitive substrates are provided on the photosensitive substrate. Position information of each mark is detected on the basis of a photoelectric signal from a mark detecting means for photoelectrically detecting each mark associated with the shot area of, and the exposure coordinate position at which the stage should be positioned at the time of exposure based on the mark position information. In the method of aligning each shot area on the photosensitive substrate with the circuit pattern image by determining, (a) determining the exposure coordinate position from a plurality of shot areas on the photosensitive substrate. A step of designating a plurality of specific shot areas that are not adjacent to each other as alignment shots so that the mark position information of a number larger than the required number m can be obtained; (b) instructing a moving position of the stage such that marks associated with each of the designated plurality of specific shot areas are sequentially detected by the mark detecting means in a predetermined order; (c) the marks Detecting each position information of the mark associated with each of the specific shot areas based on the photoelectric signal from the detection means, and from the detected mark position information, the deformation of the mark caused in the process of processing the photosensitive substrate. Selecting at least m mark position information excluding the ones that have a large accuracy deterioration due to (d) using all of the selected at least m mark position information. Calculating an exposure coordinate position of the stage such that a shot area is superimposed on the circuit pattern image.