JPH07249771A - Fabrication of misfet semiconductor device - Google Patents

Abstract

PURPOSE:To break through the limit of short channel by substantially shortening the channel length as well as the gate electrode length in the fabrication of an MISFET semiconductor device. CONSTITUTION:A gate electrode 24 is formed on a silicon semiconductor substrate 21B on the active layer side provided on an insulating film 22 which is embedded therein and in the silicon semiconductor substrate 21A on the supporting side. Impurity ions are then implanted using the gate electrode 24 as a mask to form an n-type source region 25 and an n-type drain region 26 extending from the surface to the embedded insulating film 22. Subsequently, it is heat-treated to extend the n-type source region 25 and the n-type drain region 26 through diffusion in the direction of channel thus shortening the channel length while breaking through the limit imposed by the gate electrode 24 used as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a thin film SOI (sil)
The present invention relates to an improvement in a method for manufacturing a MIS field effect semiconductor device using a con on insulator.

Currently, MISFETs (metal ins) are
ulator semiconductor field
d effect transistor) is being further miniaturized, and a semiconductor device including it is about to be highly integrated. However, since the miniaturization and high integration are beginning to be seen in various aspects, It is necessary to break down.

[0003]

2. Description of the Related Art Generally, it has been considered effective to shorten a channel in order to improve the performance of a MISFET. To realize this short channel, there is no practically effective means other than thinning the gate electrode.

FIG. 4 shows an LDD (lightly dope).
FIG. 7 is a cutaway side view of a main part showing a conventional example of a bulk type MISFET having a d drain) structure.

In the figure, 1 is a silicon semiconductor substrate, 2 is
Is a gate insulating film, 3 is a gate electrode, 4 is a low impurity concentration source region in the LDD structure, 5 is a low impurity concentration drain region in the LDD structure, 6 is a side wall, 4
A is a high impurity concentration source region in the LDD structure, 5A
Indicate the high impurity concentration drain regions in the LDD structure, respectively.

FIG. 5 shows a thin film SOI type MI having an LDD structure.
It is a principal part cutting side view showing the prior art example of SFET.

In the figure, 11A is a support-side silicon semiconductor substrate, 11B is an active layer-side silicon semiconductor substrate, 12 is a buried insulating film, 13 is a gate insulating film, 14 is a gate electrode, and 15 is a low LDD structure. Impurity concentration source region, 16 is a low impurity concentration drain region in the LDD structure, 17 is a sidewall, 15A is a high impurity concentration source region in the LDD structure, and 16A is a high impurity concentration drain region in the LDD structure. Shown respectively.

In the conventional example shown in FIG. 4, the low impurity concentration source region 4 and the low impurity concentration drain region 5 are formed by the self-alignment method using the gate electrode 3 as a mask, and as shown in FIG. In the conventional example,
Since the low impurity concentration source region 15 and the low impurity concentration drain region 16 are formed by the self-alignment method using the gate electrode 14 as a mask, in any case, the channel length thereof is the length of the gate electrode 3 or the gate electrode 3. It depends on the length of the electrode 14.

[0009]

However, when the gate electrode length is in the region of sub-quarter micron or less, it is difficult to form a fine gate electrode in terms of lithography technology, processing technology, cost, and the like. is there.

The present invention intends to cope with the shortening of the channel by making it possible to shorten the channel length substantially in addition to shortening the gate electrode length.

[0011]

According to the present invention, a thin film SOI is used.
The basic characteristic of the diffusion of impurities, namely, that the activation annealing of the ion-implanted impurities is appropriately performed and the channel length is substantially shortened by utilizing the diffusion of the impurities in the lateral direction. There is.

From the above, the MIS according to the present invention
In the method of manufacturing a field effect semiconductor device,

(1) Semiconductor (for example, support side silicon semiconductor substrate 21A and active layer side p-type silicon semiconductor substrate 21)
B) an insulating film embedded in the inside (for example, the embedded insulating film 2)
2) A step of forming a gate electrode (for example, the gate electrode 24) on the upper thin film semiconductor active layer (for example, the active layer side p-type silicon semiconductor substrate 21B), and then implanting impurity ions using the gate electrode as a mask A source region (for example, n-type source region 25) and a drain region (for example, n-type drain region 2) reaching the buried insulating film from the surface.
6) and then heat treatment to diffuse and extend the source region and the drain region in the channel direction to shorten the channel length, or

(2) A step of forming a gate electrode on the thin film semiconductor active layer on the insulating film embedded in the semiconductor, and then, by implanting impurity ions with the gate electrode as a mask, the embedded insulating film is formed from the surface. Low impurity concentration source region (for example, n-type source region 25) and low impurity concentration drain region (for example, n-type drain region 26)
And a step of performing a heat treatment to diffuse and extend the source region and the drain region in the channel direction to shorten the channel length, and then form a side wall made of an insulating film on the side surface of the gate electrode. And then implanting impurity ions using the gate electrode and the side wall as a mask to form a high impurity concentration source region (for example, n ⁺ − source) inside the low impurity concentration source region and the low impurity concentration drain region. Region 25A) and a high impurity concentration drain region (eg n ⁺
-Correspondingly forming a drain region 26A), or

(3) A solid impurity source (for example, solid impurity source 28) is formed on the portion where the source region is to be formed and the portion where the drain region is to be formed. And a step of forming a drain region.

[0016]

By adopting the above means, even when a gate electrode having a limit gate electrode length that can be formed by the conventional technique is formed, it can be compared with the normal channel length obtained by that. Since it is possible to realize a shorter channel length, it is possible to obtain a small-sized and high-speed switching MISFET which cannot be manufactured by the conventional technique. Therefore, the MIS field effect semiconductor device having improved performance can be highly integrated. be able to.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a side sectional view showing a main part of a MISFET in the process steps for explaining the first embodiment of the present invention.

In the figure, 21A is a support side silicon semiconductor substrate, 21B is an active layer side p type silicon semiconductor substrate, 2
2 buried insulating film made of SiO _2, 23 is SiO ₂
Is a gate insulating film made of polycrystalline silicon, 24 is a gate electrode made of polycrystalline silicon, 25 is an n-type source region, and 26 is an n-type drain region.

In order to manufacture this MISFET, (1) the supporting side silicon semiconductor substrate 21A and the active layer side p-type silicon semiconductor substrate 21B are provided with a buried insulating film 22 made of SiO ₂ by applying a usual technique. Pasted through.

(2) The active layer side p-type silicon semiconductor substrate 21B is thinned by applying a normal grinding / polishing method, and the thickness thereof is about the same as the depth of the source region and the drain region in the MISFET. , 800 [Å] ~
The thickness is 1000 [Å], and the thin film SOI substrate is used.

(3) Selective thermal oxidation (local oxide) using, for example, a Si ₃ N ₄ film as an oxidation resistant mask.
a field insulating film, that is, an element isolation insulating film (not shown) is formed on the surface of the p-type silicon semiconductor substrate 21B on the active layer side by applying the ion of silicon (LOCOS) method.

(4) By removing the Si ₃ N ₄ film or the like used when the inter-element isolation insulating film was formed, and then applying the thermal oxidation method, the thickness is, for example, 40 [Å]. SiO
_A gate insulating film 23 made of 2 is formed.

(5) Chemical vapor deposition (chemical)
By applying a vapor deposition (CVD) method, an n-type polycrystalline silicon film having a thickness of, for example, 1600 [Å] is formed.

(6) Resist process in lithography technology and reactive ion etching (reactive ion) using HBr as an etching gas
The n-type polycrystalline silicon film grown in the step (5) is patterned by applying the etching (RIE) method so that the gate electrode length is, for example, 0.25 [μm].
Forming the gate electrode 24.

(7) By applying the ion implantation method, the dose amount is set to 4 × 10 ¹³ [cm ⁻² ], the ion acceleration energy is set to 10 [keV], and the gate electrode 24 and the element isolation insulating film are set. Is used as a mask to implant As ions to form an n-type source region 25 and an n-type drain region 26 having a low impurity concentration.

(8) Activation annealing of the impurities implanted in the step (7) is performed. Generally, the activation anneal is
Since the characteristics of the MISFET deteriorate as the diffusion of the implanted impurities becomes deeper, only the necessary minimum is set.

In the present invention, the substrate is a thin film SOI, the thickness of the active layer side p-type silicon semiconductor substrate 21B is selected to the necessary minimum, and the impurity diffusion in the depth direction depends on the buried insulating film 22. It will be suppressed.

Therefore, activation annealing may be arbitrarily performed so that impurities are diffused laterally from the n-type source region 25 and the n-type drain region 26 to shorten the channel length as desired.

Assuming that the impurity diffusion coefficient is D and the annealing time is t, the impurity diffusion distance is 2√ (D
t), the temperature is set to 1000 [° C] and 2
When annealing is performed for [minutes], a short channel of about 0.1 [μm] is realized.

In the MISFET manufactured as described above, as can be seen from the drawing, the pn junction surface formed by the n-type source region 25 and the n-type drain region 26 is under the gate electrode 24. .

FIG. 2 is a cutaway side view of a main part of a MISFET in a process step for explaining the second embodiment of the present invention. The same symbols as those used in FIG. 1 are the same. They represent parts or have the same meaning.

In the figure, 25A is an n ⁺ -source region,
26A indicates an n ⁺ -drain region, and 27 indicates a side wall made of SiO ₂ .

In order to manufacture the MISFET of the second embodiment, after the step (8) in the first embodiment described above is completed, the next step may be successively performed.

(1) By applying the CVD method,
An insulating film made of SiO _{2 having a} thickness of, for example, about 1200 [Å] is formed.

(2) CHF ₃ + C as etching gas
By applying the RIE method using F ₄ , anisotropic etching is applied to the insulating film formed in the step (1) to form the side wall 27.

(3) By applying the ion implantation method, the dose amount is set to 4 × 10 ¹⁵ [cm ⁻² ], the ion acceleration energy is set to 30 [keV], the gate electrode 24, the side wall 27, As using the element isolation insulating film as a mask
Ions are implanted to form the n ⁺ − source region 25A and the n ⁺ − drain region 26A having a high impurity concentration.

(4) Activation annealing of the impurities implanted in the step (3) is performed. In addition, this annealing is n ⁺ −
It is performed under the condition that the diffusion ends of the source region 25A and the n ⁺ -drain region 26A do not reach the diffusion ends of the n-type source region 25 and the n-type drain region 26.

MISFET obtained according to the second embodiment
However, the so-called LDD structure is as can be seen from the figure.

FIG. 3 is a side sectional view showing the main part of the MISFET in the process steps for explaining the third embodiment of the present invention, and is the same as the symbols used in FIGS. 1 and 2. Symbols represent the same part or have the same meaning.

In the figure, reference numeral 28 denotes, for example, phospho-silicate glass (phospho-silicate glass) formed in the source region formation planned portion and the drain region formation planned portion.
1 shows a solid impurity source consisting of (lass: PSG). Note that FIG. 3 shows a state in which the diffusion of impurities has already ended and the n-type source region 25 and the n-type drain region 26 have been formed.

In order to manufacture the MISFET of the third embodiment, after the step (6) in the above-mentioned first embodiment is completed, the following steps may be successively performed.

(1) Etching gas is CHF ₃ + C
By applying the RIE method with F ₄ , the gate insulating film 23 is patterned using the gate electrode 24 as a mask.

(2) By applying the CVD method,
A PSG film having a thickness of, for example, about 5000 [Å] is formed.

(3) PSG formed in the step (2)
The n-type source region 25 and the n-type drain region 26 are subjected to a heat treatment for impurity diffusion using the film as a solid impurity source.
To form. It goes without saying that this heat treatment is carried out by setting diffusion conditions so that a desired channel length can be obtained.

(4) The PSG film formed in the step (2) is wet-etched by applying a usual lithography technique to form the source electrode 28S and the drain electrode 28D. In this case, not only the electrodes, but also the lead-out wirings connected to the electrodes may be formed.

According to the third embodiment, since the distance of impurity diffusion is accurately determined by temperature and time, the impurity distribution as designed can be obtained, which is advantageous for obtaining a required channel length.

The present invention is not limited to the above-described embodiments, and many other modifications can be realized.

For example, in each of the above-described embodiments, a so-called bonded substrate in which two silicon semiconductor substrates are bonded together with an embedded insulating film made of SiO ₂ interposed is used as the thin film SOI substrate. A silicon semiconductor substrate having a buried insulating film obtained by implanting oxygen ions into the substrate and then annealing at high temperature to recover the crystallinity, that is, SIMOX (separat).
An ion by implanted oxygen) substrate may be used.

In addition, in the first and second embodiments, when forming the source region and the drain region of low impurity concentration, oblique ion implantation with a large angle is performed, and one region below the gate electrode is formed from the beginning. Impurities may be implanted in advance in a portion, that is, in the vicinity of both ends of the channel.

Furthermore, in the third embodiment, PSG is used as the solid impurity source for forming the n-type source region and the n-type drain region, but this is arsenic silicate glass (ars).
In the case of substituting for ENO SILICATE GLASS (ASG) or forming a p-channel MISFET, borosilicate glass (borosilicate) is used.
glass: BSG) or boron phosphorus glass (bor)
ophosilicate glass: BP
SG) or the like can be used.

[0051]

In the method of manufacturing a MIS field effect semiconductor device according to the present invention, a gate electrode is formed on a thin film semiconductor active layer on an insulating film embedded in a semiconductor, and the gate electrode is used as a mask to remove impurities. Ion implantation is performed to form a source region and a drain region reaching the buried insulating film from the surface, and heat treatment is performed to diffuse and extend the source region and the drain region in the channel direction to shorten the channel length.

By adopting the above structure, even when a gate electrode having a limit gate electrode length that can be formed by the conventional technique is formed, it is compared with the normal channel length obtained by that. Since it is possible to realize a shorter channel length, it is possible to obtain a small-sized and high-speed switching MISFET which cannot be manufactured by the conventional technique. Therefore, the MIS field effect semiconductor device having improved performance can be highly integrated. be able to.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a main part of a MISFET in a process main part for explaining a first embodiment of the present invention.

FIG. 2 is a cutaway side view of an essential part of a MISFET in a process essential part for explaining a second embodiment of the present invention.

FIG. 3 is a side sectional view showing a main part of a MISFET in a process main part for explaining a third embodiment of the present invention.

FIG. 4 is a cutaway side view of a main part showing a conventional example of a bulk type MISFET having an LDD structure.

FIG. 5 is a cutaway side view of a main part showing a conventional example of a thin film SOI type MISFET having an LDD structure.

[Explanation of symbols]

21A supporting side silicon semiconductor substrate 21B active layer side p-type silicon made of a semiconductor substrate 22 SiO ₂ composed of the buried insulating film 23 SiO ₂ gate insulating film 24 gate electrode made of polycrystalline silicon 25 n-type source region 25A n ⁺ - source regions 26 n-type drain region 26A n ⁺ -drain region 27 side wall made of SiO ₂ 28 solid impurity source made of, for example, phosphosilicate glass

Claims (3)

[Claims] 1. A step of forming a gate electrode on a thin film semiconductor active layer on an insulating film embedded in a semiconductor, and then implanting impurity ions by using the gate electrode as a mask to form a buried insulating film from the surface. The MIS is characterized by including the steps of forming the reaching source and drain regions, and then performing heat treatment to diffuse and stretch the source and drain regions in the channel direction to shorten the channel length. Method for manufacturing field effect semiconductor device. 2. A step of forming a gate electrode on a thin film semiconductor active layer on an insulating film embedded in a semiconductor, and then, by implanting impurity ions using the gate electrode as a mask, the surface of the embedded insulating film is changed to the embedded insulating film. Forming a low-impurity concentration source region and a low-impurity concentration drain region to reach, then performing a heat treatment to diffuse and extend the source region and the drain region in the channel direction to shorten the channel length; Sides made of insulating film on the side of the electrode
Forming a wall, and then implanting impurity ions by using the gate electrode and the side wall as a mask to form a high impurity concentration source region and a high impurity concentration inside the low impurity concentration source region and the low impurity concentration drain region. And a step of forming the concentration drain regions corresponding to each other, the manufacturing method of the MIS field effect semiconductor device. 3. A step of forming a source region and a drain region by forming a solid impurity source on the portion where the source region is to be formed and on the portion where the drain region is to be formed, and then performing heat treatment to solid-solid diffuse the impurities. The method for manufacturing a MIS field effect semiconductor device according to claim 1, wherein the MIS field effect semiconductor device is included.