JPH07249702A - Nonvolatile semiconductor memory and its fabrication - Google Patents

Abstract

PURPOSE:To realize high density integration of memory cells in a noncontact cell type nonvolatile memory. CONSTITUTION:A first film is deposited on a tunnel oxide 2 and patterned into stripes extending perpendicularly to the longitudinal direction of channel of a memory transistor and then a diffusion layer 3 constituting a source-drain region is formed while being self-aligned with the first film. The first film is further patterned using a mask extending in the longitudinal direction of the channel to form a lower floating gate FGL and then a channel stop region 4 is formed while being self-aligned with the mask. Subsequently, a layer insulating film 5 is deposited between a word line and the diffusion layer 3 and a contact hole 5a is opened in the insulating film 5. A second film is then deposited on the entire surface and patterned thus forming an upper floating gate FGU connected with the lower floating gate FGL through the contact hole 5a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same, and is particularly suitable for application to a so-called contactless cell type nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art A contactless cell type non-volatile memory is known as a non-volatile memory suitable for increasing the integration density of memory cells (for example, US Pat. No. 43778).
18 and Japanese Patent Publication No. 63-42420). Figure 1 shows the equivalent circuit of this contactless cell nonvolatile memory.
2 shows. As shown in FIG. 12, in this contactless cell type nonvolatile memory, a word line (control gate) is used as a diffusion layer (bit / V _SS line) which constitutes a source region or a drain region of a memory transistor due to its cell architecture. Bit / V _SS i ~ Bit / V
_It needs to be formed across _SS l). On the other hand, in the non-volatile memory, it is necessary to apply a voltage of, for example, about 15 V to the word line when writing / erasing data to / from the memory transistor. Therefore, it is necessary to perform insulation isolation at the intersection of the word line and the diffusion layer forming the source region or the drain region of the memory transistor, which can withstand a voltage application of about 15V. For example, in FIG.
When writing to the memory transistor in the center of 2, it is necessary to set the potential of the bit / V _SS line Bit / V _SS k to 15 V and the potential of the word line W _q to 0 V, so this bit / V _SS line Bit / V _SS At the intersection of k and the word line W _q (the point indicated by a in FIG. 12), it is necessary to perform insulation isolation that can withstand a voltage application of 15V. Therefore, the method of forming the insulating film between the word line and the diffusion layer forming the source region or the drain region is a key point in forming the memory transistor.

Therefore, the above-mentioned US Pat. No. 4,377,818.
In the above publication, after forming an n ⁺ type diffusion layer forming a source region or a drain region, a thick oxide film for insulation isolation is selectively formed on this n ⁺ type diffusion layer by a thermal oxidation method, and thereafter, A technique for forming a tunnel oxide film and a floating gate is disclosed. On the other hand, in the above-mentioned Japanese Patent Publication 63-42420 discloses, formed in advance the Si ₃ N ₄ film on the floating gate, in a self-aligned manner with respect floating gate, forming the source region or the drain region n ⁺ After forming the type diffusion layer and the channel stop region, n 3 ⁺ is formed by using the Si ₃ N ₄ film formed on the floating gate as an oxidation mask.
A technique for selectively forming a thick oxide film for insulation separation on the mold diffusion layer by a thermal oxidation method is disclosed.

[0004]

However, the above-mentioned U.S. Pat. No. 4,377,818 and Japanese Patent Publication No. 63-424.
In any of the techniques disclosed in Japanese Patent Laid-Open Publication No. 20-1990, it is necessary to form a thick oxide film by a thermal oxidation method after forming the diffusion layer. Therefore, due to the thermal erasure during the thermal oxidation, the impurities in the diffusion layer are recovered. Diffusion occurs. The re-diffusion of the impurities causes an increase in the short channel effect of the memory transistor, which has been a problem in miniaturizing the memory transistor and thus increasing the integration density of the memory cell.

Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device capable of achieving high integration density of memory cells and a manufacturing method thereof.

[0006]

In order to achieve the above object, the first invention of the present invention is directed to a diffusion layer (3) constituting a source region or a drain region of a memory transistor.
In a nonvolatile semiconductor memory device having a structure in which word lines (W _p , W _q , W _r, etc.) are arranged above each other, they are connected to each other through a connection hole (5a) provided in an insulating film (5). The floating gate (FG _L , FG _U ) is formed by the first film (10) and the second film (14).

In one embodiment of the non-volatile semiconductor memory device according to the first aspect of the present invention, in the semiconductor substrate (1) of the first conductivity type, with respect to the first film (10) in the channel length direction of the memory transistor. A second conductive type diffusion layer (3) is provided in a self-aligned manner, and further, the first conductive layer is self-aligned with the first film (10) in a direction intersecting the channel length direction of the memory transistor. A channel stop region (4) of the mold is provided. Further, the insulating film (5) is provided so as to cover the semiconductor film (1) in the portion between the first film (10) and the first films (10) adjacent to each other. The first film (10) and the second film (14) are connected to each other through a connection hole (5a) provided in the insulating film (5) immediately above the film (10). Further, the second film (14) is formed in self-alignment with the word lines (W _p , W _q , W _r, etc.) in the direction crossing the channel length direction of the memory transistor.

In a typical embodiment of the nonvolatile semiconductor memory device according to the first invention, the first film (10) and the second film (14) are polycrystalline silicon films or refractory metal silicide films. is there.

A second aspect of the present invention has a structure in which word lines (W _p , W _q , W _r, etc.) are cross-arranged on a diffusion layer (3) forming a source region or a drain region of a memory transistor. In the method for manufacturing a nonvolatile semiconductor memory device having, a step of sequentially forming a tunnel oxide film (2) and a first film (10) for forming a floating gate on a first conductivity type semiconductor substrate (1), 1 film (1
0) using a stripe-shaped first mask (11) extending in a first direction on the semiconductor substrate (1), and performing self-patterning on the patterned first film (10). Forming a second conductivity type diffusion layer (3) by introducing impurities of the second conductivity type into the semiconductor substrate (1) in a consistent manner, and the patterned first film (10)
Is patterned by using a stripe-shaped second mask (12) extending in a second direction on the semiconductor substrate (1) intersecting the first direction to form a lower floating gate (FG _L ). Process and the second mask (1
2) Self-aligned with the semiconductor substrate (1) by introducing impurities of the first conductivity type into the semiconductor substrate (1) between the lower floating gates (FG _L ) adjacent to each other in the first direction. 1) forming a channel stop region (4) of the first conductivity type in the semiconductor substrate (1) between the lower floating gate (FG _L ) and the lower floating gates (FG _L ) adjacent to each other. Forming the insulating film (5) so as to cover the insulating film (5) immediately above the lower floating gate (FG _L ).
A step of forming a connection hole (5a) by selectively removing the metal, and a second step for forming a floating gate on the insulating film (5) and on the lower floating gate (FG _L ) of the connection hole (5a). Forming the second film (14), patterning the second film (14) using the stripe-shaped third mask (15) extending in the first direction, and at least the patterned first film (14). 2 membranes (1
4) a step of forming a coupling dielectric film (6) so as to cover the upper surface and the side surface of the same, and forming a third film (16) for forming a word line on at least the coupling dielectric film (6). Process and third film (16), coupling dielectric film (6) and patterned second film (14)
Are sequentially patterned using a stripe-shaped fourth mask (17) extending in the second direction to form a lower portion through the word line (W _p , W _q , W _r, etc.) and the connection hole (5a). And a step of forming an upper floating gate (FG _U ) connected to the floating gate (FG _L ).

In a typical embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the second invention, the first film (10) and the second film (14) are a polycrystalline silicon film or a refractory metal silicide. It is a film.

[0011]

According to the nonvolatile semiconductor memory device of the first aspect of the invention configured as described above, the insulating film for insulating and separating the word line and the diffusion layer constituting the source region or the drain region of the memory transistor from each other is provided. It can be formed without using a method of forming a thick oxide film by a thermal oxidation method after forming the diffusion layer forming the source region or the drain region. It is possible to prevent the short channel effect of the memory transistor from increasing due to the re-diffusion of impurities. As a result, the size of the memory transistor can be reduced, and the integration density of the memory cell can be increased.

Similarly, a step of forming a thick oxide film by a thermal oxidation method after forming a channel stop region and an insulating film for insulating isolation between a word line and a diffusion layer forming a source region or a drain region of a memory transistor. Therefore, the narrow channel effect of the memory transistor can be prevented from increasing due to the re-diffusion of impurities in the channel stop region. Therefore, also in this sense, it is possible to reduce the size of the memory transistor and further increase the integration density of the memory cell.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are designated by the same reference numerals.

FIG. 1 shows a contactless cell type nonvolatile memory according to an embodiment of the present invention. FIG. 1A is a plan view thereof, FIG. 1B is a sectional view taken along line BB of FIG. 1A, and FIG. FIG. 1B is a cross-sectional view taken along the line CC of FIG. 1A. An equivalent circuit of the contactless nonvolatile memory according to this embodiment is shown in FIG.

As shown in FIG. 1, in the contactless cell type non-volatile memory according to this embodiment, for example, the film thickness is approximately on a p-type semiconductor substrate 1 such as a p-type Si substrate having a resistivity of 10 Ωcm. A tunnel oxide film 2 such as a SiO ₂ film having a thickness of about 10 nm is provided. This on the tunnel oxide film 2 is provided in a matrix at predetermined intervals in a square-shaped lower floating gate FG _{direction L} are orthogonal to each other (the channel length direction and which in the direction perpendicular memory transistor). The lower floating gate FG _L is formed by a polycrystalline Si film, for example, n-type impurities such as P-doped.

Further, in the p-type semiconductor substrate 1, a predetermined number of n ⁺ -type diffusion layers 3 extending in one arrangement direction of the lower floating gates FG _L (direction perpendicular to the channel length direction of the memory transistor) are formed. It is provided in a self-aligned manner with respect to the lower floating gate FG _L in parallel to each other, and the other arrangement direction of the lower floating gate FG _L (channel length direction of the memory transistor). The n ⁺ -type diffusion layer 3 constitutes a bit line (drain line) or a bit / V _SS line which becomes a wiring (source line) for supplying the ground power supply voltage V _SS , and Bi shown in FIG.
It corresponds to t / V _SS i, Bit / V _SS j, Bit / V _SS k, and the like. Further, in the p-type semiconductor substrate 1 at a portion between the lower floating gates FG _L adjacent to each other in the one direction of arrangement of the lower floating gates FG _L (direction perpendicular to the channel length direction of the memory transistor), this one side For electrically separating the memory transistors adjacent to each other in the arrangement direction of
^{A +} type channel stop region 4 is provided.

Reference numeral 5 is a lower floating gate FG _L
And the lower floating gates FG _L adjacent to each other
An interlayer insulating film such as a SiO ₂ film provided so as to cover the tunnel oxide film 2 in a portion between the two is shown. Connection hole 5a is provided in a portion immediately above the lower floating gates FG _L of the interlayer insulating film 5. An upper floating gate FG _U is provided on the lower floating gate FG _L so as to be electrically connected to each other through the connection hole 5a. The upper floating gate FG _U is lower floating gate F
It is provided in a self-alignment manner with respect to a word line to be described later in the above one arrangement direction of G _L. This upper floating gate FG _U is lower floating gate FG _L
In the same manner as described above, a polycrystalline Si film doped with an n-type impurity such as P is formed. In this case, the entire upper floating gate FG _U and lower floating gate FG _L connected to each other act as a floating gate.

Reference numeral 6 denotes a coupling dielectric film having a three-layer structure of, for example, SiO ₂ film / Si ₃ N ₄ film / SiO ₂ film. The thickness of this coupling dielectric film 6 is SiO
It is, for example, about 20 nm in terms of _two films. The coupling dielectric film 6, so as to cover the both side surfaces of the upper floating gate FG _U the upper and lower floating gates FG _L of the other arrangement direction perpendicular upper floating on (the channel length direction of the memory transistor) gate FG _U It is provided in. W _p , W _q , W _r, etc. indicate word lines (control gates). These word lines W
_p , W _q , W _r, etc. are formed on the coupling dielectric film 6 by
Extending the lower floating gates FG _L of the other arrangement direction (channel length direction of the memory transistor) is provided. These word lines W _p , W _q , W _r
Are formed of, for example, a W polycide film having a structure in which a W silicide film is laminated on a polycrystalline Si film doped with an n-type impurity such as P.

In this case, the lower floating gate FG _L and the upper floating gate FG _U , which are connected to each other through the connection hole 5a provided in the interlayer insulating film 5, are stacked thereon with the coupling dielectric film 6 interposed therebetween. word lines, and one of the memory transistor is composed of the n ⁺ -type diffusion layer 3 provided in a self-aligned manner with respect to the lower floating gate FG _L on both sides of the lower floating gate FG _L.

Reference numeral 7 indicates a flattening insulating film such as a BPSG film. On the flat surface of the flattening insulating film 7, a metal wiring 8 made of, for example, an AlCuSi film is provided. This metal wiring 8 is provided for the purpose of preventing the resistance of the source line or the drain line (bit line) from becoming high only with the n ⁺ type diffusion layer 3, so that the lower floating Gate FG _L
A predetermined number of memory transistors arranged in one of the above arrangement directions are in contact with the n ⁺ type diffusion layer 3. Reference numeral 9 indicates a passivation film for surface protection.

Next, a method of manufacturing the contactless cell type non-volatile memory according to this embodiment constructed as described above will be described with reference to FIGS.
2A to 11A are plan views corresponding to FIG. 1A, and FIGS. 2B to 11B are FIGS. 2A to 11A, respectively.
2C to 11C are sectional views taken along the line BB of FIG. 2A to FIG. 11A, respectively.

In order to manufacture the contactless cell type nonvolatile memory according to this embodiment, first, as shown in FIG. 2, a p-type semiconductor substrate 1 such as a p-type Si substrate having a resistivity of 10 Ωcm is formed. For example, a tunnel oxide film 2 such as a SiO ₂ film having a film thickness of about 10 nm is formed by a thermal oxidation method.
Then, a polycrystalline Si film 10 for forming a lower floating gate is formed on the entire surface by, for example, a CVD method, and the polycrystalline Si film 10 is doped with an n-type impurity such as P by, for example, an ion implantation method. . Thereafter, a stripe-shaped resist pattern 11 having an inverted pattern shape of the n ⁺ type diffusion layer 3 is formed on the polycrystalline Si film 10 by lithography.

Next, as shown in FIG. 3, the polycrystalline Si film 10 is patterned by an etching method using the resist pattern 11 as a mask, and then the resist pattern 11 is used as a mask in the p-type semiconductor substrate 1, for example. N for forming a source region or a drain region by introducing an n-type impurity such as As by, for example, an ion implantation method
^{A +} type diffusion layer 3 is formed.

Next, after removing the resist pattern 11, as shown in FIG. 4, a stripe-shaped resist pattern 12 extending in the channel length direction of the memory transistor is formed again by lithography.

Next, as shown in FIG. 5, the polycrystalline Si film 10 is patterned by an etching method using the resist pattern 12 as a mask. Thus, the lower the floating gate FG _L consisting of rectangular polycrystalline Si film 10 in the memory transistor forming portion is formed.
Then, subsequently, using the resist pattern 12 as a mask, a p-type impurity such as B is introduced into the p-type semiconductor substrate 1 by, for example, an ion implantation method to form a p ⁺ -type channel stop region 4, for example. The dose of ion implantation of p-type impurities for forming the channel stop region 4 is selected sufficiently lower than the dose of ion implantation of n-type impurities for forming the n ⁺ -type diffusion layer 3. Therefore, the impurity concentration of the n ⁺ -type diffusion layer 3 in the portion where the p-type impurities are ion-implanted is only slightly decreased.

Next, after removing the resist pattern 12, as shown in FIG. 6, an interlayer insulating film 5 such as a SiO ₂ film is formed on the entire surface by, eg, CVD. Next, the lower floating gate FG of each memory transistor is formed on the interlayer insulating film 5 by lithography.
A resist pattern 13 having an opening of a predetermined shape is formed on the portion just above _L.

Next, as shown in FIG. 7, the interlayer insulating film 5 is etched using the resist pattern 13 as a mask to form a connection hole 5a.

Then, after removing the resist pattern 13, a polycrystalline Si film 14 for forming an upper floating gate is formed on the entire surface by, eg, CVD method as shown in FIG. An n-type impurity such as P is doped by, for example, an ion implantation method. Thereafter, a stripe-shaped resist pattern 15 extending in a direction perpendicular to the channel length direction of the memory transistor is formed on the polycrystalline Si film 14 by lithography.

Next, as shown in FIG. 9, the polycrystalline Si film 14 is patterned by an etching method using the resist pattern 15 as a mask. As a result, the polycrystalline Si film 14 is patterned in stripes extending in the direction perpendicular to the channel length direction of the memory transistor and separated from each other in the channel length direction.

Next, after removing the resist pattern 15, as shown in FIG. 10, a coupling having a three-layer structure of, for example, SiO ₂ film / Si ₃ N ₄ film / SiO ₂ film is formed on the entire surface by, eg, CVD method. The dielectric film 6 is formed. Then, a W polycide film 16 for forming a word line is formed on the coupling dielectric film 6 by, for example, the CVD method or the sputtering method. After this, this W polycide film 1
A stripe-shaped resist pattern 17 extending in the channel length direction of the memory transistor is formed on 6 by lithography.

Next, using the resist pattern 17 as a mask, the W polycide film 16 and the coupling dielectric film 6 are formed.
Then, the polycrystalline Si film 14 is sequentially patterned by an etching method. As a result, as shown in FIG. 11, word lines W _p , W _q , W _r and the like made of the patterned W polycide film 16 are formed. The upper floating gate FG _U consisting of the patterned polycrystalline Si film 14 is formed in self-alignment with the word lines in the direction perpendicular to the channel length direction of the memory transistor. This upper floating gate F
G _U is connected to the lower floating gate FG _L via a connection hole 5a formed in the interlayer insulating film 5.

Next, after removing the resist pattern 17, as shown in FIG. 1, a planarizing insulating film 7 such as a BPSG film is formed on the entire surface by, eg, CVD method to planarize the surface. After that, n is formed on the planarizing insulating film 7.
^A metal wiring 8 made of, for example, an AlCuSi film extending in parallel with the ⁺ type diffusion layer 3 is formed, and a passivation film 9 is further formed on the metal wiring 8 to complete an intended contactless cell type nonvolatile memory.

As described above, according to the contactless cell type non-volatile memory according to this embodiment, the n ⁺ type diffusion layer 3 (bit / V _SS line) and the word forming the source region or the drain region of the memory transistor are formed. a line, without forming a thick oxide film by a conventional thermal oxidation after the formation of the n ⁺ -type diffusion layer 3 as an insulating the interlayer insulating film 5 is formed by a CVD method after the lower floating gate FG _L form Can be separated. Therefore, n
It is possible to prevent the short channel effect of the memory transistor from increasing due to the re-diffusion of the n-type impurities in the ⁺ type diffusion layer 3, so that it is possible to reduce the size of the memory transistor and increase the integration density of the memory cell. it can. Similarly, since the n ⁺ -type diffusion layer 3 and the word line can be insulated and separated without the step of forming a thick oxide film by the thermal oxidation method after forming the channel stop region 4, It is possible to prevent the narrow channel effect of the memory transistor from increasing due to the re-diffusion of the p-type impurity. For this reason,
This also makes it possible to reduce the size of the memory transistor and further increase the integration density of the memory cell.

Further, the lower floating gate FG _L
And it is possible to carry out the floating gate and the word line consisting of the upper floating gate FG _U and by the formation of a coupling capacitor configured (control gate) independently of the channel length setting of the memory transistors, capacitance setting of the coupling capacitor There is also an advantage that the degree of freedom is large. Also in this case,
Since the capacitor to the upper floating gate FG _U memory the portion coupling the dielectric film 6 and the word line in the channel length direction perpendicular to both side surfaces be laminated of the transistors are formed, the effective coupling capacitor This is advantageous when the desired area is increased and it is desired to increase the capacitance of the coupling capacitor.

[0035]

As described above, according to the present invention, an insulating film for insulating and isolating a diffusion layer forming a source region or a drain region of a memory transistor from a word line is provided. Since it can be formed without using a method of forming a thick oxide film by a thermal oxidation method after forming a diffusion layer to be formed, it is possible to reduce the size of a memory transistor and achieve high integration density of a memory cell. it can. Similarly, the diffusion layer forming the source region or the drain region of the memory transistor and the word line can be insulated and separated without performing the step of forming a thick oxide film by the thermal oxidation method after forming the channel stop region. The size of the memory transistor can be reduced, and the density of the memory cell can be further increased.

[Brief description of drawings]

FIG. 1 is a plan view showing a contactless cell non-volatile memory according to an embodiment of the present invention, a sectional view taken along the line BB and a sectional view taken along the line CC.

FIG. 2 is a plan view for explaining a method of manufacturing a contactless cell nonvolatile memory according to an embodiment of the present invention, a cross-sectional view taken along line BB and a cross-section taken along line CC of FIG. It is a figure.

FIG. 3 is a plan view for explaining a method of manufacturing a contactless cell nonvolatile memory according to an embodiment of the present invention, a cross-sectional view taken along line BB and a cross-section taken along line CC of FIG. It is a figure.

FIG. 4 is a plan view for explaining a method of manufacturing a contactless cell non-volatile memory according to an embodiment of the present invention, a sectional view taken along the line BB and a sectional view taken along the line CC. It is a figure.

FIG. 5 is a plan view for explaining a method of manufacturing a contactless cell nonvolatile memory according to an embodiment of the present invention, a cross-sectional view taken along line BB and a cross-section taken along line CC of FIG. It is a figure.

FIG. 6 is a plan view for explaining a method of manufacturing a contactless cell type nonvolatile memory according to an embodiment of the present invention, a sectional view taken along the line BB and a sectional view taken along the line CC. It is a figure.

FIG. 7 is a plan view for explaining a method of manufacturing a contactless cell type nonvolatile memory according to an embodiment of the present invention, a sectional view taken along the line BB and a sectional view taken along the line CC. It is a figure.

FIG. 8 is a plan view for explaining a method of manufacturing a contactless cell type nonvolatile memory according to an embodiment of the present invention, a sectional view taken along the line BB and a sectional view taken along the line CC. It is a figure.

FIG. 9 is a plan view for explaining a method of manufacturing a contactless cell non-volatile memory according to an embodiment of the present invention, a sectional view taken along the line BB and a sectional view taken along the line CC. It is a figure.

FIG. 10 is a plan view for explaining a method of manufacturing a contactless cell nonvolatile memory according to an embodiment of the present invention, a sectional view taken along the line BB and a sectional view taken along the line CC. It is a figure.

FIG. 11 is a plan view for explaining a method of manufacturing a contactless cell nonvolatile memory according to an embodiment of the present invention, a sectional view taken along the line BB and a sectional view taken along the line CC. It is a figure.

FIG. 12 is an equivalent circuit diagram of a contactless cell nonvolatile memory.

[Explanation of symbols]

1 p-type semiconductor substrate 2 tunnel oxide film 3 n ⁺ type diffusion layer 4 channel stop region 5 interlayer insulating film 5a connection hole 6 coupling dielectric film 10, 14 polycrystalline Si film 11, 12, 13, 15, 17 resist pattern 16 Polycide film FG _L Lower floating gate FG _U Upper floating gate W _p , W _q , W _r Word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (8)

[Claims] 1. A non-volatile semiconductor memory device having a structure in which word lines are cross-arranged on a diffusion layer which constitutes a source region or a drain region of a memory transistor, and is connected to each other through a connection hole provided in an insulating film. A non-volatile semiconductor memory device in which a floating gate is formed by the first film and the second film thus formed. 2. A semiconductor substrate of the first conductivity type, wherein the first transistor is formed in the channel length direction of the memory transistor.
2. The nonvolatile semiconductor memory device according to claim 1, wherein the diffusion layer of the second conductivity type is provided in a self-aligning manner with respect to the film of FIG. 3. A first-conductivity-type channel stop region is provided in a first-conductivity-type semiconductor substrate in self-alignment with the first film in a direction intersecting a channel length direction of the memory transistor. The non-volatile semiconductor memory device according to claim 1, wherein 4. The insulating film is provided so as to cover the first film and a part of the semiconductor substrate between the first films adjacent to each other, and the part of the insulating film is provided directly above the first film. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the first film and the second film are connected to each other through the connection hole provided in the insulating film. 5. The non-volatile semiconductor according to claim 1, wherein the second film is formed in self-alignment with the word line in a direction intersecting a channel length direction of the memory transistor. Storage device. 6. The non-volatile semiconductor memory device according to claim 1, wherein the first film and the second film are polycrystalline silicon films or refractory metal silicide films. 7. A method for manufacturing a non-volatile semiconductor memory device having a structure in which word lines are cross-arranged on a diffusion layer forming a source region or a drain region of a memory transistor, wherein a tunnel is formed on a semiconductor substrate of a first conductivity type. A step of sequentially forming an oxide film and a first film for forming a floating gate; and patterning the first film using a stripe-shaped first mask extending in a first direction on the semiconductor substrate. Forming a diffusion layer of the second conductivity type by introducing impurities of the second conductivity type into the semiconductor substrate in a self-aligned manner with respect to the patterned first film; The patterned first film is patterned using a stripe-shaped second mask extending in a second direction on the semiconductor substrate intersecting the first direction. Forming a lower floating gate by bridging, the first by introducing a first conductivity type in a self-aligning manner in the semiconductor substrate an impurity with respect to the second mask
Forming a channel stop region of the first conductivity type in the semiconductor substrate in a portion between the lower floating gates adjacent to each other in the direction of, and a portion between the lower floating gate and the lower floating gates adjacent to each other. Forming an insulating film so as to cover the semiconductor substrate; forming a connection hole by selectively removing the insulating film directly above the lower floating gate; A second floating gate is formed on the lower floating gate in the connection hole portion.
The step of forming the film, the step of patterning the second film using the stripe-shaped third mask extending in the first direction, and at least the upper surface of the patterned second film. And a step of forming a coupling dielectric film so as to cover the side surface, a step of forming a third film for forming a word line on at least the coupling dielectric film, the third film, the coupling The dielectric film and the patterned second film are sequentially patterned using a stripe-shaped fourth mask extending in the second direction to form the lower portion through the word line and the connection hole. A step of forming an upper floating gate connected to the floating gate, the method for manufacturing a nonvolatile semiconductor memory device. 8. The method of manufacturing a nonvolatile semiconductor memory device according to claim 7, wherein the first film and the second film are polycrystalline silicon films or refractory metal silicide films.