JPH07249689A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable memory cell structure which can secure enough capacity even for the further reduction of the occupied are a of a memory cell by interposing a pad electrode consisting of a conductor layer whose height from an electrode is made higher than a storage node electrode. CONSTITUTION:A bit line 14 is made in the layer above a capacitor, and besides the bit line 14 is connected to the other of source or drain regions 6a and 6b through a pad electrode 10P being shelved up to the upper side of a storage electrode 10. Since the pad electrode 10P higher than the storage electrode 10 is made this way, even if the capacitor is made higher, a pad electrode 10P further higher than it can be made. Hereby, the retreat of the plate at processing of a plate electrode can be advanced not only in lateral direction but also in vertical direction, so the processing keeping such a margin that it is separated enough from the bit line contact area and that it does not expose the adjacent storage node electrode 10 can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a semiconductor memory device (DRA).
M) and MOSFETs and capacitors.

[0002]

2. Description of the Related Art Semiconductor integrated circuits such as DRAMs are becoming more and more integrated due to advances in microfabrication technology, and accordingly, the area of capacitors for storing information (charges) is also miniaturized. .

With the miniaturization of the capacitor area, the capacity of the capacitor is reduced, and as a result, the contents of the memory are erroneously read out, or a soft error in which the contents of the memory are destroyed by α rays or the like becomes a problem.

As one of the methods for solving such a problem and achieving high integration and large capacity, a MOS capacitor is laminated on a memory cell region and one electrode of the capacitor and a semiconductor substrate are formed. A memory cell structure called a stacked memory cell, in which one electrode of the formed switching transistor is electrically connected to substantially expand the occupied area of the capacitor and increase the capacitance of the MOS capacitor. Is proposed.

In such a structure, the storage node electrode can be expanded to above the element isolation region, and the thickness of the storage node electrode can be increased so that the side wall thereof can be used as a capacitor. It can be increased several times more than the structure. Further, the diffusion layer of the storage node portion is only the diffusion layer region under the storage node electrode, and the area of the diffusion layer that collects the charges generated by the α rays is extremely small, and has a cell structure that is resistant to soft errors.

However, also in such a stacked memory cell structure DRAM, the area occupied by the memory cell is reduced and the area of the flat portion of the storage node electrode is reduced as the miniaturization of the device is advanced due to higher integration. In order to further reduce the size and ensure a sufficient capacitor capacity, it is required to increase the effective height of the storage node electrode. For this reason, the wiring contact to be formed after this must be formed deeply, and it is easy to cause a short circuit with the lower layer wiring due to overetching, or the contact itself can be formed, but some kind of embedding technology must be used. There is a problem that disconnection of wiring material is likely to occur. Therefore, as shown in FIG. 11, there is a proposal that a pad electrode made of a body layer formed in the same step as the storage node electrode is formed in a subsequent contact formation region (bit line contact portion in this figure). . However, in this case, since the storage node and the pad are adjacent to each other and are formed at the same height, there are the following problems. (1) At the time of processing a plate electrode, if the pad electrode is made to be sufficiently away from the bit line contact surface, the capacitance will be reduced if a part of the adjacent storage node electrode is exposed. (2) Further, as shown in FIG. 12, when the storage node electrode has a crown structure to increase the capacitance, the pad also has a crown structure, which makes it difficult to form a bit line contact with the pad. (3) In particular, in the case of an open bit line type DRAM cell such as a NAND type DRAM, if the wiring resistance of the plate electrode increases, large noises will occur during writing and reading, and erroneous data reading will occur. Is a problem.

Therefore, the plate electrode needs to be formed in self alignment with the bit line contact region.
That is, when viewed from above, it is desirable that the plate electrode pattern having a hole only in the bit line contact portion is formed in a single plate shape in the cell portion.

Such a state is possible even in the prior art FIG. 10, but this is because the height of the storage node electrode is sufficiently high. For example, if the use of the high-dielectric insulating film provides a capacitor capacitance even with a sufficiently thin storage node electrode of about 0.1 μm, it is difficult to leave the plate electrode around the bit line contact pad.

[0009]

SUMMARY OF THE INVENTION The present invention has been considered in view of the above-mentioned circumstances of the prior art, and is capable of ensuring a sufficient capacitor capacity when the area occupied by the memory cell is further reduced. Another object of the present invention is to provide a memory cell structure capable of reducing the wiring resistance of the plate electrode and alleviating the problem of noise.

[0010]

In order to achieve the above object, the present invention interposes a pad electrode made of a conductor layer having a height higher than that of the storage node electrode.

[0011]

According to the present invention, since the pad electrode having a height higher than that of the storage node electrode is formed, it is possible to simultaneously form a pad electrode higher than that even if the capacitor is made higher. Therefore, the plate retreat during plate electrode processing can be advanced not only in the horizontal direction but also in the vertical direction, so that (1) a margin that is sufficiently away from the bit line contact region and does not expose the adjacent storage node electrode. It can be processed. Further, even if the capacitor is made high, the contact may be formed on the pad electrode that is shelved above the capacitor, so that the bit line contact can be easily formed. In addition, the pad electrode can be used not only in the bit line but also in the peripheral circuit portion. Therefore, the contact of the peripheral circuit can be formed on the pad electrode which is shelved to the same extent as the capacitor, so that the contact can be formed. It will be easy. Further, by making the height of the pad sufficiently high, it is possible to leave the plate electrode on the side wall of the pad with a sufficient film thickness, for example, higher than the height of the storage node electrode. The wiring resistance is significantly reduced, and the problem of noise due to an increase in the plate electrode wiring resistance can be prevented in an open bit line type cell such as a NAND type DRAM. This is particularly effective when the film thickness of the storage node electrode is sufficiently reduced by using a high dielectric film, for example, and by increasing the height of the pad electrode, the low resistance of the plate electrode can be maintained.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1A and 1B are a plan view showing two bits adjacent to each other in the bit line direction of a DRAM having a stacked memory cell structure according to the first embodiment of the present invention, and a sectional view taken along the line AA '. is there.

In this DRAM, a capacitor is used for the bit line 1.
In the structure formed under 4, the pad electrode 10P for the bit line is formed at the same time as the storage node electrode 10 is formed, and the substantial depth of the bit line contact is made shallow. Is.

That is, an n-type diffusion layer forming a source / drain region is formed in an activation region separated by an element isolation insulating film 2 formed in a p-type silicon substrate 1 having a specific resistance of about 5 Ω · cm. A MOSFET is constituted by 6a, 6b and a gate electrode 5 formed between these source / drain regions via a gate insulating film 4, and contacts the n ⁻ type diffusion layer 6b via a storage node contact 8. Storage node electrode 10
Are formed, and the capacitor insulating film 11 is interposed between the plate electrode 12 and the upper layer plate electrode 12 to form a capacitor. Then, the first bit line contact 13a formed simultaneously with the formation of the storage node contact 8
A pad electrode 10P is formed so as to contact the n ⁻ type diffusion layer 6a exposed therein, and a bit line 14 is formed via a second bit line contact 13b formed in the interlayer insulating film 7b.

The gate electrodes 5 are continuously arranged in one direction of the memory array to form word lines. Next, a method of manufacturing this DRAM will be described with reference to the drawings.

FIG. 2 is a diagram for explaining the manufacturing process of this DRAM. In each of the drawings, (a) and (b) are plan views showing two bits adjacent to each other in the bit line direction, A- thereof. It is an A'cross section figure. The DRAM used here is a pad electrode 1 formed simultaneously with the storage node electrode 10.
It is almost the same as the DRAM described in the description of the conventional art, except that 0P is formed higher than the storage node electrode 10.

First, an element isolation insulating film 2 and a p-type diffusion layer 3 for a punch-through stopper are formed on the surface of a p-type silicon substrate 1 having a specific resistance of about 5 Ω · cm by a normal LOCOS method, and then heat is applied. A gate insulating film 4 made of a silicon oxide film with a film thickness of about 10 nm is formed by an oxidation method. Then, a polycrystalline silicon film as a gate electrode material is deposited on the entire surface to a thickness of about 150 nm, and LPCVD is performed on the upper layer.
An insulating film such as a silicon oxide film with a film thickness of 100 to 30
Then, the gate electrode 5 and the insulating film 7u on the gate are patterned at the same time by using photolithography technology and anisotropic etching technology. Here, as the insulating film on the gate electrode, a silicon nitride film or a composite film of a silicon nitride film and a silicon oxide film may be used. The silicon nitride film is more effective than the silicon oxide film in preventing the short circuit between the gate electrode and the contact wiring because it has a stronger etching resistance against the treatment using the dilute HF solution performed during the contact formation and the wiring formation. Become. Then, As or P ions are ion-implanted using the gate electrode 5 as a mask to form the source / drain regions 6a and 6b made of n ⁻ type diffusion layers, and MOSFETs as switching transistors are formed. The depth of this diffusion layer is, eg, about 150 nm. Thereafter, thermal oxidation is performed if necessary to improve the breakdown voltage of the gate insulating film, and an insulating film made of a silicon oxide layer or a silicon nitride layer with a thickness of about 100 nm or less is deposited on the entire surface by a CVD method. The entire surface is etched by the reactive ion etching method, and the side wall insulating film 7s is left on the side surface of the gate electrode 5 in a self-aligned manner. Similar to the gate insulating film, a silicon nitride film is used as the sidewall insulating film 7s, so that the breakdown voltage can be further improved.

Thereafter, storage node contact 8 and first bit line contact 13a are formed on the surfaces of n ⁻ diffusion layers 6a and 6b exposed from side wall insulating film 7s and upper insulating film 7u, respectively. And these n ^-
With the exposed surfaces of the diffusion layers 6a and 6b, a polycrystalline silicon film having a thickness of about 400 to 1000 nm is deposited on the entire surface, phosphorus or arsenic is doped into this, and a pattern is formed by photolithography and reactive ion etching to form a storage node electrode. 10 and the pad electrode 10P are formed. Thus, forming the storage node electrode without forming the interlayer insulating film shortens the process. At this time, the contact region of the peripheral circuit portion may be simultaneously shelved by the pad of the storage node electrode.

Alternatively, in the peripheral circuit portion, the side wall insulating film 7s in the previous process is left on the entire surface to serve as a stopper during the processing of the storage node electrode so as to cover the cell portion after or before the processing of the storage node electrode. You may remove it using a different resist pattern as a mask. Alternatively, the conventional method of forming the storage node after forming the interlayer insulating film and then forming the storage node contact may be used. Thereafter, as shown in FIG. 2, RIE is performed using a resist pattern (pad protection pattern) 20 for protecting the bit line contact forming pad electrode 10P, and the height of the storage node electrode 10 is adjusted to the pad electrode 10.
Lower than P. Then, the film thickness is 10n by the CVD method.
800 to 900 after depositing a silicon nitride film of about m or less
Oxidation is performed in a water vapor atmosphere at a temperature of 30 ° C. for about 30 minutes to form a silicon oxide film, thereby forming a capacitor insulating film 11 having a two-layer structure of a silicon nitride film and a silicon oxide film. Further, a polycrystalline silicon film is deposited on this upper layer, and after doping, the plate electrode 12 is patterned by the photolithography technique and the isotropic dry etching technique.
Here, isotropic dry etching is used as etching because consideration is given to the withstand voltage of the capacitor insulating film due to the small etching damage. Etching or the like may be used. The capacitor insulating film 11 is also formed on the sidewall of the pad electrode 10P. This insulating film 1
No. 1 can secure a sufficient dielectric strength between the pad electrode 10P and the plate electrode 12 and can be made sufficiently thinner than using an interlayer insulating film such as a CVD oxide film, so that higher integration can be achieved. is there. In any case, since the pad electrode 10P is higher than the storage node electrode 10, the plate electrode can be left sufficiently thick in self-alignment with the pad electrode 10P, and the adjacent storage node 10 is exposed by plate processing. It has a structure that does not cause problems.

Thereafter, a second bit line contact 13b is formed so as to contact the pad electrode 10P.
If necessary, an insulating film for preventing a short circuit between the bit line 14 and the plate electrode 12 may be formed on the sidewall of the second bit line contact 13b.

By forming in this way, since the pad electrode 10P is shelved up to the height of the storage node electrode 10, the bit line contact can be formed very easily. In the processing for reducing the height of the storage node electrode described above, the storage node electrode may have a multi-layered structure in order to improve processing accuracy. That is, for example, the lower side may be As-doped polycrystalline silicon and the upper side may be P-doped polycrystalline silicon to detect the boundary between the two and stop etching.

Next, a second embodiment of the present invention will be described. In this example, the main structure is similar to that of the first embodiment, but as shown in FIG. 3, the storage node electrode is composed of the flat portion 10 and the protruding portion 9 in order to increase the capacitor area. However, the pad electrode is the flat portion 10P,
It is characterized in that it is composed of a side wall portion 9P formed at the same time as the protruding portion 9 and a flat portion TOP, and the bit line contact is formed so as to make contact with the flat portion 10P '.

Next, a method of manufacturing this DRAM will be described with reference to FIGS. First, similar to the first embodiment, element isolation is performed, a gate electrode is formed, and in a later step, a stopper film 15 for removing the interlayer film is deposited, and a flat interlayer film 16 is formed.

For example, when the interlayer film 12 is formed by reflowing a BPSG film and is removed with an NH ₄ F solution in a later step, the stopper film 11 is preferably a SiN film or the like. Then, after forming a storage node contact and a contact 13 as a pad contact, a polycrystalline silicon film 10 of about 100 nm is deposited on the entire surface to form a flat portion of the storage node electrode and a flat portion of the pad electrode. After depositing a silicon oxide film 17 with a thickness of about 700 nm by a CVD method, further depositing a polycrystalline silicon film (TOP) with a thickness of about 400 nm on the silicon oxide film 17, and then performing the above step 3 in a region where a storage node electrode and a pad electrode are formed.
Leave the layer film (FIG. 4). Here, the TOP of the storage node electrode portion is removed by etching with the pad protection pattern 20 (FIG. 5). Although all are removed, the film is thinned to such an extent that overetching when forming the storage node electrode 9 thereafter is eliminated. Then, a polycrystalline silicon film 9 to be a protrusion is further formed to a film thickness of 1
Deposit about 00 nm.

Then, both of the polycrystalline silicon are etched by anisotropic etching, and the bottom and side walls of the silicon oxide film 17 of the storage node electrode and the side wall of TOP of the pad electrode part, the bottom and side walls of the silicon oxide film 17 are etched. The polycrystalline silicon film 9 is made to remain only in the portion (FIG. 6).

Then, using an ammonium fluoride solution or the like,
The silicon oxide film 17 is removed to complete the storage node electrode and the pad electrode. In this embodiment, the interlayer film 16 is also removed at this time. At this time, the pad electrode is in the form of box-shaped polycrystalline silicon filled with silicon oxide 17.

After that, the capacitor insulating film 11 and the plate electrode 12 are deposited (FIG. 7). Then, a plate electrode is formed, an interlayer insulating film is further formed, and a bit line contact 10b is formed. After this, the bit line is formed, and as shown in FIG.
The DRAM shown in is completed. In this embodiment, the plate is previously patterned and removed, and the bit line contact is directly formed on the pad. However, the plate electrode under the bit line contact 13b is left as a stopper,
After stopping the contact etching of the interlayer film at the plate, remove the exposed plate and form an oxide film etc. on the contact side wall to prevent the short circuit between the plate and the bit line and to make contact on the pad. May be.

In this way, the formation of the bit line contact is extremely easy to form a DRAM having a large capacitance. In this embodiment, since the pattern size of the storage node is increased by the film thickness of the protruding portion 9, there is no plate processing margin, but since the pad is formed high, the plate processing that covers the storage node is performed. Is easy. Also, the pad has a box shape. At this time, since the area of the pad is expanded by the film thickness of the polycrystalline silicon formed on the side wall, the contact margin can be increased as compared with the first embodiment and the like.

Next, a third embodiment of the present invention will be described. In this example, as shown in FIG. 8, it is basically similar to the second embodiment. However, by making the height of the pad electrode sufficiently higher than the storage node electrode,
The etching surface of the plate electrode is formed to be higher than the storage electrode, so that the surface of the storage node is hard to be exposed. However, the memory cell pattern is a NAND-DRAM pattern. In the NAND-DRAM, a plurality of cells are connected in series, but basically, it is difficult to apply the folded bit line method known in the conventional DRAM. Therefore, as shown in FIG. 8, the open bit method is used. Has become.
This makes the plate processing more difficult than in the normal case.

The pattern of the plate is a line-shaped pattern 12 for exposing the pad electrode for forming the bit line contact as shown in FIG. This pattern is a lithographically preferable pattern, but as a result, the plate electrode is separated for each bit line contact portion in the bit line direction. Or, it becomes a prosperous state with almost a thin film. This increases the resistance of the plate electrode, and noise associated therewith may lead to insufficient cell operation margin.

With this structure, since the etching surface of the plate is located higher than the height of the adjacent storage node, even if a linear pattern is processed, for example, as shown in FIG. 8C. , The plate 12 can be sufficiently left between the pads, so that the plate spreads like a plate. With this configuration, it is possible to avoid the problem of noise that accompanies an increase in the resistance of the plate. Therefore, the structure of such a high pad is particularly effective for the cell structure of the NAND-DRAM.

FIG. 9 shows an embodiment in which a high dielectric film is used for the capacitor insulating film. In this case, even if the storage node electrode is as thin as 0.1 μm, a sufficient capacitor capacity can be obtained. However, at this time, if the conventional pad is formed, the height of the pad becomes 0.1 μm, and if the plate electrode is processed, it becomes difficult to leave the plate electrode around the pad by overetching. However, in the present embodiment. , The pad is high enough so there is no problem.

[0033]

According to the semiconductor device of the present invention, it is easy to manufacture, and even when the scale cell occupying area is further reduced, a sufficient capacitor capacity can be secured, and proper processing of the plate can be easily realized. it can.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a DRAM showing a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the DRAM showing the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a DRAM showing a second embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of a DRAM showing a second embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of a DRAM showing a second embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of a DRAM showing a second embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of a DRAM showing a second embodiment of the present invention.

FIG. 8 is a configuration diagram of a DRAM showing a third embodiment of the present invention.

FIG. 9 is a configuration diagram of a DRAM showing a fourth embodiment of the present invention.

FIG. 10 shows a fifth embodiment.

FIG. 11 is a configuration diagram showing a conventional DRAM.

FIG. 12 is a configuration diagram showing a conventional DRAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate 4 ... Gate insulating film 5 ... Gate electrode 6a ... N ^- type diffusion layer 6b ... N ^- type diffusion layer 8 ... Storage node contact 10 ... Storage node electrode 10P ... Pad electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (3)

[Claims] 1. A MOSFET formed in a semiconductor substrate
And connected to one of the source or drain regions of the MOSFET via a storage node contact,
A memory cell is formed by a storage node electrode formed so as to extend onto the gate electrode, a capacitor composed of a capacitor insulating film, and a plate electrode, and a bit line is formed so as to be connected to the other of the source and drain regions. Wherein the bit line is formed in an upper layer of the capacitor, and the bit line has the source or drain via a pad electrode that is shelved above the storage node electrode. A semiconductor device characterized by being connected to the other of the regions. 2. The semiconductor device according to claim 1, wherein a capacitor insulating film is formed on a sidewall of the pad electrode. 3. The semiconductor device according to claim 1, wherein the pad electrode is in the same layer as the storage node electrode.