JPH07249628A - Method of forming wiring - Google Patents

Method of forming wiring

Info

Publication number
JPH07249628A
JPH07249628A JP6067689A JP6768994A JPH07249628A JP H07249628 A JPH07249628 A JP H07249628A JP 6067689 A JP6067689 A JP 6067689A JP 6768994 A JP6768994 A JP 6768994A JP H07249628 A JPH07249628 A JP H07249628A
Authority
JP
Japan
Prior art keywords
connection hole
alloy layer
substrate
wiring
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6067689A
Other languages
Japanese (ja)
Inventor
Satoshi Hibino
三十四 日比野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Priority to JP6067689A priority Critical patent/JPH07249628A/en
Publication of JPH07249628A publication Critical patent/JPH07249628A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve step coverage of Al or Al alloy layer. CONSTITUTION:After an insulating film 12 covering a part to be connected is formed on the surface of a semiconductor substrate 10, a connection hole 12A corresponding with the part to be connected is formed. An Al or Al alloy layer 14 is formed on the upper surface of a substrate via a barrier metal layer 13 by a sputtering method. The substrate temperature during the sputtering process is set at 50-200 deg.C. After that, annealing process is continuously performed at 350-450 deg.C in a reduced pressure atmosphere. Hence the covering state of the Al or Al alloy layer 14 comes to adapt to the step-difference of a connection hole 12A. As another method, the substrate temperature during the sputtering process is set at 350-450 deg.C, and the annealing process may be abolished. After that, wiring layers are obtained by patterning the wiring material layers 13, 14.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、Al又はAl合金層
等を含む配線の形成法に関し、特にスパッタ処理中又は
その後に350〜450℃の熱処理によりAl又はAl
合金層の段差被覆性を改善したものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring containing an Al or Al alloy layer and the like.
The step coverage of the alloy layer is improved.

【0002】[0002]

【従来の技術】従来、LSI等の半導体装置の配線形成
法としては、配線を構成するAl又はAl合金層をスパ
ッタ法で被着するものが知られている。
2. Description of the Related Art Conventionally, as a wiring forming method for a semiconductor device such as an LSI, there is known a method of depositing an Al or Al alloy layer constituting a wiring by a sputtering method.

【0003】図6は、標準的なスパッタ工程を示すもの
で、半導体基板10の表面を覆う絶縁膜12に接続孔を
形成した後、基板上面には50〜200℃の基板温度に
てスパッタ処理によりAl又はAl合金層14を被着す
る。
FIG. 6 shows a standard sputtering process. After forming a connection hole in the insulating film 12 covering the surface of the semiconductor substrate 10, the upper surface of the substrate is subjected to a sputtering process at a substrate temperature of 50 to 200.degree. The Al or Al alloy layer 14 is deposited by.

【0004】図7は、高温スパッタ工程を示すもので、
接続孔形成後、基板上面にはAl又はAl合金が流動す
るような高い基板温度にてスパッタ処理によりAl又は
Al合金層14を被着する。
FIG. 7 shows a high temperature sputtering process.
After forming the connection holes, the Al or Al alloy layer 14 is deposited on the upper surface of the substrate by sputtering at a high substrate temperature such that Al or Al alloy flows.

【0005】[0005]

【発明が解決しようとする課題】図6のスパッタ処理に
よると、接続孔のサイズが小さくなるにつれて接続孔の
下方側壁部Pの被覆性が劣化する不都合がある。
According to the sputtering process of FIG. 6, there is a disadvantage that the coverage of the lower side wall portion P of the connection hole deteriorates as the size of the connection hole becomes smaller.

【0006】また、図7のスパッタ処理によると、微細
な接続孔の埋め込みも可能になるが、接続孔の開口端部
Qで膜厚が薄くなる不都合がある。これは、接続孔の容
積に対し、供給するAlの量が限られているためで、密
集配置の接続孔ほどその傾向が強い。また、温度が高い
ため、上層配線に対する接続孔では使えない。
Further, according to the sputtering process of FIG. 7, it is possible to embed a fine connection hole, but there is a disadvantage that the film thickness is thin at the opening end Q of the connection hole. This is because the amount of Al supplied is limited with respect to the volume of the connection holes, and the denser the connection holes, the stronger the tendency. Moreover, since the temperature is high, it cannot be used in a connection hole for an upper layer wiring.

【0007】この発明の目的は、Al又はAl合金層の
段差被覆性を改善した新規な配線形成法を提供すること
にある。
An object of the present invention is to provide a novel wiring forming method with improved step coverage of an Al or Al alloy layer.

【0008】[0008]

【課題を解決するための手段】この発明に係る配線形成
法は、基板の表面に被接続部を覆って絶縁膜を形成した
後、該絶縁膜に該被接続部に対応した接続孔を形成する
工程と、前記接続孔及び前記絶縁膜を覆ってAl又はA
l合金層を被着する工程と、前記Al又はAl合金層を
350〜450℃の温度でアニール処理して前記接続孔
の段差に順応した被覆状態にする工程と、前記Al又は
Al合金層を前記アニール処理の後でパターニングして
配線層を形成する工程とを含むものである。
According to the wiring forming method of the present invention, an insulating film is formed on a surface of a substrate so as to cover a connected portion, and then a connection hole corresponding to the connected portion is formed in the insulating film. And a step of covering the connection hole and the insulating film with Al or A
a step of depositing an Al alloy layer, a step of annealing the Al or Al alloy layer at a temperature of 350 to 450 ° C. to provide a covering state adapted to the step of the connection hole, and the Al or Al alloy layer. And a step of forming a wiring layer by patterning after the annealing treatment.

【0009】このような配線形成法にあっては、スパッ
タ処理中の基板温度を350〜450℃の範囲内に設定
することによりAl又はAl合金層の被覆状態を接続孔
の段差に順応した状態とし、スパッタ処理後のアニール
処理をやめてもよい。
In such a wiring forming method, by setting the substrate temperature during the sputtering process within the range of 350 to 450 ° C., the covering state of the Al or Al alloy layer is adapted to the step difference of the connection hole. Therefore, the annealing process after the sputtering process may be stopped.

【0010】[0010]

【作用】この発明の方法によれば、スパッタ処理中又は
その後に350〜450℃の熱処理を行なうようにした
ので、Al又はAl合金層は、例えば図3の層14で示
すように接続孔の段差に順応した被覆状態となる。すな
わち、Al又はAl合金層は、図6で示したように接続
孔の下方側壁部で薄くなったり、図7で示したように接
続孔の開口端部で薄くなったりすることがなくなる。
According to the method of the present invention, since the heat treatment at 350 to 450 ° C. is performed during or after the sputtering process, the Al or Al alloy layer is formed of the contact hole as shown in the layer 14 of FIG. 3, for example. The covered state is adapted to the step. That is, the Al or Al alloy layer does not become thin at the lower side wall of the connection hole as shown in FIG. 6 and does not become thin at the open end of the connection hole as shown in FIG.

【0011】[0011]

【実施例】図1〜4は、この発明の一実施例に係る配線
形成法を示すもので、各々の図に対応する工程(1)〜
(4)を順次に説明する。
1 to 4 show a wiring forming method according to an embodiment of the present invention. Steps (1) to (1) corresponding to the respective drawings are shown.
(4) will be sequentially described.

【0012】(1)例えばシリコンからなる半導体基板
10の表面に不純物ドープ領域等の被接続部を覆って絶
縁膜12を形成した後、ホトリソグラフィ及びドライエ
ッチング処理により被接続部に対応した接続孔12Aを
形成する。そして、基板上面には、接続孔12A及び絶
縁膜12を覆ってスパッタ法によりTi層13a、Ti
N層13b等を順次に被着してバリアメタル層13を形
成する。
(1) After forming an insulating film 12 on a surface of a semiconductor substrate 10 made of, for example, silicon so as to cover a connection portion such as an impurity-doped region, a connection hole corresponding to the connection portion is formed by photolithography and dry etching. 12A is formed. Then, on the upper surface of the substrate, the Ti layer 13a, the Ti layer 13a
A barrier metal layer 13 is formed by sequentially depositing the N layer 13b and the like.

【0013】(2)次に、基板上面には、接続孔12A
及び絶縁膜12を覆ってバリアメタル層13に重ねてス
パッタ法によりAl又はAl合金層14を被着する。こ
の場合、スパッタ処理中の基板温度は、50〜200℃
の範囲内に設定する。
(2) Next, the connection hole 12A is formed on the upper surface of the substrate.
The insulating film 12 is covered with the barrier metal layer 13 and an Al or Al alloy layer 14 is deposited by sputtering. In this case, the substrate temperature during the sputtering process is 50 to 200 ° C.
Set within the range of.

【0014】(3)スパッタ処理後引き続いてスパッタ
室内の減圧雰囲気中で350〜450℃の温度でアニー
ル処理を行なう。この結果、Al又はAl合金層14
は、接続孔12Aの段差に順応した被覆状態となる。発
明者の研究によれば、アニール温度が350〜450℃
の範囲内にあるときに段差順応性のよい被覆状態が得ら
れ、350〜450℃の範囲外になると段差順応性が低
下することが判明した。
(3) After the sputtering process, an annealing process is subsequently performed at a temperature of 350 to 450 ° C. in a reduced pressure atmosphere in the sputtering chamber. As a result, the Al or Al alloy layer 14
Is in a covered state adapted to the step difference of the connection hole 12A. According to the research by the inventor, the annealing temperature is 350 to 450 ° C.
It was found that a coating state with good step conformability was obtained when the temperature was in the range of, and the step conformability was lowered when the temperature was out of the range of 350 to 450 ° C.

【0015】図5は、Al又はAl合金層14の被覆状
態がアニール温度に依存する様子を示すもので、アニー
ル温度が350〜450℃のときに良好な被覆状態が得
られることがわかる。特に、390〜420℃のアニー
ル温度にて好ましい被覆状態が得られた。アニール温度
を450℃より高くすると、段差部の膜厚tが薄くな
る。
FIG. 5 shows how the coating state of the Al or Al alloy layer 14 depends on the annealing temperature. It can be seen that a good coating state can be obtained when the annealing temperature is 350 to 450 ° C. In particular, a preferable coating state was obtained at an annealing temperature of 390 to 420 ° C. When the annealing temperature is higher than 450 ° C., the film thickness t of the step portion becomes thin.

【0016】(4)この後は、ホトリソグラフィ及びエ
ッチング処理により所望の配線パターンに従って配線材
層(バリアメタル層13及びAl又はAl合金層14の
積層)をパターニングして配線層16を形成する。配線
層16は、バリアメタル層13の残存部13A及びAl
又はAl合金層14の残存部14Aからなるもので、接
続孔12Aを介して基板10の被接続部に接続される。
(4) After that, the wiring material layer (the lamination of the barrier metal layer 13 and the Al or Al alloy layer 14) is patterned according to a desired wiring pattern by photolithography and etching to form the wiring layer 16. The wiring layer 16 includes the remaining portion 13A of the barrier metal layer 13 and Al.
Alternatively, it is composed of the remaining portion 14A of the Al alloy layer 14 and is connected to the connected portion of the substrate 10 through the connection hole 12A.

【0017】この発明の他の実施例としては、図2のス
パッタ処理において、基板温度を350〜450℃の範
囲内に設定することにより図3に示すように接続孔の段
差に順応した被覆状態を得るようにしてもよい。この場
合、スパッタ処理後のアニール処理は不要となり、工程
が簡単となる。
As another embodiment of the present invention, in the sputtering process of FIG. 2, the substrate temperature is set in the range of 350 to 450 ° C. to cover the step of the connection hole as shown in FIG. May be obtained. In this case, the annealing process after the sputtering process is unnecessary and the process is simplified.

【0018】[0018]

【発明の効果】以上のように、この発明によれば、Al
又はAl合金層の被覆状態が接続孔の段差に順応したも
のとなるので、配線形成歩留りが向上すると共に、配線
の信頼性が向上する効果が得られるものである。
As described above, according to the present invention, Al
Alternatively, since the coating state of the Al alloy layer is adapted to the step difference of the connection hole, the wiring formation yield is improved and the reliability of the wiring is improved.

【0019】すなわち、この発明によれば、次の(イ)
〜(ニ)の利点が得られる。
That is, according to the present invention, the following (a)
The advantages of (d) can be obtained.

【0020】(イ)接続孔のサイズによらず、また接続
孔配置の孤立、密集によらず良好な段差被覆性が得られ
る。
(A) A good step coverage can be obtained regardless of the size of the connection holes, or the isolation or density of the connection hole arrangement.

【0021】(ロ)接続孔に順応した被覆状態であるた
め、比較的薄い膜厚でもよい。このため、多層配線に有
利である。
(B) Since the coating state is adapted to the connection hole, the film thickness may be relatively thin. Therefore, it is advantageous for multilayer wiring.

【0022】(ハ)350〜450℃の温度であるた
め、基板に対する接続孔に限らず上層配線に対する接続
孔でも使用できる。
(C) Since the temperature is 350 to 450 ° C., not only the connection hole for the substrate but also the connection hole for the upper layer wiring can be used.

【0023】(ニ)被覆性、膜質とも良好であるため、
マイグレーション耐性がよい。
(D) Since the coatability and film quality are good,
Good migration resistance.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明の一実施例に係る配線形成法におけ
るバリアメタル被着工程を示す基板断面図である。
FIG. 1 is a substrate cross-sectional view showing a barrier metal deposition step in a wiring forming method according to an embodiment of the present invention.

【図2】 図1の工程に続く配線材被着工程を示す基板
断面図である。
FIG. 2 is a substrate cross-sectional view showing a wiring material attaching step following the step of FIG.

【図3】 図2の工程に続くアニール工程を示す基板断
面図である。
FIG. 3 is a substrate cross-sectional view showing an annealing process following the process of FIG.

【図4】 図3の工程に続く配線パターニング工程を示
す基板断面図である。
FIG. 4 is a substrate cross-sectional view showing a wiring patterning process that follows the process of FIG.

【図5】 Al又はAl合金層の被覆状態がアニール温
度に依存する様子を示す断面図である。
FIG. 5 is a cross-sectional view showing how the coating state of an Al or Al alloy layer depends on the annealing temperature.

【図6】 従来のスパッタ工程の一例を示す基板断面図
である。
FIG. 6 is a substrate cross-sectional view showing an example of a conventional sputtering process.

【図7】 従来のスパッタ工程の他の例を示す基板断面
図である。
FIG. 7 is a substrate cross-sectional view showing another example of a conventional sputtering process.

【符号の説明】[Explanation of symbols]

10:半導体基板、12:絶縁膜、12A:接続孔、1
3:バリアメタル層、14:Al又はAl合金層、1
6:配線層。
10: semiconductor substrate, 12: insulating film, 12A: connection hole, 1
3: barrier metal layer, 14: Al or Al alloy layer, 1
6: Wiring layer.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】基板の表面に被接続部を覆って絶縁膜を形
成した後、該絶縁膜に該被接続部に対応した接続孔を形
成する工程と、 前記接続孔及び前記絶縁膜を覆ってAl又はAl合金層
を被着する工程と、 前記Al又はAl合金層を350〜450℃の温度でア
ニール処理して前記接続孔の段差に順応した被覆状態に
する工程と、 前記Al又はAl合金層を前記アニール処理の後でパタ
ーニングして配線層を形成する工程とを含む配線形成
法。
1. A step of forming an insulating film on a surface of a substrate so as to cover the connected portion and then forming a connection hole corresponding to the connected portion in the insulating film, and covering the connection hole and the insulating film. A step of depositing an Al or Al alloy layer by means of annealing, and a step of annealing the Al or Al alloy layer at a temperature of 350 to 450 ° C. to provide a covering state adapted to the step of the connection hole; Forming a wiring layer by patterning the alloy layer after the annealing treatment.
【請求項2】基板の表面に被接続部を覆って絶縁膜を形
成した後、該絶縁膜に該被接続部に対応した接続孔を形
成する工程と、 前記接続孔及び前記絶縁膜を覆ってAl又はAl合金層
をスパッタ法で形成する工程であって、スパッタ処理中
の基板温度を350〜450℃の範囲内に設定すること
により前記Al又はAl合金層の被覆状態を前記接続孔
の段差に順応した状態にするものと、 前記Al又はAl合金層をパターニングして配線層を形
成する工程とを含む配線形成法。
2. A step of forming an insulating film on a surface of a substrate so as to cover the connected portion and then forming a connection hole corresponding to the connected portion in the insulating film, and covering the connection hole and the insulating film. In the step of forming an Al or Al alloy layer by a sputtering method by setting the substrate temperature during the sputtering process within a range of 350 to 450 ° C., the covering state of the Al or Al alloy layer of the connection hole is set. A wiring forming method, comprising: forming a wiring layer by patterning the Al or Al alloy layer so as to be adapted to a step.
JP6067689A 1994-03-11 1994-03-11 Method of forming wiring Pending JPH07249628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6067689A JPH07249628A (en) 1994-03-11 1994-03-11 Method of forming wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6067689A JPH07249628A (en) 1994-03-11 1994-03-11 Method of forming wiring

Publications (1)

Publication Number Publication Date
JPH07249628A true JPH07249628A (en) 1995-09-26

Family

ID=13352212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6067689A Pending JPH07249628A (en) 1994-03-11 1994-03-11 Method of forming wiring

Country Status (1)

Country Link
JP (1) JPH07249628A (en)

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