JPH07249060A - Delay time verification device for logic circuit - Google Patents

Abstract

PURPOSE:To verify the delay of the logic circuit under actual use conditions in consideration of all assembler instruction sequences to be inputted to the logic circuit. CONSTITUTION:An assembler instruction sequence storage means 1 holds all the assembler instruction sequences which are expected to be inputted to the logic circuit to be verified. An ineffective specification generation means 2 finds variation patterns of bits which are not present in the respective assembler instruction sequences by bit positions on the basis of those all assembler instruction sequences, and generates and outputs ineffective specifications regarding the rise or fall kind of an arc having its start node at a terminal of the logic circuit where a bit having no rise or fall variation pattern is applied to an ineffective specification storage means 3 on the basis of the result. A delay time verification means 9 corrects model information stored in a model information storage means 4 according to the ineffective specification stored in the ineffective specification storage means 3, and verifies the delay time of the logic circuit on the basis of the corrected model information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay time verification device for a logic circuit, and more particularly to a device for modeling a logic circuit according to graph theory and performing delay verification for the logic circuit according to the model information.

[0002]

2. Description of the Related Art A conventional delay time verification device for a logic circuit of this type will be described with reference to a simple logic circuit shown in FIG.

The logic circuit of FIG. 2 includes a circuit element 20, external input terminals 21 and 22, and an external output terminal 23, and a 1-bit signal having a signal name A applied to the external input terminal 21 and an external input terminal 22. Is a circuit for generating a 1-bit signal of the signal name C in the circuit element 20 from the 1-bit signal of the signal name B applied to and outputting it to the external output terminal 23.

When such a logic circuit is graphed according to graph theory, a directed graph represented as shown in FIG. 3 is obtained. That is, it is a directed graph in which external input / output terminals and terminals of circuit elements are nodes p to u and arcs a to e having signal flows between the nodes as their directions. Here, the arc a is a node p corresponding to the external input terminal 21.
Is a starting point node, an arc having a node q corresponding to one input terminal of the circuit element 20 as an end point node, and an arc b corresponds to a starting point node corresponding to the external input terminal 22 and the other input terminal of the circuit element 20. The arc having the node u as the end point node, the arc c having the node r corresponding to the output terminal of the circuit element 20 as the start point node, the arc having the node s corresponding to the external output terminal 23 as the end point node, the arc d and the arc e In the arcs corresponding to the internal signal paths of the circuit element 20, the start point node of the arc d is q, the end point node is r, the start point node of the arc e is u, and the end point node is r. The information of each node p to u includes the information of the signal name applied to its own node.

Further, as weights of the respective arcs a to e, as shown in FIG.
As shown in, the delay time information indicating the delay time of each arc is given as a part of the graph information. This delay time is given for each rising (R) or falling (F) type (hereinafter also referred to as R / F type) of the start point node and the end point node of each arc, and when there is no corresponding delay time In this case, the weight in that case is undefined (invalid) "x". Here, as shown in FIG. 4, the combination of the rising (R) and the falling (F) of the signals of the start point node and the end point node of a certain arc is such that the start point is R and the end point is R (R / R). In the case, the start point is R and the end point is F
There are four combinations of (R / F), the start point is F and the end point is R (F / R), and the start point is F and the end point is F (F / F). In the example of the logic circuit of 2,
Since it is not necessary to consider the combination of R / F and F / R2 types of each arc (possibly the case of an inverter function), it is defined as undefined "x", and the other two types of R / R,
With respect to the F / F combination, a delay time is given as a weight according to the characteristics of the circuit element 20. In FIG. 4, “0”, “1”, and “2” are delay times (unit is ns).

At the time of actual delay verification, the information shown in FIGS. 3 and 4 is prepared as model information, and the first path of a → d → c and the second path of b → e → c are prepared. For each of them, all the weights are calculated for each R / F type of the start point and the end point of each arc in FIG. 4, and the sum of the calculated weights is calculated as the delay time of each path. Finally, the maximum delay time is obtained for a plurality of paths having the same start and end nodes. The detailed operation of verifying the delay time will be described in detail later, but in the case of the information shown in FIGS. 3 and 4, 2 ns is calculated as the maximum delay time.

[0007]

By the way, when the logic circuit illustrated in FIG. 2 is actually used, an instruction sequence called an assembler instruction sequence for operating the logic circuit as intended by the user is concerned with the logic circuit. Applied to. Generally, each bit of the assembler instruction sequence is applied to the external input terminals 21 and 22 of the logic circuit, but it may be directly applied to the terminal of the internal element depending on the type of the logic circuit. In the following example, it is assumed that the voltage is applied to the external input terminals 21 and 22.

FIG. 5 shows the external input terminal 2 of the logic circuit of FIG.
An example of all the assembler instruction sequences scheduled to be applied to Nos. 1 and 22 is shown, and here three assembler instruction sequences 51, 52 and 53 are shown. Each of the assembler instruction sequences 51 to 53 has two external input terminals 21 and 22 of the logic circuit of FIG. 2, so that “00”, “01”,
Two or more of any four types of 2-bit instructions "10" and "11" (this is called an assembler instruction) are arranged side by side. That is, the assembler instruction sequence 51 is "1.
Three assembler instructions "1", "10", "01" are arranged, and the assembler instruction string 52 is "10", "0".
A series of three assembler instructions "1" and "00",
The assembler instruction string 53 is an array of two assembler instructions "01" and "00", each of which is to operate the logic circuit as intended by the user through a series of operations. The upper bit of each assembler instruction is associated with the signal name A, and the lower bit is associated with the signal name B, and the lower bit is associated with the signal name B. Is applied to the bit.

When all the assembler instruction sequences input to the logic circuit are determined, the delay time of the logic circuit is verified by detecting a timing problematic path within the range of these assembler instruction sequences. On the contrary, it is not preferable to verify in the range of an arbitrary assembler instruction sequence because it is different from the actual use condition. Considering from this point of view, when all the assembler instruction sequences applied to the logic circuit of FIG. 2 are those shown in FIG. 5, when the change pattern of the bit corresponding to the signal name A is examined, each assembler instruction The state of the signal having the signal name A immediately before the input of the sequence is undefined, so that the assembler instruction sequence 51 is undefined → 1 → 1 →
0, and the assembler instruction sequence 52 is undefined 1
→ 0 → 0, and the assembler instruction sequence 53 changes indefinitely → 0 → 0, and no change pattern of 0 → 1 appears in any assembler instruction sequence. Therefore, for the signal name A, it is necessary to verify the delay time on the assumption that there is no change pattern of 0 → 1. However, the delay time verification device of the conventional logic circuit does not have such a change pattern. However, there is a problem that the verification result cannot be obtained under the actual use condition because it does not have a mechanism for detecting the error and reflecting it in the delay verification.

The present invention solves such a conventional problem, and its purpose is to eliminate bits that do not exist based on all the assembler instruction sequences that are planned to be applied to the logic circuit to be verified. It is an object of the present invention to provide a delay time verification device for a logic circuit that can detect a change pattern and perform delay verification on the assumption that such a change pattern does not exist.

The inventor of the present invention filed a prior patent application (Japanese Patent Application No.
-105017), regarding an arc in which only one of the rising edge and the falling edge of the signal is effective,
A designer directly specifies the arc and the type of rising or falling that becomes invalid, a designating unit that modifies the model information based on the designating information by the designating unit, and the model after the modification. A delay time verification device for a logic circuit including a means for verifying the delay time of the logic circuit based on information is proposed. The above problem can be solved by using such a proposed device, but since the designer must create the invalid designation, there is a possibility that invalid designation omission or erroneous designation due to manual creation will occur. is there. Therefore, another object of the present invention is to enable generation of invalid designations without human intervention and prevent omission or incorrect designation of invalid designations due to manual creation.

[0012]

In order to achieve the above object, the present invention uses each external terminal and each circuit element terminal of a logic circuit whose delay time is to be verified as a node, and Consists of directed graph information in which the arc has a flow as its direction, and delay time information that holds the delay time each has as a weight of each of these arcs for each rising / falling type of the start node and end node corresponding to the arc. Model information storage means for storing the generated model information, and all of the bit-represented assembler instruction sequence to be applied to the logic circuit, together with information specifying the position to which each bit is applied. Based on the assembler instruction sequence storage means and all the assembler instruction sequences stored in the assembler instruction sequence storage means, A change pattern of a nonexistent bit is obtained for each bit position, and according to the result, a rising or arc of an arc whose start point node is the terminal of the logic circuit to which a bit having no rising or falling change pattern is applied is applied. Invalid designation generating means for generating invalid designation relating to fall type, invalid designation storing means for storing the invalid designation generated by the invalid designation generating means, invalid designation stored in the invalid designation storing means, and the model information. Based on the model information stored in the storage means,
And a delay time verification means for verifying the delay time.

[0013]

In the logic circuit delay time verification device of the present invention, all the assembler command strings that the assembler command string storage means is expected to apply to the external input terminals of the logic circuit whose delay time is to be verified. Is held together with information (for example, a signal name) for specifying the position to which each bit is applied. At the time of delay verification, the invalidation specification generating means stores all the assembler instruction strings stored in the assembler instruction string storing means. Based on the result, the change pattern of the bit that does not exist in each assembler instruction sequence is obtained for each bit position, and according to the result, the terminal of the logic circuit to which the bit for which the rising or falling change pattern does not exist is applied is determined. Generates an invalid designation related to the rising or falling type of the arc that is the start point node, outputs it to the invalid designation storage means, and delays it. During verification means, based on the invalid specification and model information stored in the model information storing means stored in the invalid specification storage unit verifies the delay time. That is, the delay time verification means corrects the delay time information in the model information stored in the model information storage means according to the invalid designation stored in the invalid designation storage means, and based on the corrected model information Verify the delay time.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, a delay time verification device for a logic circuit according to an embodiment of the present invention includes an assembler instruction sequence storage means 1, an invalid designation generation means 2 and an invalid designation storage means 3.
A model information storage means 4, a delay time verification means 9,
And output means 8.

The model information storage means 4 stores model information of a logic circuit whose delay time is to be verified. In the case of the logic circuit shown in FIG. 2, the directed graph information shown in FIG. 3 and FIG. The graph information composed of the delay time information shown in FIG. That is, each external terminal of the logic circuit whose delay time is to be verified and each terminal of the circuit element are used as nodes, and an arc having a signal flow between each node as its direction is set, and each arc has a weight as a weight. A delay time is given, and this delay time is given for each R / F type of the start point node and the end point node corresponding to the arc.

Each bit is applied to the assembler instruction sequence storage means 1 for all the assembler instruction sequences which are scheduled to be applied to the logic circuit represented by the model information stored in the model information storage means 4. It is stored in advance together with the signal name for specifying the position. FIG. 5 shows an entire assembler instruction sequence stored in the assembler instruction sequence storage means 1,
It includes three assembler instruction sequences 51, 52 and 53. Signal names A and B designating the position where each bit is input are added to each of the assembler instruction sequences 51 to 53.

The invalidation specification generating means 2 obtains, for each bit position, a change pattern of bits which does not exist in each assembler instruction sequence, based on all the assembler instruction sequences stored in the assembler instruction sequence storing means 1, and According to the result
An invalid designation in a format that can be used by the delay time verification means 9 is generated and output to the invalid designation storage means 3.

FIGS. 6 and 7 are flowcharts showing an example of processing of the invalid designation generating means 2, and the operation of the invalid designation generating means 2 will be described below.

The invalidation specification generating means 2 first recognizes all the existing signal names by referring to the assembler instruction sequence stored in the assembler instruction sequence storing means 1, and recognizes the rising edge detection flag and the falling edge for each signal name. Generate a detection flag,
All of these flags are initialized to off (S1). Figure 5
In the above example, the rising detection flag corresponding to the signal name A,
A total of four flags including the falling detection flag, the rising detection flag corresponding to the signal name B, and the falling detection flag are generated, and all of them are initialized to OFF.

Next, paying attention to the signal name A which is the first signal name (S2), the first assembler instruction string 51 is input from the assembler instruction string storage means 1 (S3). Then, the first bit value "1" in the assembler instruction sequence 51 is assigned to the variable X (S4), and the next bit value "1" is set to the variable Y.
(S5), XY calculation is executed (S7), and the result is determined (S8).

If the operation result is negative (-), it means that the change pattern of 0 → 1 has been detected. Therefore, the rising detection flag corresponding to the signal name A is turned on (S9), and it is positive (+). For example, since the change pattern of 1 → 0 is detected, the fall detection flag corresponding to the signal name A is turned on (S10), and if the result is 0, the flag operation is not performed. In this case, both X and Y are 1, so the result is 0.
Then, Y is substituted for X (S12), the next bit value "0" is substituted for Y, and the operation of XY is performed again (S5).
S7). Since this result is positive, the fall detection flag corresponding to the signal name A is turned on (S10). Since the next bit does not exist in the assembler instruction sequence 51 input this time, the process proceeds from step S6 to S13 to input the next assembler instruction sequence 52, and the process returns to step S4 to repeat the same processing as the assembler instruction sequence 51. The bit of the signal name A of this assembler instruction string 52 changes from 1 → 0 → 0, and 0 →
Since there is no change of 1, the rising edge detection flag corresponding to the signal name A remains off even after the processing of the assembler instruction sequence 52. Next, the assembler instruction sequence 53 is processed in the same manner, but the bit of the signal name A only changes from 0 to 0, and there is no change from 0 to 1, so even after the processing of the assembler instruction sequence 53 The rising detection flag corresponding to A remains off. Since the end of the assembler instruction sequence is identified when the next assembler instruction sequence is to be input after processing of the assembler instruction sequence 53,
The process for the signal name A is completed, the next signal name B is focused (S15), and the same process as the signal name A is performed for the signal name B.

For the signal name B, the operation result of the first bit value "1" and the second bit value "0" of the signal name B in the first assembler instruction string 51 is positive,
First, the fall detection flag corresponding to the signal name B is turned on, and then the operation result of the second bit value “0” and the third bit value “1” becomes negative, so it corresponds to the signal name B. The rising detection flag is turned on. At this point, since both flags are turned on, the process for the signal name B ends, and steps S11 to S15 and S1 are performed.
6, it is determined that attention has been paid to all signal names, and the process proceeds to FIG. 7.

In the process of FIG. 7, attention is first paid to the signal name A (S21), and the states of the rising detection flag and the falling detection flag corresponding thereto are discriminated (S22, S23). If the rising detection flag is off, the terminal of the logic circuit to which the signal of the signal name A is input is specified from the information of the node in the directed graph in the model information storage means 4, and the specified terminal is used as the starting point. An arc is specified from the delay time information in the model information storage unit 4, an invalid specification for invalidating the weight of the specified rising type of the arc is generated and output to the invalid specification storage unit 3 (S24). On the other hand, if the fall detection flag is off, the terminal of the logic circuit to which the signal of the signal name A is input is specified from the information of the node in the directed graph in the model information storage means 4, and the specified terminal is set as the starting point. The arc to be performed is specified from the delay time information in the model information storage unit 4, and an invalid specification for invalidating the weight of the specified fall type of the arc is generated and output to the invalid specification storage unit 3 (S25). In this case, since the rising detection flag is off, the invalid designation as shown in FIG. 8 is made in step S2.
4 is generated and output to the invalid designation storing means 3.

After the signal name A, attention is focused on the signal name B (S26), and the same processing as the signal name A is performed, but in this case, neither the rising detection flag nor the falling detection flag is off. The invalid designation is not generated for the signal name A. When it is determined in step S27 that attention has been paid to all signal names, the invalid designation generation process ends.

Now, referring again to FIG. 1, the delay time verification means 9 verifies the delay time based on the invalid designation stored in the invalid designation storage means 3 and the model information stored in the model information storage means 4. Model information correction unit 5 that corrects the model information stored in the model information storage unit 4 according to the invalidation specification stored in the invalidation specification storage unit 3, and a correction model that stores the model information after the correction. The delay time of the logic circuit is verified based on the information storage unit 6 and the modified model information, and the verification result is output means 8
And the delay verification unit 7 for outputting to.

FIG. 9 is a flowchart showing a processing example of the model information correction section 5. The model information correction unit 5 first inputs the model information shown in FIGS. 2 and 3 from the model information storage unit 4 (S30). Next, invalid designation storage means 3
As the first invalid designation, the invalid designation shown in FIG. 8 is input (S31), and the model information is corrected according to this invalid designation. That is, the weight of the R / R which is the R / F type designated by the invalid designation of the arc a designated by the invalid designation is set to invalid "x" (S33). Then, the next invalid designation is input from the invalid designation storage means 3 (S34), and if it exists, the model information is corrected according to the invalid designation. In this case, however, since there is no other invalid designation, the corrected model is corrected. The information is output to the modified model information storage unit 6 (S36),
The model information correction process ends. If there is no invalid designation in the invalid designation storing means 3, step S
The process proceeds from 32 to step S37, and the input model information itself is output to the modified model information storage unit 6.

By the above-described processing being performed by the model information correction section 5, the information in FIG. 4 is corrected as shown in FIG.

The delay verification unit 7 of FIG. 1 performs delay verification according to the modified model information stored in the modified model information storage unit 6, and its operation is the same as the conventional one. Less than,
The operation of the delay verification unit 7 will be described with reference to the flowchart of FIG.

Since there are generally a plurality of signal paths in the model to be verified, the delay time is calculated for each path,
Finally, from these calculated delay times, the paths having the same start point and end point are combined into one and the delay time is finally calculated. Therefore, first, a vertical search (depth-first search;
A path in the depth direction is obtained by the Depth First Search (DFS) method (S41). Then, one of these paths is selected as the first path (S4
2) The R / F type of all the nodes of the path is set to, for example, all R (S44).

In the example of FIG. 2, assuming that the first path is a → d → c, the nodes of the path are p, q, r, and s,
It is assumed that all of these are set at the signal rising edge R. Then, the current combination of R / F types of all nodes, that is, in the present case, all arcs a in all R,
The weights (delay times) of d and c are obtained (S4)
6). This weight is obtained from the corrected information in FIG.
For example, regarding the weight of the arc a, since the starting point is p and the ending point is q, and the current R / F types are all R, refer to the starting point / ending point R / R of the arc a in FIG. Then, the weight “x” is searched. The weights of the other arcs d and c are similarly searched, and the results are shown in the top row of FIG.

In this way, when the R / F types of all nodes are all R, the weights of the arcs shown in the uppermost row of FIG. 12 are obtained and their sum is calculated (S4).
7). However, in the weight summing process in this case, if even one weight has an invalid "x", the total is also invalid "x".

Next, one R / F type of the node is set to F, and a second R / F type is combined (S4).
8). That is, as shown in the second line of FIG. 12, the type of each node R / F is changed from all R (R, R, R, R) to (F,
R, R, R) combination. And this R / F
Steps S46 and 47 are executed by the combination of the types, the total weight of each arc is calculated, and in step S48, the R / F types of the other nodes are set to F and the third R / F type combination is set. That is, as shown in the third line of FIG. 12, the R / F type of each node is a combination of (R, F, R, R). Then, steps S46 and S48 are executed for this combination of R / F types.

Since there are four nodes in this path,
Combinations of R / F type for all nodes is 2 ^4, thus a combination of the two ^four R / F type, step S
46 and S47 are executed. The weight of each arc and the total thereof in the case of the last combination of all F (F, F, F, F) are shown in the bottom row of FIG.

When all combinations of R / F types of all nodes (all of 2 ⁴ ) are completed (YES in S45), the next second path is selected (S49). Also for this second pass, similarly to the above-mentioned first pass, steps S44,
S46, S47 and S48 are sequentially and repeatedly executed.

The execution result of the second pass is shown in FIG.
3 is shown. Note that, in FIG. 13, all the results when the invalid “x” is included are omitted.

When the above operation is completed for all paths (YES in S43), finally, a plurality of paths having the same start point and end point nodes are combined into one path having the maximum delay time (S50).

The examples of FIGS. 12 and 13 are paths in which both paths are combined into one. In this case, the maximum delay time of the first path is 1 ns, and the maximum delay time of the second path is also 1 ns.
Since it is ns, the final result is 1 ns. This final result is output to the output means 8 of FIG.

On the other hand, in the delay verification using the information of FIG. 4 before the correction, the maximum delay time of the first pass is 2 ns, so that the correct verification is performed within the range of the assembler instruction sequence to be used. Will not be possible.

[0040]

As described above, according to the present invention,
To detect a non-existent bit change pattern based on all assembler instruction sequences that are expected to be applied to the logic circuit to be verified, and perform delay verification assuming that such a change pattern does not exist. The logic circuit can be verified under actual use conditions. Further, by automating the detection of the nonexistent bit change pattern and the generation of the invalid designation based on the detection result, it is possible to reduce the burden on the designer and prevent human error from being mixed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a logic circuit to be verified.

FIG. 3 is a directed graph showing the logic circuit of FIG. 2 according to graph theory.

FIG. 4 shows R for each arc in the directed graph of FIG.
It is a figure which shows the example of the delay time given for every / F type.

FIG. 5 is a diagram showing an example of an assembler instruction sequence.

FIG. 6 is a flowchart showing a part of a processing example of an invalid designation generating means.

FIG. 7 is a flowchart showing the remaining part of the processing example of the invalid designation generation means.

FIG. 8 is a diagram showing an example of invalid designation.

FIG. 9 is a flowchart illustrating a processing example of a model information correction unit.

FIG. 10 is a diagram showing model information modified according to invalid designation.

FIG. 11 is a flowchart illustrating a processing example of a delay verification unit.

FIG. 12 is a diagram showing an example of a delay verification result.

FIG. 13 is a diagram showing an example of a delay verification result.

[Explanation of symbols]

 1 ... Assembler instruction string storage means 2 ... Invalid designation generation means 3 ... Invalid designation storage means 4 ... Model information storage means 5 ... Model information correction section 6 ... Modified model information storage section 7 ... Delay verification section 8 ... Output means 9 ... Delay Time verification means

Claims (3)

[Claims] 1. Directed graph information in which each external terminal and a terminal of each circuit element of a logic circuit whose delay time is to be verified are defined as nodes, and a flow of a signal between the nodes is defined as an arc, and each of these arcs. Model information storage means for storing model information constituted by delay time information held by each rising / falling type of a start point node and an end point node corresponding to an arc, each having a delay time as a weight of And an assembler instruction sequence storage means for storing all of the bit-represented assembler instruction sequence to be applied to each of the bits together with information specifying the position to which each bit is applied, and the assembler instruction sequence storage means. Based on all the assembler instruction sequences, the change pattern of bits that does not exist in each assembler instruction sequence According to the result, the invalid designation generating means for generating the invalid designation regarding the rising or falling type of the arc whose starting point is the terminal of the logic circuit to which the bit having no rising or falling change pattern is applied is generated. And an invalid designation storage unit for storing the invalid designation generated by the invalid designation generation unit, and a delay time based on the invalid designation stored in the invalid designation storage unit and the model information stored in the model information storage unit. And a delay time verifying means for verifying the above. 2. The model information correction unit, wherein the delay time verification unit corrects the delay time information in the model information stored in the model information storage unit in accordance with the invalid designation stored in the invalid designation storage unit, The delay time verification device for a logic circuit according to claim 1, further comprising a delay verification unit that verifies a delay time of the logic circuit based on the model information corrected by the model information correction unit. 3. The model information correction section invalidates and corrects the delay time in the model information corresponding to the rising or falling type of the arc designated by the invalidation specification. Delay time verification device for logic circuits.