JPH0724294B2 - Semiconductor mounted cooling structure - Google Patents

Semiconductor mounted cooling structure

Info

Publication number
JPH0724294B2
JPH0724294B2 JP24253087A JP24253087A JPH0724294B2 JP H0724294 B2 JPH0724294 B2 JP H0724294B2 JP 24253087 A JP24253087 A JP 24253087A JP 24253087 A JP24253087 A JP 24253087A JP H0724294 B2 JPH0724294 B2 JP H0724294B2
Authority
JP
Japan
Prior art keywords
semiconductor element
cooling
semiconductor
printed circuit
flexible printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24253087A
Other languages
Japanese (ja)
Other versions
JPS6486543A (en
Inventor
慧 小倉
孝雄 舟本
良一 梶原
光雄 加藤
孝 服巻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP24253087A priority Critical patent/JPH0724294B2/en
Publication of JPS6486543A publication Critical patent/JPS6486543A/en
Publication of JPH0724294B2 publication Critical patent/JPH0724294B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体素子を実装する冷却構造体に係り、特
に半導体素子と多層積層板とをフレキシブルプリント回
路を介し微小はんだ付けをビーム熱源によつて行い、し
かも該半導体素子の冷却を効率よく行う半導体実装冷却
構造体に関する。
Description: FIELD OF THE INVENTION The present invention relates to a cooling structure for mounting a semiconductor element, and more particularly to a semiconductor element and a multilayer laminated board via a flexible printed circuit for micro soldering as a beam heat source. The present invention relates to a semiconductor-mounted cooling structure that efficiently cools the semiconductor element.

〔従来の技術〕[Conventional technology]

半導体素子の外部接続用パツトから外部への接続法につ
いては、一般的に知られているように細線の金属ワイヤ
によるワイヤボンデイング法、プリント基板と半導体素
子の外部接続用パツトを向合せて微小はんだにより直接
接合させるコントロールコラプス法、更にフレキシブル
プリント回路を用いる方法として、例えば特開昭62-465
37号公報に記載されているようにテープ・オートメイテ
ツド・ボンデイング法がある。
As for the method of connecting the external connection pad of the semiconductor element to the outside, as is generally known, the wire bonding method using a thin metal wire, the printed circuit board and the external connection pad of the semiconductor element are faced to each other and fine soldering is performed. As a control collapse method for directly joining by means of a method using a flexible printed circuit, for example, Japanese Patent Laid-Open No. 62-465.
There is a tape automated bonding method as described in Japanese Patent No. 37.

また、半導体素子と多層積層板との接続は特開昭61-203
648号公報に記載されているように、上記のコントロー
ルコラプス法を用い、熱歪を吸収してはんだポールの破
壊を防止して接続する方法がある。第2図に高密度で半
導体素子を実装する従来例として、コントロールコラプ
ス法を示す。すなわち第2図はその従来の1実施例の縦
断面図であり、符号1は半導体素子、2は接合層、10は
多層配線、11は多層積層板、12は放熱体、13ははんだバ
ンプを意味する。半導体素子1はフエースダウンに配置
され多層積層板11中の多層配線10にはんだバンプ13を介
してはんだ付けされる。したがつて放熱体12は半導体素
子の裏面に接合層2を介して接合される。
Further, the connection between the semiconductor element and the multilayer laminated board is disclosed in JP-A-61-203.
As described in Japanese Patent No. 648, there is a method in which the control collapse method described above is used to absorb thermal strain and prevent the solder pole from being broken, thereby connecting the solder pole. FIG. 2 shows a control collapse method as a conventional example in which semiconductor elements are mounted at high density. That is, FIG. 2 is a vertical cross-sectional view of a conventional embodiment of the invention. Reference numeral 1 is a semiconductor element, 2 is a bonding layer, 10 is a multilayer wiring, 11 is a multilayer laminated plate, 12 is a radiator, and 13 is a solder bump. means. The semiconductor element 1 is arranged in a face-down manner and is soldered to the multilayer wiring 10 in the multilayer laminate 11 via solder bumps 13. Therefore, the radiator 12 is bonded to the back surface of the semiconductor element via the bonding layer 2.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上記従来技術で示したように半導体素子端子と多層積層
板を高密度で接続するためには半導体素子をフエースダ
ウンに配置し、半導体素子端子と多層積層板を向合せて
直接にコントロールコラプス法ではんだ付けする方が有
利である。
As shown in the above-mentioned prior art, in order to connect the semiconductor element terminals and the multilayer laminated board at high density, the semiconductor elements are arranged in the face-down, and the semiconductor element terminals and the multilayer laminated board are opposed to each other by the control collapse method directly. Soldering is more advantageous.

しかし、半導体素子の形状が大きくなる場合、半導体素
子と多層積層板の熱膨張率の差によつて応力が発生し、
上記従来法でも応力は低減できず、はんだバンプに破壊
を生じる。これを解決するためには柔軟なフレキシブル
プリント回路を用いる方が有利である。
However, when the shape of the semiconductor element becomes large, stress is generated due to the difference in coefficient of thermal expansion between the semiconductor element and the multilayer laminated plate,
Even with the above conventional method, the stress cannot be reduced, and the solder bump is broken. To solve this, it is more advantageous to use a flexible printed circuit.

更に、半導体素子をフエースダウンに配置すると半導体
素子の発する熱を上方向から除去する必要があり、冷却
体の重量や歪による応力が直接接続部のはんだバンプに
かかるようになり、はんだバンプが破壊する恐れがあ
る。したがつて冷却体からの応力がはんだバンプに直接
に作用しない構造が好ましい。
Furthermore, if the semiconductor elements are arranged in a phase-down manner, it is necessary to remove the heat generated by the semiconductor elements from above, and the stress due to the weight and strain of the cooling body will be applied directly to the solder bumps at the connection parts, destroying the solder bumps. There is a risk of Therefore, a structure in which the stress from the cooling body does not directly act on the solder bumps is preferable.

本発明の目的は半導体素子の端子にかかる応力を低減
し、しかも、半導体の発する熱を有効に除去する半導体
実装冷却構造体を提供することにある。
An object of the present invention is to provide a semiconductor mounted cooling structure that reduces stress applied to terminals of a semiconductor element and effectively removes heat generated by the semiconductor.

〔問題点を解決するための手段〕[Means for solving problems]

本発明を概説すれば、本発明は半導体実装冷却構造体に
関する発明であつて、発熱を伴い間接的に冷却を要する
半導体素子を実装する冷却構造体において、該半導体素
子の外部接続用パツト形成面を上向きに配置し、該半導
体素子の下面は、内部を冷却媒体によつて冷却された金
属冷却体に接合され、該パツトはフレキシブルプリント
回路によつて接合され、該フレキシブルプリント回路の
外部端子は、該金属冷却体のスルーホールを通して多層
積層板に接合されていることを特徴とする。
Briefly describing the present invention, the present invention relates to a semiconductor mounting cooling structure, which is a cooling structure for mounting a semiconductor element that requires heat and indirectly requires cooling, in which a pad forming surface for external connection of the semiconductor element is provided. And the lower surface of the semiconductor element is joined to a metal cooling body whose inside is cooled by a cooling medium, the pad is joined by a flexible printed circuit, and the external terminal of the flexible printed circuit is It is characterized in that it is joined to the multilayer laminate through the through holes of the metal cooling body.

前記目的は半導体素子の外部接続用パツト形成面を上向
に配置し、そのパツトとフレキシブルプリント回路とは
上部よりビーム熱源によりはんだ付けし、該半導体素子
の下面は冷却体に接合して熱を冷却体により吸収するこ
とにより解決される。
The purpose is to arrange the external connection pad forming surface of the semiconductor element upward, and the pad and the flexible printed circuit are soldered from above with a beam heat source, and the lower surface of the semiconductor element is joined to a cooling body to heat the surface. It is solved by absorption by the cooling body.

半導体素子の外部接続用パツトは上面にあるので、フレ
キシブルプリント回路との位置合せは上部よりTV等の光
学的手段によつて正確に行え、はんだ付けは接合部にレ
ーザ、赤外線、キセノンなどのビーム熱源を直接に加熱
しはんだを溶融することによつて容易に行える。また、
接合後の検査及び補修等も接合部が上部に露出している
ので容易に行える。更にフレキシブルプリント回路を用
いているので、半導体素子のはんだ接合部にかかる応力
は少なく使用中の信頼性は大幅に向上する。
Since the external connection pad of the semiconductor element is on the top surface, the alignment with the flexible printed circuit can be performed accurately from the top by optical means such as TV, and the soldering can be done by laser, infrared, xenon, etc. This can be easily done by directly heating the heat source to melt the solder. Also,
Inspection and repair after joining can be easily performed because the joint is exposed at the top. Further, since the flexible printed circuit is used, the stress applied to the solder joint portion of the semiconductor element is small and the reliability during use is greatly improved.

また、半導体素子の裏面は金属冷却体に接合されるの
で、半導体素子の発生する熱は効率よく冷却される。
Moreover, since the back surface of the semiconductor element is bonded to the metal cooling body, the heat generated by the semiconductor element is efficiently cooled.

本発明の半導体実装冷却構造体においては、半導体素子
の下面と該金属冷却体とが、その間に、電気抵抗が高く
熱伝導性の良好な層を挟み、電気的に絶縁されて接合さ
れている構造が好ましい。
In the semiconductor-mounted cooling structure of the present invention, the lower surface of the semiconductor element and the metal cooling body are electrically insulated and joined by sandwiching a layer having high electrical resistance and good thermal conductivity therebetween. The structure is preferred.

該金属冷却体は、熱伝導の良好な金属板からなり、その
中に通路が形成され、その通路には冷却媒体が流されて
冷却が行われ、通路の形成されない部分にはその板厚方
向にスルーホールが形成され、このスルーホール中には
電気回路を通してフレキシブルプリント回路と多層積層
板とが電気的に接続される構造である。
The metal cooling body is made of a metal plate having good heat conduction, a passage is formed therein, a cooling medium is flown in the passage to perform cooling, and a portion where the passage is not formed has a thickness direction thereof. A through hole is formed in the through hole, and the flexible printed circuit and the multilayer laminated board are electrically connected to each other through an electric circuit in the through hole.

また、半導体素子の外部接続用パツトと多層積層板の端
子とが、フレキシブルプリント回路によつてはんだによ
り接続されているのが好ましい。
Further, it is preferable that the external connection pads of the semiconductor element and the terminals of the multilayer laminate are connected by soldering with a flexible printed circuit.

〔実施例〕〔Example〕

以下、本発明を実施例により更に具体的に説明するが、
本発明はこれら実施例に限定されない。
Hereinafter, the present invention will be described in more detail with reference to Examples.
The present invention is not limited to these examples.

実施例1 第1図は全体構成を示す本発明の半導体実装冷却体の縦
断面図を示す。第1図において、符号1は半導体素子、
2は接合層、3は半導体素子端子、4はフレキシブルプ
リント回路、5は多層配線端子、6は絶縁板、7は金属
冷却体、8は冷却孔、9はスルーホール、10は多層配
線、11は多層積層板を意味する。半導体素子1は外部接
続用パツト形成面を上向き、すなわちフエースアツプに
配置され金属冷却体7に接合層2を介して電気的には絶
縁され、熱の伝導が良好になるように接合される。金属
冷却体7は熱伝導の良好な金属、例えば鋼等で構成さ
れ、その中に金属的な接合法、例えばはんだ付け、ろう
付け、拡散接合等を用いて冷却孔8が形成され、その中
に冷却媒体が流され冷却される。金属冷却体7には冷却
孔8の無い部分にスルーホール9があけられる。多層積
層板11は金属冷却体7の下法に設置され、多層配線10は
スルーホール9を通して絶縁板6上に引出される。半導
体素子1の外部接続用パツトと多層配線10とはフレキシ
ブルプリント回路4を介して半導体素子端子3と多層配
線端子5にてはんだ付けされる。
Embodiment 1 FIG. 1 is a vertical cross-sectional view of a semiconductor mounted cooling body of the present invention showing the entire structure. In FIG. 1, reference numeral 1 is a semiconductor element,
2 is a bonding layer, 3 is a semiconductor element terminal, 4 is a flexible printed circuit, 5 is a multilayer wiring terminal, 6 is an insulating plate, 7 is a metal cooling body, 8 is a cooling hole, 9 is a through hole, 10 is a multilayer wiring, 11 Means a multilayer laminate. The semiconductor element 1 is arranged with the external connection pad forming surface facing upward, that is, is arranged on the face-up and is electrically insulated from the metal cooling body 7 via the bonding layer 2 and is bonded so that heat conduction is good. The metal cooling body 7 is made of a metal having good heat conduction, such as steel, and the cooling hole 8 is formed therein by using a metallic joining method such as soldering, brazing, or diffusion joining. A cooling medium is caused to flow through and is cooled. The metal cooling body 7 is provided with a through hole 9 in a portion where there is no cooling hole 8. The multi-layer laminated plate 11 is installed under the metal cooling body 7, and the multi-layer wiring 10 is drawn out on the insulating plate 6 through the through hole 9. The external connection pads of the semiconductor element 1 and the multilayer wiring 10 are soldered at the semiconductor element terminal 3 and the multilayer wiring terminal 5 via the flexible printed circuit 4.

第3図はフレキシブルプリント回路4と半導体素子1と
の接続状況を示す正面図である。第3図中符号1、3及
び5は第1図と同義であり、14は絶縁膜、15は応力緩和
用切込みを意味する。フレキシブルプリント回路4は絶
縁膜、例えばポリイミド膜上に銅電極が形成されたもの
であり、電極は半導体素子端子3及び多層配線端子5に
おいてはんだ付けされる。フレキシブルプリント回路は
それ自身が柔軟構造体のため接合部にかかる応力は小さ
いが、更に絶縁膜14の角には応力緩和用切込み15を入れ
て接合部にかかる応力を低減させ、接合部の破壊を防止
する。
FIG. 3 is a front view showing a connection state between the flexible printed circuit 4 and the semiconductor element 1. In FIG. 3, reference numerals 1, 3 and 5 have the same meanings as in FIG. 1, 14 is an insulating film, and 15 is a stress relaxation notch. The flexible printed circuit 4 is formed by forming a copper electrode on an insulating film, for example, a polyimide film, and the electrode is soldered to the semiconductor element terminal 3 and the multilayer wiring terminal 5. Since the flexible printed circuit itself is a flexible structure, the stress applied to the joint is small, but the stress relaxation notch 15 is further formed in the corner of the insulating film 14 to reduce the stress applied to the joint, resulting in destruction of the joint. Prevent.

第4図は金属冷却体7の水平方向の中心における横断面
図である。第4図中の符号1、5、8及び9は第1図と
同義である。半導体素子1の下方には金属冷却体7の中
に冷却孔8が微細に形成され、この中に冷媒、例えば水
等を流すことにより半導体素子1から発生する熱は効率
よく除去される。半導体素子1の周囲には多層配線10を
通すためのスルーホール9が形成される。このスルーホ
ール9は冷却孔8の形成されていない位置に形成され、
冷却孔8への冷媒の導入及び排出口はスルーホール9の
間隙に形成される。金属冷却体7中に微細で複雑な冷却
孔を形成するためには、金属板にエツチング等により冷
却孔8のパターンにエツチング等で溝を形成し、他の金
属板をはんだ付け、ろう付け、拡散接合等で接合するこ
とによつて可能となる。また、スルーホール9中に多層
配線端子5を保持するためにはスルーホール9と多層配
線端子5の間に電気的絶縁物を充てんすることによつて
達成される。
FIG. 4 is a horizontal cross-sectional view of the metal cooling body 7 at the horizontal center. Reference numerals 1, 5, 8 and 9 in FIG. 4 have the same meanings as in FIG. Cooling holes 8 are finely formed in the metal cooling body 7 below the semiconductor element 1, and heat generated from the semiconductor element 1 is efficiently removed by flowing a coolant, such as water, into the cooling holes 8. Through holes 9 are formed around the semiconductor element 1 for passing the multilayer wiring 10. The through hole 9 is formed at a position where the cooling hole 8 is not formed,
The inlet and outlet of the cooling medium to and from the cooling hole 8 are formed in the gap between the through holes 9. In order to form a fine and complicated cooling hole in the metal cooling body 7, a groove is formed in the pattern of the cooling hole 8 by etching or the like in the metal plate by soldering, soldering or brazing another metal plate, It becomes possible by joining by diffusion joining or the like. Further, in order to hold the multilayer wiring terminal 5 in the through hole 9, it is achieved by filling an electrical insulator between the through hole 9 and the multilayer wiring terminal 5.

実施例2 本発明の実装法は薄い金属冷却体を用い、しかも、半導
体素子の端子の接合が薄くできるので、全体として薄い
構造になる。今後は電気信号の高速化によつて電気回路
のインピーダンスを低減することが要求されるが、この
場合、本発明によれば薄く実装された冷却体を更に多層
にかさねて立体化でき、内部から冷却する3次元実装が
可能になる。
Example 2 The mounting method of the present invention uses a thin metal cooling body, and since the terminals of the semiconductor element can be joined thinly, the overall structure is thin. In the future, it is required to reduce the impedance of the electric circuit by increasing the speed of the electric signal, but in this case, according to the present invention, the thinly mounted cooling body can be formed into a three-dimensional structure by stacking it in layers. Three-dimensional mounting with cooling becomes possible.

実施例3 本発明の冷却構造体は超電導デバイスに応用できる。超
電導材料としてY-Ba-Cu-O系のベロプスカイト結晶体は8
2Kで超電導を示すことが知られている。したがつて沸点
72Kの液体窒素が冷媒として用いられる。このような超
電導デバイスを液体窒素で間接的に冷却する場合、本発
明の冷却体に液体窒素を流し冷却することによつて超電
導デバイスが動作する。
Example 3 The cooling structure of the present invention can be applied to a superconducting device. As a superconducting material, the Y-Ba-Cu-O-based perovskite crystal is 8
It is known to show superconductivity at 2K. Therefore, boiling point
72K liquid nitrogen is used as the refrigerant. When indirectly cooling such a superconducting device with liquid nitrogen, the superconducting device operates by flowing and cooling liquid nitrogen into the cooling body of the present invention.

〔発明の効果〕〔The invention's effect〕

本発明によれば次に示す2つの効果がある。 The present invention has the following two effects.

第1の効果としては、微細で接合が最も困難な半導体素
子の外部接続端子のはんだ付けが容易に行われ、しか
も、接合部に応力が少ないので破壊に対して強い信頼性
の高い接合部が得られる。はんだ付けにおける位置合せ
は半導体素子がフエースアツプのため上部より直接観察
することによつて行え、更にはんだ付けは同様に上部よ
り直接観察をしながら、レーザ、赤外線、キセノン等の
ビーム熱源によつて局部的に加熱が行える。更に接合後
の検査、補修等も上部より観察できるので容易である。
The first effect is that the external connection terminals of the semiconductor element, which are fine and the most difficult to join, can be easily soldered, and moreover, since there is little stress on the joint, a joint with high reliability against breakage is provided. can get. Alignment in soldering can be done by directly observing from above from the semiconductor element because it is a face-up, and soldering is also locally observed by beam heat source such as laser, infrared ray, xenon, etc. while observing directly from above. Can be heated. Furthermore, inspections and repairs after joining can be observed from the top, which is easy.

第2の効果としては、半導体素子の冷却効率が良好なこ
とである。すなわち、半導体素子の裏面より直接に冷却
体に伝達される。冷却体は微細に形成された冷却孔によ
つて効率よく外部に除去される。半導体素子と冷却体の
接合は電気的に絶縁を要する場合は薄い絶縁膜を介して
接合される。
The second effect is that the cooling efficiency of the semiconductor element is good. That is, the heat is directly transmitted from the back surface of the semiconductor element to the cooling body. The cooling body is efficiently removed to the outside by the finely formed cooling holes. When the semiconductor element and the cooling body are electrically connected to each other, they are connected via a thin insulating film.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例である半導体実装冷却構造体
の縦断面図、第2図は従来の実施例の縦断面図、第3図
は半導体素子と多層配線の接合にフレキシブルプリント
回路を用いた正面図、第4図は冷却体中の冷却孔及びス
ルーホール形成状況を示す横断面図である。 1:半導体素子、2:接合層、3:半導体素子端子、4:フレキ
シブルプリント回路、5:多層配線端子、6:絶縁板、7:金
属冷却体、8:冷却孔、9:スルーホール、10:多層配線、1
1:多層積層板、12:放熱体、13:はんだバンプ、14:絶縁
膜、15:応力緩和用切込み
FIG. 1 is a vertical cross-sectional view of a semiconductor mounted cooling structure according to an embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a conventional embodiment, and FIG. 3 is a flexible printed circuit for joining a semiconductor element and a multilayer wiring. FIG. 4 is a cross-sectional view showing a state of forming cooling holes and through holes in a cooling body. 1: semiconductor element, 2: bonding layer, 3: semiconductor element terminal, 4: flexible printed circuit, 5: multilayer wiring terminal, 6: insulating plate, 7: metal cooling body, 8: cooling hole, 9: through hole, 10 : Multilayer wiring, 1
1: Multilayer laminated board, 12: Heat radiator, 13: Solder bump, 14: Insulating film, 15: Notch for stress relaxation

───────────────────────────────────────────────────── フロントページの続き (72)発明者 加藤 光雄 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 服巻 孝 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuo Kato 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitate Manufacturing Co., Ltd.Hitachi Laboratory Ltd. Hitachi Research Laboratory

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】発熱を伴い間接的に冷却を要する半導体素
子を実装する冷却構造体において、該半導体素子の外部
接続用パツト形成面を上向きに配置し、該半導体素子の
下面は、内部を冷却媒体によつて冷却された金属冷却体
に接合され、該パツトはフレキシブルプリント回路によ
つて接合され、該フレキシブルプリント回路の外部端子
は、該金属冷却体のスルーホールを通して多層積層板に
接合されていることを特徴とする半導体実装冷却構造
体。
1. In a cooling structure for mounting a semiconductor element that requires heat generation and indirectly requires cooling, a pad forming surface for external connection of the semiconductor element is arranged upward, and a lower surface of the semiconductor element cools the inside. It is bonded to a metal cooling body cooled by a medium, the pad is bonded by a flexible printed circuit, and the external terminal of the flexible printed circuit is bonded to a multilayer laminate through a through hole of the metal cooling body. A semiconductor-mounted cooling structure characterized in that
【請求項2】該半導体素子の下面と該金属冷却体とが、
その間に、電気抵抗が高く熱伝導性の良好な層を挟み、
電気的に絶縁されて接合されている特許請求の範囲第1
項記載の半導体実装冷却構造体。
2. The lower surface of the semiconductor element and the metal cooling body,
In between, sandwich a layer with high electrical resistance and good thermal conductivity,
Claim 1 wherein they are electrically insulated and joined
The semiconductor mounted cooling structure as described in the item.
【請求項3】該半導体素子の外部接続用パツトと多層積
層板の端子とが、フレキシブルプリント回路によつては
んだにより接続されている特許請求の範囲第1項又は第
2項記載の半導体実装冷却構造体。
3. The semiconductor mounting cooling according to claim 1 or 2, wherein the external connection pads of the semiconductor element and the terminals of the multilayer laminate are connected by soldering with a flexible printed circuit. Structure.
【請求項4】該金属冷却体は、熱伝導の良好な金属板か
らなり、その中に通路が形成され、その通路には冷却媒
体が流されて冷却が行われ、通路の形成されない部分に
はその板厚方向にスルーホールが形成され、このスルー
ホール中には電気回路を通してフレキシブルプリント回
路と多層積層板とが電気的に接続される構造である特許
請求の範囲第1項〜第3項のいずれか1項に記載の半導
体実装冷却構造体。
4. The metal cooling body is made of a metal plate having good heat conduction, a passage is formed therein, and a cooling medium is flown in the passage to cool the metal cooling body, and a portion where the passage is not formed is formed. The through-hole is formed in the plate thickness direction, and the flexible printed circuit and the multilayer laminated board are electrically connected to each other through an electric circuit in the through-hole. The semiconductor mounted cooling structure according to any one of 1.
JP24253087A 1987-09-29 1987-09-29 Semiconductor mounted cooling structure Expired - Lifetime JPH0724294B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24253087A JPH0724294B2 (en) 1987-09-29 1987-09-29 Semiconductor mounted cooling structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24253087A JPH0724294B2 (en) 1987-09-29 1987-09-29 Semiconductor mounted cooling structure

Publications (2)

Publication Number Publication Date
JPS6486543A JPS6486543A (en) 1989-03-31
JPH0724294B2 true JPH0724294B2 (en) 1995-03-15

Family

ID=17090483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24253087A Expired - Lifetime JPH0724294B2 (en) 1987-09-29 1987-09-29 Semiconductor mounted cooling structure

Country Status (1)

Country Link
JP (1) JPH0724294B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2564645Y2 (en) * 1992-04-30 1998-03-09 太陽誘電株式会社 Hybrid integrated circuit device having heat-generating components
JP3339730B2 (en) * 1992-12-24 2002-10-28 忠弘 大見 Semiconductor device
JP4385783B2 (en) * 2004-02-10 2009-12-16 セイコーエプソン株式会社 Substrate, light source device and projector
US7432592B2 (en) * 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
JP4899903B2 (en) * 2007-02-05 2012-03-21 富士通株式会社 Printed wiring board, electronic device, and printed wiring board manufacturing method
JP5023735B2 (en) * 2007-02-21 2012-09-12 富士通株式会社 Cold plate and electronic device
JP5125242B2 (en) * 2007-06-14 2013-01-23 株式会社トッパンNecサーキットソリューションズ Semiconductor device mounting structure, printed wiring board, and manufacturing method thereof
CN112638029B (en) * 2020-12-23 2022-07-22 华为数字能源技术有限公司 Circuit board
EP4266363A1 (en) * 2022-04-21 2023-10-25 Airbus SAS Improved power component for electric or hybrid aircraft

Also Published As

Publication number Publication date
JPS6486543A (en) 1989-03-31

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