JPH07240688A - A/d conversion method - Google Patents

Abstract

PURPOSE:To made the interval of a reference level four times as wide as a conventional one even in the case where a resolution nearly as high as that of conventional ones is needed. CONSTITUTION:A reference level closest to an input analog signal level is selected, corresponding digital data are determined except for LSB and 2SB from the closest reference level, a difference subtracting the closest reference level form the input analog signal level is detected, the 2SB being the digital data are decided based on the polarity of the difference, the polarity representing the relation of quantity between the absolute value of the difference and the level of the LSB is obtained, and the digital data LSB are decided based on the exclusive OR between the polarity representing the relation of quantity and the 2SB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion method for converting an analog signal into a digital signal, and in particular, an A / D capable of increasing a resolution while widening a reference level (comparison reference value) interval. It relates to a conversion method.

[0002]

2. Description of the Related Art A conventional n-bit full parallel A / D conversion method for realizing A / D conversion will be described with reference to FIG. “0” to “(2 ⁿ −1) on the vertical axis in FIG.
“A” is a reference level with an interval of “a”, and “00 ... 0000” to “11 ... 1111” on the horizontal axis are n-bit digital values corresponding to each reference level.

The analog signal level input is 2
It is compared by ^n- 1 reference levels. The comparison result is different depending on whether the analog signal level is lower or higher than the reference level.

That is, in the method of determining the range above the reference level and below the upper reference level as the input level corresponding to the reference level,
For example, when the input analog signal voltage V _IN has a level of 3a ≦ V _IN <4a near the reference level 3a, the A / D-converted digital value corresponds to the reference level 3a of “00. ······················································, however, it is “00 ... 0010” corresponding to 2a when 2a ≦ V _IN <3a.

Differently from the above, it is also possible to adopt a method of determining the range above the reference level and below the upper reference level as the input level corresponding to the reference level. For example, when the input analog signal voltage V _IN has a level of 3a <V _IN ≦ 4a, the A / D converted digital value is set to “00 ... 0011” corresponding to the reference level 3a,
When 2a <V _IN ≦ 3a, “0 corresponding to 2a
0 ... 0010 ”.

FIG. 13 shows a block diagram of an n-bit fully parallel A / D converter. Reference _numeral 1 is an analog voltage input terminal, 2 is an input terminal for a reference voltage V _REF , 3 is a voltage dividing resistor group having a value of R or R / 2 for obtaining a reference voltage, and 4 is 2
^A group of ⁿ comparators with latches, 5 is a group of 2 ⁿ -1 AND gates, 6 is an encoder, 7 is a group of n-bit digital output terminals, and 8 is an overflow output terminal.

The n-bit fully parallel type A / D shown in FIG.
In the converter, the analog voltage input to input terminal 1
It is compared with each reference voltage in 2 ⁿ comparator groups 4, passes through 2 ⁿ -1 AND gate groups 5, a comparison level with respect to the input voltage is selected, and finally encoded by the encoder 6.

[0008]

However, this n
The full-bit parallel A / D conversion method has a problem that the higher the resolution is, the narrower the adjacent intervals of the reference levels are, and the critical reading accuracy is required in terms of the performance of the circuit element.

An object of the present invention is to solve the above-mentioned problems by making it possible to make the adjacent intervals of the reference levels wider than in the conventional case even when the same resolution as that in the conventional case is required. It is to provide a D conversion method.

[0010]

According to a first aspect of the present invention, in an n-bit fully parallel A / D conversion method for converting an input analog signal into an n-bit digital signal, a reference level closest to the input analog signal level is selected. The corresponding digital value from the closest reference level to the LSB.
And 2SB, the difference obtained by subtracting the closest reference level from the input analog signal level is detected, 2SB of the digital value is determined from the polarity of the difference, and the absolute value of the difference and the level of the LSB. The polarity representing the magnitude relationship with the
The LSB of the above digital value is determined from the exclusive OR with B.

A second invention is an n-bit fully parallel A / D conversion method for converting an input analog signal into an n-bit digital signal, where the LSB level is a, the reference level is 2a which is an odd multiple of 2a, 6a, 10a, ...
············· (2 ⁿ −2) a, the first subtraction is performed on the input analog signal and each reference level, and the first subtraction is performed.
Finds a first reference level at which the result of subtraction is the minimum level value, determines a digital value excluding LSB and 2SB from the n-bit digital value corresponding to the first reference level, and determines the above from the polarity of the first subtraction. The value of 2SB is determined, and the result of the first subtraction is absolute-valued. The value of twice the LSB level is subtracted from the first absolute-value conversion result, and the only negative one is selected. And the LSB level are added together, and the value of the LSB is determined from the exclusive OR of the polarity of the result and the value of the 2SB.

In the second invention, the input analog signal is used as a voltage signal, the voltage signal is converted into a current signal, and the converted current signal is subjected to a first subtraction with a current signal corresponding to each of the reference levels. Then, the first surplus current and the first shortage current are obtained and converted into binary signals of the first group for setting the high level and the low level of the voltage, and the first surplus current and the first surplus current are obtained. The second surplus current obtained as a result of the second subtraction with the absolute value of the undercurrent and the current corresponding to twice the LSB, and the second undercurrent are the high level and the low level of the second voltage.
The binary signal of the group is converted into the second surplus current, the second excess current, and the second excess current.
The third surplus current and the third shortage current obtained as a result of the third subtraction by selecting only one of the shortfall currents obtained and the current according to the LSB and the third shortfall current at a high voltage level. , A low-level first binary signal, and encodes the first group binary signal, the second group binary signal, and the first binary signal according to the input analog signal. N
It is preferable to obtain the digital value of the bits.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The n-bit fully parallel A / D conversion method of the present invention will be described below. FIG. 1 is a diagram illustrating the principle of the A / D conversion method. "2a" to "( ^2n- 2) on the vertical axis in FIG.
“A” is the reference level, and “00 ... 000” on the horizontal axis.
? ? "... 11? 111 ??" is an n-bit digital value indicating the level range of each reference level ± 2a (4a in total). That is, LSB (least significant bit) and 2SB (lower second bit) are unknown.

The reference levels are "2a" and "6".
a ”,“ 10a ”,“ 14a ”, ...,“ (2 ⁿ
-2) Like "a", the LSB level is "a",
It is an odd multiple of "2a". Therefore, for the levels of "2a" and above, the adjacent level interval is "4a" as compared with that shown in FIG.

Next, the processing method will be described. For example,
As shown in FIG. 2A, an n-bit digital value “0
Levels expected to have 0 ... 01110 "(specifically, exceeding reference level 14a and 15a
The following levels. However, the reference level 15a is not set. Consider the case where the analog signal A of) is input.

First, the input analog signal A is subtracted by the individual reference levels "a" to "(2 ⁿ -2) a". As a result, as shown in FIG. 2B, a positive subtraction result is obtained on the reference level side smaller than the level of the analog signal A, and a negative subtraction result is obtained on the larger reference level side. You can get only the number of reference levels. In addition, (a) of this FIG.
As in FIG. 1, (b) shows the level on the vertical axis and the digital value classification on the horizontal axis.

Next, the respective subtraction results are converted into absolute values (here, the negative level is converted into the positive level) to obtain the result as shown in FIG. Then, after this, the result obtained by subtracting 2a (twice the LSB level) from each absolute value conversion result is obtained as shown in FIG.

The negative result obtained by the above-mentioned FIG. 3B is theoretically one. FIG. 4A shows a state in which the negative result is selected and enlarged. Then, a subtraction result obtained by subtracting -a (LSB level) from this is obtained as shown in FIG.

The reference level corresponding to the minimum value obtained in FIG. 2B is "14a", and the digital value corresponding to this level is "00 ... 011?
? , And LSB and 2SB (lower second bit) are unknown.

Next, the values of 2SB and LSB are derived. Two
SB can be directly derived by the sign of the result of FIG. Here, the minimum level polarity of the subtraction result obtained in (b) of FIG. 2 is “positive”, which indicates that it exceeds the reference level “14a”. Therefore, "1" is applied as 2SB. As a result, the digital value corresponding to the input analog signal is "00 ... 0111?"
Becomes

Regarding LSB, the positive / negative of the result obtained in FIG. 4 (b) and the 2SB obtained as described above.
Derived by exclusive-NOR with. Since the result of FIG. 4B is negative, it is “0”, and therefore 2SB (= “1”).
The exclusive-NOR with is 0, that is, the LSB
= 0.

From the above, the digital value of the input analog signal A is determined to be "00 ... 01110". This value is 14a at the reference level. That is, the analog signal A exceeds the reference level 14a and is 15
This makes it clear that it is less than a (the reference level of 15a is actually not).

As described above, first, the reference level corresponding to the subtraction result of the minimum level is found from the subtraction results of the input analog signal A and the plurality of reference levels, and the digital value excluding LSB and 2SB is determined from this reference level. To be done. That is, it is determined that the level of the input analog signal A is within the range of the reference level ± 2a. Next, according to the polarity of the minimum level, if it is negative, the level of the input analog signal A is equal to or lower than the reference level (2SB =
If 0) is positive, it is determined that it is over (2SB = 1). Next, 2a is subtracted from the absolute value of the minimum level (it is always negative), and the polarity of the result obtained by subtracting -a from the subtraction result is obtained, and the polarity (positive = 1, negative = 0) and Two
The LSB is determined by exclusive-NOR with SB.

When the input analog signal is at or above the reference level full scale, the digital value of the reference level at the full scale is always output,
When the input analog signal is equal to or lower than the reference level of 0 (may be noise input, etc.), it is always 0
Output the digital value of the reference level of.

Further, in the above, a method is adopted in which the range exceeding the reference level (although some are not set) and below the upper reference level is determined as the input level corresponding to the reference level. It is also possible to employ a method of determining an input level corresponding to the reference level that is equal to or higher than the reference level and lower than the upper reference level.

As described above, according to the present invention, the resolution becomes equal to that of the conventional one while the reference level interval is four times that of the conventional one.

FIG. 5 and FIG. 6 are diagrams showing a concrete circuit for implementing the above A / D conversion method. Here, 4
1 illustrates a fully parallel A / D converter of bits. FIG. 5 shows an analog processing section 11 that compares the input analog signal with a plurality of reference levels and performs the above-described subtraction processing, and FIG. 6 shows a digital processing section 12 that performs encoding. Output signal X of FIG.
1 to X4, Y1 to Y4, and Z1 are the input signals in FIG.

In the analog processing section 11 of FIG.
Is an input terminal to which an analog signal voltage is input, 14 to 17 are V / I converters that convert the analog signal voltage into current signals, 18 to 21 are subtraction / absolute value conversion processors, and 22 to 25 are LSB level An odd multiple of double the level, ie "2
a ”,“ 6a ”,“ 10a ”, and“ 14a ”are sequentially set as reference current sources, 26 to 29 are 2SB level“ 2a ”current sources as subtraction signals, and 30 is a subtraction signal. A current source of LSB level "a", 31 is a selective subtraction absolute value converter, and 32 is a subtraction limiter.

In order to operate this, first, the input analog signal voltage V _IN is V / V to the current level I _{IN at} which the value is "0" at full scale and "2 ⁴ a = 16a" at zero. The I converters 14 to 17 perform linear conversion.

As a result, from the output currents of the V / I converters 14-17, the current "2" of the reference current sources 22-25.
The current resulting from the subtraction of “a”, “6a”, “10a”, and “14a” is sucked into or discharged from the subtraction / absolute value processor 18 to 21 as a surplus current or an undercurrent (FIG. 2 (b) processing).

At this time, when the current is discharged as an undercurrent, the voltage of the input terminals 18a to 21a of the subtraction / absolute value processing units 18 to 21 becomes low level, and when it is sucked in as an excess current, it becomes high level. And this voltage is
The data X1 to X4 are input to the digital unit 12 of.

Further, the subtraction / absolute value conversion processors 18-2
The surplus current and the insufficient current are converted into absolute values and unified into the suction current and output to each of the output terminals 18b to 21b of No. 1 (processing of (a) of FIG. 3). Then, this suction current and the 2SB level “2 of the current sources 26 to 29 connected thereto are
The surplus current and the undercurrent as a result of subtraction from the current of “a” are output to the selective subtraction absolute value digitizer 31 (processing of FIG. 3B).

The surplus current flowing into the selective subtraction absolute value converter 31 is only one of those corresponding to the subtraction / absolute value converters 18 to 21, and the rest are all undercurrent. Only when the surplus current is input, the selective subtraction absolute value digitizer 31 sucks the current having the same value as the surplus current from the output terminal 31e (the process of FIG. 4A). Further, on the input side of the selective subtraction absolute value converter 31, these surplus currents,
The insufficient current is converted into a high level voltage and a low level voltage, respectively, and is input to the digital section 12 of FIG. 6 as signals Y1 to Y4.

The output of the selective subtraction absolute value digitizer 31 is LS.
The reference current source 30 of the B level "a" subtracts (processing of FIG. 4B), and the push-pull of the excess current or the undercurrent is performed at the input of the subtraction limiter 32. A voltage level of the level is generated, and this is input to the digital unit 12 in FIG. 6 as Z1.

The digital section 12 shown in FIG.
49, inverters 50-55, OR gates 56-58,
It comprises NOR gates 59 to 70 and an exclusive NOR gate 71. Then, the digital values d1 to d obtained at the output terminals of the NOR gates 68 to 70 and the exclusive NOR gate 71
4 is a truth value shown in FIGS. 7 and 8 according to the signals X1 to X4, Y1 to Y4, and Z1.

FIG. 9 is a diagram showing a specific circuit of the subtraction / absolute value processor 18 shown in FIG. The other subtraction / absolute value conversion processors 19 to 21 have exactly the same configuration. The processor 18 includes a diode D1 which is turned on by a suction current signal, a diode D2 which is turned on by a discharge current signal, current sources 18c and 18d, current mirror connection transistors Q1 to Q4, current mirror connection transistors Q5 to Q8, current mirror connection transistors. Q
9 to Q12.

In this processor 18, the current sources 18c, 18
Set the current of d to the same "Io" value. Input terminal 1
When there is no current input / output to 8a, the current “Io” flows through all the transistors Q1 to Q12, and no current is input / output at the output terminal 18. Further, the input terminal 18a has a high impedance.

When the current "Ia" is drawn from the input terminal 18a, the diode D1 is turned on and the diode D2 is turned off so that the collector currents of the transistors Q9 to Q12 are "Ia + I".
"o" and the current "Ia" is absorbed from the output terminal 18b. At this time, the voltage V _{1 8 a1} of the input terminal 18a is the forward voltage of the diode D1 V _F1, the transistor Q10
When the base-emitter voltage of the base-emitter voltage of V _{BEQ1 0,} Q11 and V _{BE Q1 1,} the V _{1 8 a1} = 3V _{BE (where, V BE = V F1 = V} BEQ1 0 = V BEQ1 ₁ ).

When the current "Ib" is discharged from the input terminal 18a, the diode D1 is turned off and D2 is turned on, and the collector currents of the transistors Q5 to Q12 are "Ib + I".
Then, the current Ib is absorbed from the output terminal 18b in the same manner as above. In this way, the absolute value conversion process is performed. At this time, the voltage V _{1 8 a2} input terminal 18a is the forward voltage V _F2 of the diode D2, the base-emitter voltage of the transistor Q5 to the base-emitter voltage of V _BEQ5, Q8 and V _BEQ8, V _{1 8 a2} = V _REF -3V _BE (however, V _BE = V _F2 = V _BEQ5 = V _{BE 8} ).

[0040] Comparing the voltage V _{1 8 a1} and V _{1 8 a2} input terminal 18a, than by setting the V _REF appropriate, V _{1 8 a1}
Because> the V _{1 8 a2,} high level voltage during current sink at the input terminal 18a is, low-level voltage is obtained at the time of discharging.

FIG. 10 is a diagram showing a specific circuit of the subtraction limiter 32 shown in FIG. 5. The input transistors Q13, Q14,
It is composed of diode-connected transistors Q15 to Q18 and a diode D3.

The subtraction limiter 32 has an input terminal 32a.
When drawing the current from the transistor Q14, Q1
7. Base-emitter voltage of Q18 is V _{BEQ1 4} , V
_{Assuming BEQ1 7} and V _{BEQ1 8} , the voltage V _{3 2 a1 at} the input terminal 32a becomes V _{3 0 a1} = 3V _BE (where V _BE = V _{BEQ1 4} = V _{BEQ1 7} = V
_{BEQ1 8} ).

When the current is discharged from the input terminal 32a, the bases of the transistors Q13, Q15, Q16 are
When the emitter-to-emitter voltages are V _{BEQ1 3} , V _{BEQ1 5} , and V _{BEQ1 6} , the voltage V _{3 2 a2 at the} input terminal 32a becomes V _{3 2 a2} = V _REF -3V _BE (where V _BE = V _{BEQ1 3} = V _{BEQ1 5} = V
_{BEQ1 6} ).

Therefore, by appropriately setting the power supply voltage V _CC , it is possible to obtain the voltage V _{3 2 a1} > V _{3 2 a2,} and obtain the high level when the current is drawn and the low level when the current is drawn. You can

FIG. 11 is a diagram showing a specific circuit of the selective subtraction absolute value quantizer 31. This selective subtraction absolute quantizer 31
Four input terminals 31a to 31d and one output terminal 31e
And a transistor Q19 to Q22 to which a constant voltage Vf is applied by a constant voltage source 31f is provided inside, and a current mirror and a transistor including transistors Q23 to Q25 using the current Io of the constant current source 31g as a reference current. A current mirror composed of Q26 to Q28 is provided,
A current mirror composed of transistors Q29 to Q32 is also provided. D4 to D7 are diodes whose anodes are connected to the input terminals 31a to 31d.

In this circuit, when the diodes D4 to D7 are off, the current flowing through the transistors Q25 and Q28 and the current flowing through the transistors Q30 and Q31 become the same current (current Io of the current source 31g), and the output terminal 3
There is no current flowing in or out of 1e. First, the input terminals 31a-3
When the current input to 1d is a surplus current (inflow), the corresponding one of the diodes D4 to D7 is turned on and the corresponding one of the transistors Q19 to Q22 is turned off. Therefore, a current corresponding to the current flowing through the input terminals 31a to 31d flows from the output terminal 31e. When the currents of the input terminals 31a to 31d are insufficient current (outflow), the above is reversed, and the current of the output terminal 31e does not flow in or out.

The input terminals 31a to 31d supply the forward voltage of the diodes D4 to D7 to V _F and the bases of the transistors Q30 and Q32 when the surplus current flows (flows in).
To-emitter voltage and _{V BE 3 0, V BE 3} 2, ( the voltage at the other terminal is the same, representatively shown the voltage of the terminal 31a) voltage V _{3 1 a1} terminal excess current flows , V _{3 1 a1} = V _F + V _{BE 3 0} + V _{BE 3 2} = 3V _BE (where, V _F = V _{BE 3 0} = V _{BE 3 2} = V _BE ).

On the other hand, when an undercurrent flows (flows out),
Since any one or more transistors Q19~Q22 is turned on, when the transistor Q19 (although other transistors are similar representatively shows this) to the collector-emitter voltage of V _{CE 1 9,} is under current (the voltage of the other terminal is the same, representatively shown the voltage of the terminal 31a) voltage voltage V _{3 1 a2} terminal flowing becomes _{V 3 1 a2 = V CC -V} CE 1 9.

Therefore, by appropriately setting the power supply voltage V _CC , the voltage V _{3 1 a1} > V _{3 1 a2} can be obtained, and a high level logic level is obtained when there is an excess current and a low level logic level is obtained when there is an insufficient current. be able to.

[0050]

As described above, according to the present invention, the reference level interval can be quadrupled as compared with the conventional one, so that the number of comparators can be reduced. Further, even if the reference level is set at an interval of four times the conventional reference level in this way, the resolution can be maintained at the same level as the conventional one.

[Brief description of drawings]

FIG. 1 is a conversion explanatory diagram of an n-bit fully parallel A / D conversion method of the present invention.

FIG. 2 is an explanatory diagram of a process of an n-bit fully parallel A / D conversion method of the present invention.

FIG. 3 is an explanatory diagram of processing of an n-bit fully parallel A / D conversion method according to the present invention.

FIG. 4 is an explanatory diagram of processing of an n-bit fully parallel A / D conversion method according to the present invention.

FIG. 5 is a 4-bit fully parallel A / D according to an embodiment of the present invention.
It is a circuit diagram of an analog processing unit of the conversion circuit.

FIG. 6 is a 4-bit fully parallel A / D according to an embodiment of the present invention.
It is a circuit diagram of a digital processing unit of the conversion circuit.

FIG. 7 is an explanatory diagram of a truth value of the digital processing unit in FIG.

FIG. 8 is an explanatory diagram of a truth value of the digital processing unit in FIG.

9 is a specific circuit diagram of the subtraction / absolute value processor in the circuit of FIG.

10 is a specific circuit diagram of a subtraction limiter in the circuit of FIG.

11 is a specific circuit diagram of the selective subtraction absolute value quantizer in the circuit of FIG.

FIG. 12 is a conversion explanatory diagram of a conventional n-bit fully parallel A / D conversion method.

FIG. 13 is a block diagram of a conventional n-bit fully parallel A / D converter.

[Explanation of symbols]

11: analog processing unit, 12: digital processing unit, 13:
Input terminal, 14 to 17: V / I converter, 18 to 21: subtraction / absolute value conversion processor, 22 to 25: reference current source, 26 to 29: LSB current source, 30: 2 LSB current source, 31: selection Subtraction absolute quantizer, 32: Subtraction limiter, 4
1 to 49: buffer, 50 to 55: inverter, 56 to
58: OR gate, 59-70: NOR gate, 71: Exclusive NOR gate.

Claims (3)

[Claims] 1. An n-bit fully parallel A / D conversion method for converting an input analog signal into an n-bit digital signal, selects a reference level closest to the input analog signal level, and responds from the closest reference level. Determine the digital value excluding LSB and 2SB, detect the difference obtained by subtracting the closest reference level from the input analog signal level, determine 2SB of the digital value from the polarity of the difference, and determine the absolute value of the difference. An A / D conversion method, characterized in that a polarity representing a magnitude relationship with the level of the LSB is obtained, and the LSB of the digital value is determined from an exclusive OR of the polarity representing the magnitude relationship and the 2SB. 2. An n-bit fully parallel A / D conversion method for converting an input analog signal into an n-bit digital signal, where the LSB level is a and the reference level is 2a.
2a, 6a, 10a, ..., which is an odd multiple of (2 ⁿ
-2) As a, the first subtraction is performed with the input analog signal and each refanless level, the first reference level at which the result of the first subtraction becomes the minimum level value is found, and the first reference level is obtained. The digital value excluding LSB and 2SB is determined from the n-bit digital value corresponding to, the value of 2SB is determined from the polarity of the first subtraction, and the result of the first subtraction is converted into absolute value. The value that is twice the LSB level is subtracted from the value-valued result to select the only negative one, and the above is calculated from the exclusive OR of the polarity of the result of adding the selection result and the LSB level and the value of the 2SB. An A / D conversion method characterized by determining the value of LSB. 3. The input analog signal is used as a voltage signal, the voltage signal is converted into a current signal, and the converted current signal is subjected to a first subtraction with a current signal corresponding to each of the reference levels to obtain a first signal. Of the excess current and the first undercurrent and converting them into a binary signal of the first group for setting the high level and the low level of the voltage, the absolute value of the first excess current and the first undercurrent The second surplus current and the second undercurrent obtained as a result of the second subtraction with the value and the current corresponding to twice the LSB are converted into the high level and low level voltage binary signals of the second group. A third current obtained as a result of converting and selecting only one of the second surplus current and the second shortage current that can be obtained and performing a third subtraction with this and the current according to the LSB The surplus current and the third undercurrent are the high level and low level of the first voltage.
Of the first group of binary signals, the second group of binary signals, and the first binary signal of which the n-bit digital value corresponding to the input analog signal is converted. 3. The A / D conversion method according to claim 2, wherein