JPH07115368A - A/d converting method - Google Patents

Abstract

PURPOSE:To widen an adjacent interval of a reference level by subtracting an input analog signal level from the reference level being the nearest to the input analog signal level, and determining an LSB of a digital value from the polarity of its difference. CONSTITUTION:An input analog signal is converted to a digital signal of (n) bits. That is, reference levels 'a'-'(2<n>-1)a' being the nearest to an input analog signal level are selected, and from its nearest reference level, the corresponding digital values '00...0001'-'11...1111' are determined by regarding its LSB as unknown, a difference obtained by subtracting the input analog signal level from the nearest reference level is detected, and from the polarity of its difference, the LSB of the digital value is determined. In this case, it is desirable that the LSB of the digital value is set as '1', and to '0', when the input analog signal level exceeds the nearest reference level, and is under the latter, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion method for converting an analog signal into a digital signal, and in particular, an A / D capable of increasing a resolution while widening a reference level (comparison reference value) interval. It relates to a conversion method.

[0002]

2. Description of the Related Art A conventional n-bit full parallel A / D conversion method for realizing A / D conversion will be described with reference to FIG. “0” to “2 ^{n- 1} a” on the vertical axis of FIG. 8 indicates an interval of “a”.
And the reference level, "00 ... 000" on the horizontal axis
"0" to "11 ... 1111" are n-bit digital values corresponding to each reference level.

The analog signal level input is 2
Compared by ^{n- 1} reference levels. The comparison result is different depending on whether the analog signal level is lower or higher than the reference level. That is, the digital value to be obtained is the comparator reference level immediately below which this comparison result is inverted, and is the digital value corresponding to this reference level.

For example, when the input analog signal voltage V _IN is 3
If the level is a ≦ V _IN <4a, the A / D converted digital value is “00 ... 0011”, but 2a ≦ V
_{If IN} <3a, it is "00 ... 0010".

FIG. 9 shows a block diagram of an n-bit fully parallel A / D converter. Reference _numeral 1 is an analog voltage input terminal, 2 is an input terminal for a reference voltage V _REF , 3 is a voltage dividing resistor group having a value of R or R / 2 for obtaining a reference voltage, and 4 is 2 ^n−
One latched comparator group, 5 2 ^{n- 1} AND gate groups, 6 encoders, 7 n-bit digital output terminal groups, and 8 overflow output terminals.

In the n-bit fully parallel A / D converter shown in FIG. 9, the analog voltage input to the input terminal 1 is 2
^It is compared with each reference voltage in ^{n− 1} comparator groups 4, passes through 2 ^{n− 1} AND gate groups 5, a comparison level with respect to the input voltage is selected, and finally encoded by an encoder 6.

[0007]

However, this n
The full-bit parallel A / D conversion method has a problem that the higher the resolution is, the narrower the adjacent intervals of the reference levels are, and the critical reading accuracy is required in terms of the performance of the circuit element.

The object of the present invention is to solve the above problem by making it possible to make the adjacent intervals of the reference level wider than the conventional one, even when the resolution similar to the conventional one is required. It is to provide a D conversion method.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to select a reference level closest to an input analog signal level in an n-bit fully parallel A / D conversion method for converting an input analog signal into an n-bit digital signal. Then, the corresponding digital value from the closest reference level is determined as LSB unknown, the difference obtained by subtracting the input analog signal level from the closest reference level is detected, and the LSB of the digital value is determined from the polarity of the difference. This is achieved by an A / D conversion method characterized by deciding.

At this time, it is preferable that the LSB of the digital value is "1" when the input analog signal level is equal to or higher than the closest reference level and "0" when it is less than the closest reference level.

Another object of the present invention is an n-bit fully parallel type A for converting an input analog signal into an n-bit digital signal.
In the / D conversion method, if the LSB level is a, the reference levels are a, 3a, 5a ,.
ⁿ −1) As a, subtraction is performed between the input analog signal and the refanless level, the subtraction result is converted into an absolute value, and the minimum level value of the absolute value is obtained from the reference level, Corresponding to the reference level and LS
An n-bit digital value other than B is determined, and the LS of the n-bit digital value is determined according to the polarity of the result obtained by subtracting the LSB level from the minimum level value of the absolute value conversion result.
It is also achieved by an A / D conversion method characterized by determining B to 1 or 0.

At this time, the input analog signal is used as a voltage signal, the voltage signal is converted into a current signal, the converted current signal is subtracted from the current signal corresponding to each of the reference levels, and a surplus obtained as a result of the subtraction is obtained. Converts the current signal and undercurrent signal into a high-level or low-level binary signal of voltage,
The absolute value of the subtraction result is subtracted from the current signal corresponding to the LSB, and the surplus current signal and the undercurrent signal obtained as a result of the subtraction are converted into a high-level or low-level binary signal of voltage,
It is preferable to obtain an n-bit digital value corresponding to the input analog signal by encoding the former binary signal conversion value and the latter binary signal conversion value.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The n-bit fully parallel A / D conversion method of the present invention will be described below. FIG. 1 is an explanatory diagram of the A / D conversion method. In FIG. 1, “a” to “(2 ⁿ −1) a” on the vertical axis are reference levels and “00 ... 0001” on the horizontal axis.
“11 ... 1111” is an n-bit digital value corresponding to each reference level.

The reference levels are "a" and "3".
a ”,“ 5a ”,“ 7a ”, ...,“ (2 ⁿ
For levels exceeding "a" such as "-1) a", the adjacent level intervals are doubled as compared with those shown in FIG. That is, an odd multiple of "a" is used as the reference level, and the level interval is 2a.

Next, the processing method will be described. For example,
As shown in (a) of FIG. 2, levels expected to have an n-bit digital result of "00 ... 0111" [specifically, reference levels "7a" and "8a"].
(However, there is no reference level such as "8a".) Consider a case where an analog signal A of an intermediate level] is input.

First, the analog signal A is subtracted by the individual reference levels "a" to "(2 ⁿ -1) a". As a result, as shown in FIG. 2B, a positive subtraction result is obtained on the reference level side smaller than the analog signal A level, and a negative subtraction result is obtained on the reference level side larger than the analog signal A level. These subtraction results are obtained by the number of reference levels.
2A to 2D, the vertical axis represents level and the horizontal axis represents digital value classification.

Next, the respective subtraction results are converted into absolute values (here, the negative level is converted into the positive level) to obtain the result as shown in FIG. 2 (c). Then, after this, the LSB level (“a” in FIG. 2) is calculated based on the results of individual excellence.
The result of subtracting is obtained as shown in FIG.

Since the absolute value conversion is performed as described above,
In the previous stage, the same result can be obtained by subtracting each reference level by the analog signal A, in addition to subtracting the analog signal A by each reference level.

From the above, the subtraction result of the minimum level is determined, and the subtraction result of this minimum level is (the minimum level is a
Less than) always has a negative value. Here, the digital value corresponding to the reference level from which this minimum level is obtained is "00 ... 0111" described above, but here, the LSB is unknown and "00 ... 011".
? ".

Next, this LSB is determined to be "1" when the minimum level of the subtraction result before being made an absolute value is positive, and "0" when it is negative. Positive means that the level of the input analog signal is higher than the reference level closest to the level of the input analog signal, and negative means that the level is low. In this example, since it is positive, it is “1”. From the above, the digital value is “00 ... 011” after all.
1 ”.

In this way, the reference level "7a" closest to the level of the input analog signal A is first determined,
The digital value corresponding to the reference level "7a" is determined as "00 ... 011?". And
When the level of the input analog signal A is equal to or higher than the reference level “7a”, the digital value “00 ... 0111” corresponding to the reference level “7a”.
However, when the reference level is less than “7a”,
The digital value becomes "00 ... 0110".

When the level of the input analog signal coincides with the intermediate level between two vertically adjacent reference levels, that is, when there are two closest reference levels, "a" is given to the upper reference level. "
However, the reference level on the lower side becomes larger by “a”. At this time, it is necessary to decide which one of the reference levels on the upper side and the lower side belongs to, but this is decided in advance. .

In the above case, for example, when it is determined in advance that it belongs to the higher reference level, the LSB of the digital value corresponding to the higher reference level is determined.
Is set to "0". On the contrary, when it is determined in advance that the digital value belongs to the lower reference level, the LSB of the digital value corresponding to the lower reference level is set to "1".

As described above, in the present invention, the level of the input analog signal is intermediate between the adjacent level intervals (2a) of the reference level by performing the subtraction process of the level corresponding to the LSB after the absolute value conversion process. It is determined whether it is in the upper area, the lower area, or just the middle portion of. As a result, in the present invention, the reference level interval is set to the conventional 2
The resolution will be the same as the conventional one, even though it is doubled.

When the input analog signal is at or above the reference level full scale, the digital value of the reference level at the full scale is always output,
Whenever the input analog signal is below the reference level of zero, the digital value of the reference level of zero is output.

FIG. 3 and FIG. 4 are diagrams showing a concrete circuit for implementing the above A / D conversion method. Here, 3
1 illustrates a fully parallel A / D converter of bits. FIG. 3 shows an analog processing unit 11 that compares input analog signals at a plurality of reference levels and performs the above-described subtraction processing, and FIG. 4 shows a digital processing unit 12 that performs encoding. Output signal X of FIG.
1 to X4 and Y1 to Y4 are the input signals in FIG.

In the analog processing section 11 of FIG.
Is an input terminal to which an analog signal voltage is input, 14 to 17 are V / I converters that convert the analog signal voltage into current signals, 18 to 21 are subtraction / absolute value conversion processors, and 22 to 25 are LSB levels. odd multiple of "a", that is, "a", "3"
Reference current sources whose levels are sequentially set to "a", "5a", and "7a", and 26 to 29 are LS as subtraction signals.
A current source of B level "a", 30 is a subtraction limiter.

[0028] Now, in order for this to work, first the input analog signal voltage V _IN is "0" during a full scale, to "2 ⁿ a = 8a" values become current level I _IN of the midnight, the V
The / I converters 14 to 17 perform linear conversion.

As a result, from the output currents of the V / I converters 14-17, the current "a" of the reference current sources 22-25,
The current resulting from subtraction of “3a”, “5a”, and “7a” is pushed or sucked from the subtraction / absolute value processor 18 to 21 as a surplus current or an undercurrent. pull)

At this time, when the current is discharged as an undercurrent, the voltage at the input terminals 18a to 21a of the subtraction / absolute value processing units 18 to 21 becomes a low level, and when it is absorbed as an excess current, it becomes a high level. And this voltage is
The data X1 to X4 are input to the digital unit 12 of.

Further, the subtraction / absolute value conversion processors 18-2
The surplus current and the shortage current are converted into absolute values and output as suction currents to the output terminals 18b to 21b of No. 1. Then, the sink current and the sink current as a result of subtraction between the sink current and the current sources 26 to 29 of the LSB level “a” connected thereto are input to the subtraction limiter 30 and low level voltages are respectively supplied thereto. It is converted into a high level voltage and is input to the digital section 12 of FIG. 4 as signals Y1 to Y4.

The digital section 12 shown in FIG.
1-38, inverters 39-44, or gates 45-4
7 and NOR gates 48 to 59. The digital values d1 to d obtained at the output terminals of the NOR gates 57 to 59
3 becomes the truth value shown in FIG. 5 according to the signals X1 to X4 and Y1 to Y4.

FIG. 6 is a diagram showing a specific circuit of the subtraction / absolute value processor 18 shown in FIG. The other subtraction / absolute value conversion processors 19 to 21 have exactly the same configuration. The processor 18 includes a diode D1 which is turned on by a suction current signal, a diode D2 which is turned on by a discharge current signal, current sources 18c and 18d, current mirror connection transistors Q1 to Q4, current mirror connection transistors Q5 to Q8, current mirror connection transistors. Q
9 to Q12.

In this processor 18, the current sources 18c, 18
Set the current of d to the same "Io" value. Input terminal 1
When there is no current input / output to 8a, the current “Io” flows through all the transistors Q1 to Q12, and no current is input / output at the output terminal 18. Further, the input terminal 18a has a high impedance.

When the current "Ia" is drawn from the input terminal 18a, the diode D1 is turned on and the diode D2 is turned off so that the collector currents of the transistors Q9 to Q12 are "Ia + I".
"o" and the current "Ia" is absorbed from the output terminal 18b. At this time, the voltage V _{1 8 a1} of the input terminal 18a is the forward voltage of the diode D1 V _F1, the transistor Q10
When the base-emitter voltage of the base-emitter voltage of V _{BEQ1 0,} Q11 and V _{BE Q1 1,} the V _{1 8 a1} = 3V _{BE (where, V BE = V F1 = V} BEQ1 0 = V BEQ1 ₁ ).

When the current "Ib" is discharged from the input terminal 18a, the diode D1 is turned off and D2 is turned on, and the collector currents of the transistors Q5 to Q12 are "Ib + I".
Then, the current Ib is absorbed from the output terminal 18b in the same manner as above. In this way, the absolute value conversion process is performed. At this time, the voltage V _{1 8 a2} input terminal 18a is the forward voltage V _F2 of the diode D2, the base-emitter voltage of the transistor Q5 to the base-emitter voltage of V _BEQ5, Q8 and V _BEQ8, V _{1 8 a2} = V _REF -3V _BE (however, V _BE = V _F2 = V _BEQ5 = V _{BE 8} ).

[0037] Comparing the voltage V _{1 8 a1} and V _{1 8 a2} input terminal 18a, than by setting the V _REF appropriate, V _{1 8 a1}
Because> the V _{1 8 a2,} high level voltage during current sink at the input terminal 18a is, low-level voltage is obtained at the time of discharging.

FIG. 7 is a diagram showing a specific circuit of the unit circuit of the subtraction limiter 30 shown in FIG. The subtraction limiter 30 is configured by connecting four unit circuits shown in FIG. 7 in parallel. This unit circuit includes input transistors Q13 and Q14, diode-connected transistors Q15 to Q18, and a diode D3.
Consists of.

In this unit circuit, when the current is absorbed from the input terminal 30a, the transistors Q14, Q17, Q
18 base-emitter voltages are V _{BEQ1 4} , V _{BEQ1 7} ,
If V _{BE Q1 8 then} the voltage V at the input terminal 30a
_{3 0 a1} becomes a V _{3 0 a1} = 3V _{BE (However, V BE = V BEQ1 4 =} V BEQ1 7 = V
_{BEQ1 8} ).

When the current is discharged from the input terminal 30a, the bases of the transistors Q13, Q15, Q16 are
To-emitter voltage _{V BEQ1 3, V BEQ1 5,} V BEQ1 6 to the voltage V _{3 0 a2} of the input terminal 30a becomes a _{V 3 0 a2 = V REF -3V} BE ( where, V _BE = V _{BEQ1 3} = V _{BEQ1 5} = V
_{BEQ1 6} ).

[0041] Thus, by setting the power supply voltage V _CC as appropriate, it is possible to obtain a voltage _{V 3 0 a1> V 3 0} a2, high level when current sink, to obtain a low-level logic level when the discharging You can

[0042]

As described above, according to the present invention, the reference level interval can be doubled as compared with the conventional one, so that the number of comparators can be reduced. Number of comparators when setting reference levels at equal intervals of conventional LSB level 2 ⁿ −
The number is 2 ^(n-1) less than one. For example, n =
In the case of 4 bits, in the conventional case, 15 comparators are required, but in the present invention, 8 comparators are required.

Further, even if the reference level is set at an interval twice as large as that of the conventional reference level, the resolution can be maintained at the same level as the conventional resolution.

[Brief description of drawings]

FIG. 1 is a conversion explanatory diagram of an n-bit fully parallel A / D conversion method of the present invention.

FIG. 2 is an explanatory diagram of a process of an n-bit fully parallel A / D conversion method of the present invention.

FIG. 3 is a 3-bit fully parallel A / D according to an embodiment of the present invention.
It is a circuit diagram of an analog processing unit of the conversion circuit.

FIG. 4 is a 3-bit fully parallel A / D according to an embodiment of the present invention.
It is a circuit diagram of a digital processing unit of the conversion circuit.

5 is an explanatory diagram of a truth value of the digital processing unit in FIG.

6 is a specific circuit diagram of the subtraction / absolute value processor 18 in the circuit of FIG.

7 is a specific circuit diagram of a unit circuit of the subtraction limiter 30 in the circuit of FIG.

FIG. 8 is a conversion explanatory diagram of a conventional n-bit fully parallel A / D conversion method.

FIG. 9 is a block diagram of a conventional n-bit fully parallel A / D converter.

[Explanation of symbols]

11: analog processing unit, 12: digital processing unit, 13:
Input terminal, 14 to 17: V / I converter, 18 to 21: subtraction / absolute value conversion processor, 22 to 25: reference current source, 26 to 29: LSB current source, 30: subtraction limiter, 3
1-38: Buffer, 39-44: Inverter, 45-
47: OR gate, 48-59: NOR gate.

Claims (4)

[Claims] 1. In an n-bit fully parallel A / D conversion method for converting an input analog signal into an n-bit digital signal, a reference level closest to the input analog signal level is selected, and the reference level closest to the reference level is selected. A / D conversion, wherein a digital value to be set is determined excluding the LSB, a difference obtained by subtracting the input analog signal level from the closest reference level is detected, and the LSB of the digital value is determined from the polarity of the difference. Method. 2. The LS of the digital value when the input analog signal level is equal to or higher than the closest reference level.
The A / D conversion method according to claim 1, wherein B is "1", and when it is less than "0". 3. An n-bit fully parallel A / D conversion method for converting an input analog signal into an n-bit digital signal, where LSB level is a, reference level is a,
3a, 5a, ..., (2 ⁿ -1) a, subtraction is performed between the input analog signal and the reference level, and the subtraction result is converted into an absolute value, and the absolute value conversion result. From the reference level that obtains the minimum level value of the above, determine an n-bit digital value that corresponds to the reference level and excludes the LSB,
An A / D conversion method, characterized in that the LSB of the n-bit digital value is determined to be 1 or 0 according to the polarity of the result of subtracting the SB level. 4. A surplus current obtained by subtracting the input analog signal as a voltage signal, converting the voltage signal into a current signal, subtracting the converted current signal from a current signal corresponding to each of the reference levels. Signal and undercurrent signal are converted into a high-level or low-level binary signal of voltage, the absolute value of the subtraction result is subtracted from the current signal according to the LSB, and the surplus current signal obtained by the subtraction result is insufficient. The current signal is converted into a high-level or low-level binary signal of voltage, and the former binary signal converted value and the latter binary signal converted value are coded to obtain an n-bit signal corresponding to the input analog signal. The A / D conversion method according to claim 3, wherein a digital value is obtained.