JPH07240638A - High frequency amplifier - Google Patents

Abstract

PURPOSE:To amplify high frequency signals over a wide band with low waveform distortion and low power consumption by connecting a specified impedance matching circuit for the distortion of a field-effect transistor to the transistor. CONSTITUTION:The source of the field-effect transistor (FET) Q as an active element is connected to a ground terminal, the impedance matching circuit Ain composed of a coil L1 and a capacitor C1 is connected to the gate and the impedance matching circuit Aout composed of the coil L2, and the capacitor C2 is connected to the drain. Then, DC bias is set to let the FET Q perform the amplification operation of an AD class. In this case, the respective output impedances Z11 and Z12 of the impedance matching circuits Ain and Aout are decided so as to match with the output impedance when power addition efficiency becomes maximum to the fixed third distortion of the FET Q. Thus, the distortion and adjacent channel leakage power are reduced and the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency amplifier for amplifying a high frequency signal over a wide band with low waveform distortion and low power consumption.

[0002]

2. Description of the Related Art In recent years, by using a microwave amplifying transistor having a large electron mobility such as GaAsFET, a microwave amplifier up to several tens of GHz can be realized by a semiconductor integrated circuit (IC or the like). I can do it now.

However, since such a transistor is a non-linear active element, when the input power P _in is small, its output power P _out is proportional to the input power P _in ,
_Moreover , the frequency component of the signal of the output power P _out is the input power P _in
However, as the input power P _in becomes larger, the output power P _out becomes equal to the power P _{f at} the frequency _f as well as the frequency (2 ×) due to the second-order waveform distortion.
f) power P _2f and frequency due to third-order waveform distortion (3 ×
The power P _{3f in} f) increases sharply.

Such a high-order harmonic component (particularly, a harmonic component due to a third-order waveform distortion) causes a serious problem such as interference between adjacent channels in the field of wireless communication. Taking the field of mobile phones as an example, in a fixed station for wireless communication such as a base station, instead of amplifying for each signal in a predetermined frequency band assigned to each channel, a wideband signal over a large number of channels (of different frequencies) is used. By amplifying multiple signals at once with one high-frequency amplifier,
Since the system is configured to greatly reduce the number of high-frequency amplifiers, third-order intermodulation distortion is increased due to the presence of third-order waveform distortion, which causes interference between adjacent channels. Also, in mobile phones that apply digital modulation,
Generation of adjacent channel leakage power due to such high-order intermodulation distortion is also a serious problem.

Therefore, in the conventional communication technique, in order to reduce the third-order intermodulation distortion, the FE having a large saturated output power is used.
This FE is used with T (field effect transistor).
T was used in a small output power range. The method of using the FET in such a small output power range is called back-off.

[0006]

However, since this back-off technique uses the FET only in a small output power range, linearity can be obtained and the third-order intermodulation distortion can be reduced. Since the set operating power supply range is not effectively used, the power consumption is relatively increased. Such problems will be described in detail with reference to FIG.

FIG. 9 is a principle diagram for explaining the backoff technique. In the figure, the horizontal axis represents the input power (unit: dBm) of the high frequency amplifier, and the vertical axis represents the output power (unit: dBm) and power added efficiency (unit:%), and the input power of the signal of frequency f. Fundamental wave output power P _f and third-order intermodulation distortion output power P with respect to increase / decrease of P _in
Changes in _IM3 and power added efficiency η _add are shown. The power added efficiency η _add is the DC power P _DC supplied from the power source.
Evaluation value indicating how much is converted to microwave power (that is, a measure of the quality of FET power amplification characteristics)
And η _add = 100 × (P _f −P _in ) / P _DC (%).

As shown in FIG. 9, when the input power P _in gradually increases, the fundamental wave output power P _f becomes a certain input power P _f.
Up to _in1 , it increases linearly in proportion to the constant increase rate, and beyond that, the increase rate decreases non-linearly,
It saturates at a certain input power P _in2 . On the other hand, the third-order intermodulation distortion output power P _IM3 also has similar output power characteristics as the input power P _in1 increases. However, the increase rate G _IM3 increase rate G _f and the third-order intermodulation distortion output power P _IM3 output power P _f of the linear increase range, since the relationship of G _f <G _IM3, these growth rates G _f, Output power P based on G _IM3
An intersection IP3 is obtained by extending _f , P _IM3 , and the upper limit of the operating power region (dynamic range) is determined by the output power P _IP3 corresponding to this intersection (referred to as an intercept point) IP3.

The power added efficiency η _add is as shown in the figure.
It becomes the maximum value η _{MAX at a} certain input power P _in2 . Therefore, if the input power P _in that satisfies the condition that the power added efficiency η _add is η _MAX is supplied, the DC power P _DC is most effectively used. However, the basic output power P _f and the third-order intermodulation distortion output power P _IM3 when η _add = η _MAX
The difference ΔP _out does not satisfy the noise resistance characteristic defined by the communication standard or the like. Therefore, the third-order intermodulation distortion output power P
_The third-order distortion IM3 (= P _f −P _IM3 ) is, for example, −40 when the reduction of _IM3 is the main and the optimization of the power added efficiency η _{add is} the secondary.
The input power P _in is limited within an upper limit range that satisfies the standard condition of dBc. In the figure, the upper limit of this input power is indicated by P _in1 , but the power added efficiency η _{add at} this time is shown.
Becomes η _IM3 , and η _IM3 <η _MAX . Then, the input power when η _add = η _MAX (P _{in2 in} the figure) and the input power P when η _add = η _IM3
Since the power supply power for the difference BO (= P _in2 −P _in1 ) from _in1 is not effectively used, the power consumption is relatively increased.

As described above, in the conventional high frequency amplifier, in order to reduce the third-order intermodulation distortion caused by the wide band amplification, the power consumption is not sufficiently reduced, and an effective technical means is also taken. There wasn't.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a high frequency amplifier for amplifying a high frequency signal over a wide band while satisfying both low waveform distortion and low power consumption. To aim.

[0012]

In order to achieve such an object, the present invention provides a high-frequency amplifier having a field-effect transistor which maximizes the power-added efficiency with respect to a constant third-order distortion of the field-effect transistor. An impedance matching circuit that matches the output impedance at that time is connected to the field effect transistor. Also,
The field effect transistor is configured to be biased in a state in which the power added efficiency is maximized with respect to a constant third-order distortion. Further, an impedance matching circuit that matches the output impedance when the power added efficiency is maximum with respect to the constant adjacent channel leakage power of the field effect transistor is connected to the field effect transistor.
Further, the field effect transistor is configured to be biased in a state where the power added efficiency is maximized with respect to a constant adjacent channel leakage power.

[0013]

According to the high frequency amplifier of the present invention having such a configuration, the impedance circuit is provided and the bias of the field effect transistor is set based on the condition that the power added efficiency with respect to the distortion and the adjacent channel leakage power is maximized. Therefore, a high-frequency amplifier capable of reducing distortion and adjacent channel leakage power and reducing power consumption is realized.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. The circuit configuration will be described with reference to FIG. In this embodiment, a GaAs MESFET Q is used as an active element, its source is connected to the ground terminal, and its gate is coil L _1.
Impedance matching circuit A _in consisting of capacitor and capacitor C ₁
Is connected, the impedance matching circuit A _{out including a} coil L ₂ and a capacitor C ₂ is connected to the drain, and a direct current bias (operating point) is set so that the FET Q performs class AB amplification operation.

The impedance matching circuit A
The output impedances Z ₁₁ and Z ₂₂ of _in and A _out are
It is determined according to the following design principles (conditions). In order to clarify this design principle, explanations and experiments conducted by the present inventor will be explained while comparing and weighing them.

The matching with the load impedance is taken into consideration as the largest cause of the high-order distortion of the FET Q.
That is, the load circuit and the FET connected in cascade to the FET Q
If there is a mismatch with the output terminal of Q, the output signal (microwave) of the FET Q is reflected and returned to the FET Q, and distortion due to interference occurs. Therefore, the relationship between the output power P _out of the FET Q and its output impedance Z _QO (hereinafter, P
_out vs. Z _QO ), the relationship between the power P _{IP3 of} the third-order distortion intercept point IP3 (see FIG. 9) and the output impedance Z _QO (hereinafter referred to as P _IP3 vs Z _QO ), and the adjacent channel leakage power P _CT . The relationship between the output impedance Z _QO (hereinafter referred to as P _{CT and} Z _QO ) was measured. Figure 2 shows (P
_out vs. Z _QO ), FIG. 3 shows the result of measurement (P _IP3 vs. Z _QO ), and FIG. 4 shows the result of measurement (P _CT vs. Z _QO ).

First, the actual measurement result shown in FIG.
It is a plot of the change of the output impedance Z _QO when the frequency of the input power P _in is changed on the Smith chart using _out as a parameter. Therefore, as shown in the figure, a contour-line measurement result is obtained for each different output power P _out , and the output impedance Z _Pmax when the output power P _out reaches the maximum value P _max is set to the first determination condition (Z. _QO
= Z _Pmax ).

The actual measurement results shown in FIG. 3 are obtained by plotting on the Smith chart the change in the output impedance Z _QO when the frequency of the input power P _in is changed with the power P _IP3 at the third-order distortion intercept point as a parameter. Is.
Therefore, as shown in the figure, a contour-shaped measurement result is obtained for each different power P _IP3 , and the power P _IP3 is the maximum value P
The output impedance Z _Ipmax when the _Ipmax, the second determination condition (Z _QO = Z _IPmax).

The actual measurement result shown in FIG. 4 is a plot of the change in the output impedance Z _QO when the frequency of the input power P _in is changed on the Smith chart using the adjacent channel leakage power P _CT as a parameter. In FIG. 4, the adjacent channel leakage power P _CT is set for every 10 dBc in the range of −20 dBc to −60 dBc. Therefore, as shown in the figure, a contour-shaped result is obtained for each different adjacent channel leakage power P _CT , and the output impedance Z _CTmin when the power P _CT becomes the minimum value P _CTmin (= −60 dBc) Decision condition 3 (Z _QO = Z
_CTmin ).

Here, in a general power amplifier design,
The output impedance Z _QO = Z _Pmax that can _{maximize the} output power is adopted. That is, the first determination condition is applied to determine the circuit constant of the impedance matching circuit A _out . When designing a high frequency amplifier for reducing third-order distortion and adjacent channel leakage power,
The output impedance Z _QO = Z _IPmax or Z _QO = Z _CTmin shown in the third determination condition or is determined to determine the circuit constant of the impedance matching circuit A _out .

However, the present invention is intended to reduce the third-order distortion and the adjacent channel leakage power, and also to reduce the power consumption. Therefore, if these decision conditions are independently adopted, the optimum high frequency is obtained. An amplifier cannot be realized. This is clear from the experimental results shown in FIG. Fig. 5 shows the current I _DS flowing in the drain of FET Q and the FET
It is an actual measurement result showing the relationship of the output impedance Z _QO of Q. That is, the current I _DS (I
Input power P with _DS1 ≤ I _DS ≤ I _DS4 ) as a parameter
Output impedance Z _QO when _in frequency is changed
It is a plot of the change of the number on the Smith chart. As is clear from the figure, when a signal with a large input power P _in is input, the output impedance Z _QO of the FET Q changes and the drain current I _DS also changes, so the circuit constant of the impedance matching circuit A _out is set to 3 output impedance Z _Ipmax the power P _IP3 of distortion intercept point may be the maximum value P _Ipmax (second determination condition)
_{Alternatively} , even if the output impedance Z _CTmin (third determination condition) that can make the adjacent channel leakage power P _{CT the} minimum value P _CTmin is adopted, the power consumption cannot be sufficiently reduced. Therefore, the present invention further provides the impedance matching circuit A _out based on the optimum conditions described below.
Has been decided.

The principle for obtaining the first optimum condition will be described with reference to FIG. FIG. 6 shows the third-order intermodulation distortion output power P.
It is the result of actually measuring the relationship between the power added efficiency η _add with respect to _IM3 (see FIG. 9) and the output impedance Z _QO and plotting it on the Smith chart. That, -40 dB difference IM3 fundamental wave output power P _f and the third-order intermodulation distortion output power P _IM3
Fixed to c, the power added efficiency η _add (6% ≦ η _add ≦ 1
2%) as a parameter, the change in output impedance Z _QO with respect to the maximum output power is shown.

In this embodiment, the power added efficiency η
The output impedance Z _op1 when _add has the maximum value is determined as the first optimum condition, and each element constant of the impedance matching circuit A _out is determined so that the impedance Z ₂₂ matches the output impedance Z _op1 . If the impedance matching circuit A _out is designed based on this first optimum condition, both power consumption and third-order intermodulation distortion output power can be reduced at the same time.

In this embodiment, IM3 = -40 dB
The condition is c, but the present invention is not limited to this. That is, the reason that IM3 = -40 dBc is based on the specific standard in the wireless communication system. Next, the second optimum condition will be described with reference to FIG. Figure 7
It is the result of actually measuring the relationship between the power added efficiency η _add with respect to the adjacent channel leakage power P _CT (see FIG. 9) and the output impedance Z _QO and plotting it on the Smith chart. That is,
Adjacent channel leakage power P _CT is fixed at −60 dBc,
It shows a change in the output impedance Z _QO with respect to the maximum output power when the power added efficiency η _add (10% ≦ η _add ≦ 40%) is used as a parameter.

Then, in this embodiment, the output impedance Z _op2 when the power added efficiency η _add becomes the maximum value.
Is defined as the second optimum condition, and each element constant of the impedance matching circuit A _out is determined so that the impedance Z ₂₂ matches the output impedance Z _op2 . When the impedance matching circuit A _out is designed based on this second optimum condition, both power consumption and adjacent channel leakage power can be reduced at the same time.

In this embodiment, P _CT = -60 dBc
However, the present invention is not limited to this.
That is, P _CT = −60 dBc is based on a specific standard in the wireless communication system, and may be changed according to other standards or design specifications. That is, in a specific P _CT , the impedance matching circuit A _out can be optimized by _obtaining the output impedance Z _op2 corresponding to the maximum power added efficiency η _add based on the actual measurement result shown in FIG. Becomes

Further, the third optimum condition will be described with reference to FIG. FIG. 8 shows an actual measurement of the relationship between the DC bias dependence of the FET Q and the power added efficiency η _add.
The drain-source voltage V _{DS of} Q (V _DS is set to 8 V and 7.5 V) is used as a parameter, and IM3
4 shows changes in the output power P _out and the power added efficiency η _add with respect to the gate-source voltage V _gs of the FET Q under fixed conditions of = -40 dBc and P _CT = -60 dBc. Then, the gate-source voltage V _gsop when the power added efficiency η _add becomes maximum is _determined as the optimum bias condition (third optimum condition) of the FET Q.

The output power P at IM3 = -40 dBc
_With the output power P _OUT ′ at _OUT and P _CT = −60 dBc,
P _OUT 'has increased by about 6 dB, and P _CT =-
The power added efficiency of 7 _add ′ at 60 dBc is improved by about 4 times.

When the DC bias (operating point) is set based on the third optimum condition, the high frequency amplifier becomes a class AB amplifier. Further, in this embodiment, IM3 = -40d
Although Bc is used as a condition, it may be changed according to other standards or design specifications.

Then, as shown in FIG. 1, by connecting the impedance matching circuits A _in and A _out satisfying the above first to third optimum conditions to the FET Q, a high frequency amplifier with low power consumption and distortion is obtained. Can be realized. The impedance matching circuit A _in is FET Q
Is a circuit determined on the basis of the above-mentioned first to third optimum conditions obtained with respect to another FET (not shown) provided on the upstream side.

Further, the impedance matching circuit A _in , A _out of this embodiment shown in FIG. 1 is an example, and another circuit configuration can be used as long as it corresponds to the output impedance satisfying the above optimum conditions. Good.

[0032]

As described above, according to the high frequency amplifier of the present invention, the field effect transistor for high frequency amplification is used, and the condition in which the power added efficiency with respect to the distortion of the field effect transistor and the adjacent channel leakage power is maximized. Since the impedance matching circuit that satisfies the above condition is provided in the field effect transistor and the bias of the field effect transistor is set, distortion and adjacent channel leakage power can be reduced and a high frequency amplifier with reduced power consumption can be provided. . Further, it is possible to provide a high frequency amplifier under more optimal operating conditions as compared with a high frequency amplifier obtained based on the back-off technique.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment according to the present invention.

FIG. 2 is a measurement diagram showing a relationship between output power and output impedance in a high frequency amplifier.

FIG. 3 is a measurement diagram showing a relationship between power and output impedance at an interceptor point in a high frequency amplifier.

FIG. 4 is a measurement diagram showing a relationship between adjacent channel leakage power and output impedance in a high frequency amplifier.

FIG. 5 is a measurement diagram showing the relationship between drain current and output impedance in a high frequency amplifier.

FIG. 6 is a measurement diagram showing a relationship between power added efficiency and output impedance in a high frequency amplifier when IM3 = −40 dBc.

FIG. 7 is a measurement diagram showing a relationship between power added efficiency and output impedance in a high frequency amplifier when an adjacent channel leakage power is set to −60 dBc.

FIG. 8 is a measurement diagram showing the relationship between bias dependence and power added efficiency in a high frequency amplifier.

FIG. 9 is an explanatory diagram for explaining a design principle of a conventional high frequency amplifier.

[Explanation of symbols]

L ₁ , L ₂ ... Coil, C ₁ , C ₂ ... Capacitance element, Q ... FE
T.

Claims (4)

[Claims] 1. A high-frequency amplifier having a field-effect transistor, wherein an impedance matching circuit that matches an output impedance when the power-added efficiency is maximum with respect to a constant third-order distortion of the field-effect transistor is provided. High frequency amplifier characterized by being connected to. 2. A high frequency amplifier having a field effect transistor, wherein the field effect transistor is biased in a state in which the power added efficiency is maximized with respect to a constant third-order distortion. 3. A high-frequency amplifier having a field-effect transistor, wherein the impedance matching circuit that matches the output impedance when the power-added efficiency is maximum with respect to a constant adjacent-channel leakage power of the field-effect transistor is provided with the field-effect transistor. A high-frequency amplifier characterized by being connected to a transistor. 4. A high-frequency amplifier having a field-effect transistor, wherein the field-effect transistor is biased in a state in which power added efficiency is maximized with respect to a constant adjacent channel leakage power.