JPH07239842A - Integrated-circuit processor for discrete cosine conversion and inversion - Google Patents

Abstract

PURPOSE: To provide a processor which can undergo an operation in reciprocal order despite its simple structure, reduce the dedicated space of a integrated circuit and also increase its processing speed concerning an integrated circuit processor for discrete cosine transformation/inverse transformation in image processing. CONSTITUTION: This processor combines a butterfly operation unit 2 which executes a butterfly operation, a multiplicative operation unit 3 which executes a simple multiplicative operation, an auxiliary addition and subtraction unit 32 which executes an additive and multiplicative operation or a corrective subtractive and multiplicative operation by connecting to the unit 32, and a data register 4 which accesses an intermediate result of operation process by means of a write/read port. Then, one-dimensional DCT/IDCT operation of each time is carried out with parallel processing in a pipeline operation mode through the unit 2 and the unit 3 by forming six steps which include three steps of the butterfly operation, one step of the simple multiplicative operation and the multiplicative operation via two steps of auxiliary addition and subtraction and can undergo these operations in due turn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit processor, and more particularly to an integrated circuit processor for discrete cosine transform capable of forward / reverse order operation.

[0002]

2. Description of the Related Art Discrete Cosine Transform
Transform (hereinafter referred to as "DCT") and its inverse transform (Inverse Discrete Cosine Transform, hereinafter referred to as "IDC")
"T") are used in the compression process and the decompression process of digital images, respectively. In the process of compressing a digital image, usually, the image is subdivided into a large number of blocks of 8 × 8 pixels, and then DCT conversion is performed for each block one by one and converted into frequency domain data. Further, in the restoration process, the data in the frequency domain is restored to the image data through the IDCT.

When performing two-dimensional DCT / IDCT, one-dimensional row (or column) conversion is first performed, and then one-dimensional column (or row) conversion is performed once. Be done. For example, a one-dimensional DCT of any row or column of an 8 × 8 block can be expressed as:

[Equation 1]

The above-mentioned relational expression is composed of a series of multiplications and totals, of which S (m) is image data in the spatial domain and F (k) is data in the domain after conversion. A series of fast algorithms can be derived from this relational expression, and the one-dimensional DCT can be executed by 13 multiplications and 29 additions and subtractions, and the process is as shown in FIG.

In this process, three kinds of operations are defined in particular, and as shown in FIGS. 7 (a) to 7 (d),
Intrinsic Multiplication, Butterfly Operation, Pre-addition Multiplication (P
re-added Multiplication) is included. The other combination operation shown in FIG. 7 is post-subtraction multiplication.
cted multiplication) and is used for the processing process on the IDCT side. Therefore, it can be inferred that 12 butterfly operations, 5 pre-addition multiplications, and 8 simple multiplications have been executed from the process of the one-dimensional DCT, and these operations are further divided into 6 operation steps. It is done in order. The order is the first operating step:
Execution of 4 butterfly operations, 2nd operation step: 2
Execution of pre-addition multiplication operation three times, third operation step: execution of butterfly operation four times again, fourth operation step:
Execution of pre-addition multiplication operation three times, fifth operation step:
Further, the butterfly operation is executed four times, and the sixth operation step: simple multiplication operation is executed eight times. In this way, the one-dimensional DCT is completed. If this one-dimensional operation step is performed in reverse order, a one-dimensional IDCT as shown in FIG. 8 can be obtained. This one-dimensional IDCT
Similarly, the calculation is performed in the order of 6 operation steps, but in the first operation step, the simple multiplication operation, the second, the fourth
The butterfly operation is executed in the sixth and sixth operation steps, and the posterior subtraction multiplication operation is executed in the third and fifth operation steps.

The present invention relates to a DCT / IDCT integrated circuit processor designed on the basis of the above-mentioned high-speed operation method. Due to its unique hardware configuration, for example, 8 × 8 block data is sequentially processed by the above six operation steps. After completing the one-dimensional DCT / IDCT, the order can be further transposed and another one-dimensional DCT / IDCT can be performed to complete the two-dimensional transformation. On the other hand, most of the conventional DCT / IDCT processors have an enormous amount of hardwired logic.
red Logic) is used to speed up processing to achieve tight pipeline work and is therefore very costly, but in practice in a typical application environment such tight and The conversion process of the immediate response can be achieved without requiring high-speed timing.

[0007]

In view of the above-mentioned drawbacks of the conventional DCT / IDCT processor, the present invention is capable of performing forward / reverse order operations with a simple hardware structure.
Moreover, the space occupied by the integrated circuit can be significantly reduced to reduce the cost, and the demand for real-time processing that matches the general usage environment can be met, and the processing speed can be doubled. It is an object of the present invention to provide a DCT / IDCT integrated circuit processor capable of forward and reverse operations and a processing method thereof.

[0008]

To achieve the above object, the present invention provides an input unit to which external data is input, a butterfly operation unit for executing a butterfly operation, and a multiplication operation for executing a simple multiplication operation. A unit, an auxiliary addition / subtraction unit that is combined with the multiplication operation unit to perform a pre-addition multiplication operation or a post-subtraction multiplication operation, and a write / read port with four pins to access an intermediate result of the operation process. By combining with a data register, it is possible to perform two forward and reverse one-dimensional DCT / IDCT operations, and each one-dimensional DCT / IDCT operation is a three-step butterfly operation and a one-step simple multiplication operation, And 6 calculation steps including a multiplicative calculation with 2 steps of auxiliary adjustment.

[0009]

According to the present invention, two-dimensional DCT / IDCT operations can be executed twice by the above-mentioned operation configurations, and at the same time, the butterfly operation unit and the multiplication operation unit are used to perform pipeline processing parallel processing. Therefore, it is possible to significantly reduce the volume of the integrated circuit of the processor capable of forward / reverse order operation, and it is possible to meet general real-time processing requirements. Further, when two of these processors are serially connected to each other, each of them can perform the first and second one-dimensional DCT / IDCT operations of block data according to the pipeline work method of both, so that the processing speed can be further improved, It can be adapted for higher bit rate applications.

[0010]

1 is an embodiment of an integrated circuit processor according to the present invention. This integrated circuit processor includes an input unit 1, a butterfly operation unit 2, a multiplication operation unit 3,
It has a data register 4, an output unit 5, and a control unit 6. The input unit 1 is composed of a demultiplexer, selects data Din from the outside according to the DCT operation or the IDCT operation, and sends it to the butterfly operation unit 2 or the multiplication operation unit 3.

The butterfly operation unit 2 includes a first front multiplexer 21 and a butterfly operation unit 22. The butterfly computing unit 22 is composed of a pair of adders and subtractors. The butterfly operation unit 2
The output data from the input unit 1 or the data register 4 is selected by the pre-multiplexer 21, the butterfly operation is performed by the butterfly operation unit 22, and the operation result is written in the data register 4 or output from the output unit 5 to the outside. .

The multiplication operation unit 3 includes a second front multiplexer 31, an auxiliary adder / subtractor 32, a multiplier 33, and a coefficient R.
An OM 34 and an output selector 35 are provided. Coefficient R
The OM 34 stores the coefficient portion of the multiplication operation, and the data stored therein is used as the operand of the multiplier 33. The multiplication operation unit 3 is in charge of operations of simple multiplication, pre-addition multiplication, and post-subtraction multiplication, and its input data is sent from the input unit 1 or the data register 4, and the second pre-multiplexer is supplied in accordance with each operation. 31 or the auxiliary adder / subtractor 32, and the calculation result is
It is written back to the data register 4 via the output selector 35, or the output of the multiplier 33 is sent to the outside via the output unit 5. When the multiplication operation unit 3 is executing the simple multiplication operation, the input data is given to the multiplier 33 by the selection of the pre-multiplexer 31, and the coefficient R
The simple multiplication operation is completed by synergizing the coefficients of the corresponding addresses from the OM 34. Further, in the case of the pre-addition multiplication operation, both data output from the data register 4 are sent to the auxiliary adder / subtractor 32, and after both are added,
The result is sent to the multiplier 33 and synergized with the coefficient of the corresponding address from the coefficient ROM 34, whereby the pre-addition multiplication operation is completed. Further, in the case of the post-subtraction multiplication operation, similarly, both data output from the data register 4 are sent to the second pre-multiplexer 31 and the auxiliary adder-subtractor 32, respectively. The data sent to 31 is input to the multiplier 33, the simple multiplication operation is executed, and the operation result is the auxiliary adder / subtractor 3
The difference between the two is sent as the result of the posterior subtraction multiplication operation.

The data register 4 is composed of a 4-port register unit, and stores intermediate result data of the calculation process by a RAM or the like. The 4-port structure can be divided into two pairs of write / read (WP1-RP1, WP2-RP2), which are used as data access paths for the butterfly operation unit 2 and the multiplication operation unit 3, respectively.

The output unit 5 comprises a multiplexer, and selects the output from the butterfly computing unit 22 or the multiplier 33 according to whether it is an IDCT operation or a DCT operation, and outputs the output data to the outside. To do. The control unit 6 is used to generate a control sequence and controls the operating procedure of each unit.

2 and 3 show the order in which this processor performs DCT / IDCT operations based on the above configuration. In the figure, one-dimensional transformation ("1st 1-D DCT / IDCT" and "2nd 1-D DCT / IDC" twice before and after the block N is performed.
T ”) is performed, and in each one-dimensional transformation, 6
The butterfly operation and the multiplicative operation in one operation step are sequentially performed, and the butterfly operation unit 2 and the multiplicative operation unit 3 respectively perform parallel processing in a pipeline work system. In the DCT shown in FIG. 2,
In the third and fifth steps, butterfly calculation is performed,
In the second and fourth steps, the pre-addition multiplication operation is performed, and in the sixth step, the simple multiplication operation is performed. Further, in the IDCT shown in FIG. 3, the simple multiplication operation is performed in the first step, the posterior subtraction multiplication operation is performed in the third and fifth steps, and the butterfly operation is performed in the second, fourth, and sixth steps. Done. Also, data is input from Din at the same time as the operation of the first step of the first one-dimensional conversion (that is, "1st 1-D DCT / IDCT"), and the second one-dimensional conversion (that is, "2nd 1-D DCT"). When the operation of the sixth step of "/ IDCT") is executed, the result is output from the external Dout.

The operation data of each step, except for the input and output to the outside, are set to the data register 4 as the source or the destination, and the result of the previous forward step is derived from the subsequent forward step. Therefore, the access method of the data register 4 requires that two one-dimensional conversions in the same block transpose the order of each other. For example, if the first one-dimensional conversion is accessed in row order. , The second one-dimensional transformation is always accessed in column order. The reverse is also true. However, the access order between the blocks adjacent to each other, that is, the second one-dimensional conversion of the previous block and the first one-dimensional conversion of the next block is unchanged. Further, the butterfly multiplicative arithmetic unit 2 and the multiplicative arithmetic unit 3 can simultaneously access data from the individual write / read ports of the data register 4 to the data register 4, and therefore, both the arithmetic units 2 and 3 described above. It is possible to perform parallel processing in a pipelined work method by using, and the similar operation steps are sequentially executed in the same operation unit one after another.

This will be described below together with an embodiment. (1) When performing DCT, for example, an 8 × 8 pixel block is input from Din in the order of rows (or columns) as 64 pixel data, The selection of the input unit 1 is sent to the butterfly multiplication calculation unit 2 and the first step calculation is executed. This is a butterfly operation, and the result is written from the write port WP1 to the data register 4, then read from the read port RP1 and sent to the multiplication operation unit 3 to advance the operation of the second step. This is the pre-addition multiplication operation. Then, after waiting for the result of the pre-addition multiplication operation to be written back to the data register 4 from the other write port WP2 and the operation of the first step being completed, the result from the other read port RP2 can be read. The result of the two step operations is read and sent to the butterfly multiplication operation unit 2, and the third step operation is advanced. The calculation result is written back to the data register 4 by the write port WP1. From the same point of view, the calculation of the fourth step is performed by the multiplication calculation unit 3 after the calculation of the second step, and the calculation of the fifth step is performed after the calculation of the third step by the butterfly multiplication calculation unit. 2 will be held. The sixth step operation is performed by the multiplication operation unit 3 after the operation of the fourth step.
The simple multiplication operation is executed in and the results are written back to the data register 4. Then, when the calculation of the sixth step is completed, the first one-dimensional DCT is completed.

Thereafter, the order is reversed, that is, the data is read from the data register 4 by the RP1 in the order of columns (or rows) and sent to the butterfly multiplication operation unit 2, and the first step of the second one-dimensional DCT. The calculation of is started. The operation method of each subsequent step is the same as that of the first one-dimensional DCT, except that it differs from the sixth one at the end.
That is, the calculation result of the step is directly output from the multiplier 33 of the multiplication calculation unit 3 without being written back to the data register 4, and is output to the external Dout via the output unit 5. This final output is frequency domain data that has been DCT computed for the block pixels.

(2) When executing the IDCT, 64 pieces of frequency domain data are input from the Din to the input unit 1 in the order of rows (or columns), and are sent to the multiplicative arithmetic unit 3 according to the selection thereof. The calculation of the step is performed. This is a simple multiplication operation, the result of which is written in the data register 4 by the write port WP2, then read by the read port RP1 and sent to the butterfly multiplication operation unit 2, which performs the second step operation. Be done. This belongs to the butterfly operation, the result of which is written back to the data register 4 by another write port WP1. The third step is a post-subtraction multiplication operation, which reads the result of the second step operation by the read port RP2 and sends it to the multiplication operation unit 3 which is executed subsequent to the first step operation. The calculation result is written back to the data register 4 by WP2. From the same viewpoint, the calculation of the fourth step is executed by the butterfly multiplication calculation unit 2 after the calculation of the second step, and the calculation of the fifth step is executed by the multiplication calculation unit 3 after the calculation of the third step. To be executed. And the sixth
The operation of the step is executed by the butterfly multiplication operation unit 2 after the fourth step operation, the operation result by this is written back to the data register 4, and thus the sixth step operation is completed. This completes the first one-dimensional IDCT.

Subsequently, in RP2, the data is read from the data register 4 in the order of columns (or rows) and sent to the multiplication operation unit 3, whereby the operation of the first step in the second one-dimensional IDCT is started. The operation of each subsequent step is the same as that of the first one-dimensional IDCT, except that the final operation result of the sixth step is not written back to the data register 4 and is output via the output unit 5. Output to the external Dout. This final output is the pixel data that has undergone IDCT reconstruction.

FIG. 4 shows another embodiment of the processor according to the present invention, in which both basic modules shown in FIG. 1 are connected in series, and two primary operations of block data are performed by pipeline work. Process the original DCT / IDCT,
In other words, both modules each perform one one-dimensional conversion
The steps are executed in order.

This processor mainly comprises a first one-dimensional processing unit 7, a second one-dimensional processing unit 8 and a control unit 9. The first one-dimensional processing unit 7 includes an input unit 71 and a front multiplexer 721.
And a first butterfly operation unit 72 having a butterfly operation unit 722, a first multiplexer operation unit 73 having a front multiplexer 731, an auxiliary adder / subtractor 732, a multiplier 733, a coefficient ROM 734, and an output selector 735, and block data. Input and a first data register 74 for performing a first one-dimensional conversion. First
The data register 74 of the Transpose Mem
ory) and serves as the source of the input data of the second one-dimensional processing unit 8.

On the other hand, the second one-dimensional processing unit 8 includes a second butterfly operation unit 81 having a front multiplexer 811 and a butterfly operation unit 812, a front multiplexer 821, an auxiliary adder / subtractor 822, and a multiplier 82.
3, a second multiplication operation unit 82 having an output selector 824, a second data register 83, and an output unit 84. Second multiplication operation unit 82
The operation input terminal of the multiplier 823 is connected to the first multiplication operation unit 73, and the first multiplication operation unit 73
It can be shared with the coefficient ROM 734 of. The second one-dimensional processing unit 8 outputs a second one-dimensional conversion of the block data and a final result. Control unit 9
Are used to control the execution processes of these first and second one-dimensional processing units 7, 8.

According to the above construction, the execution order of the DCT / IDCT operation is such that the block data DC is processed by the pipeline work of the one-dimensional processing units 7 and 8 as shown in FIG.
When the T / IDCT operation is executed and the input data of the block N enters the first one-dimensional processing unit 7 from Din, the result of the first one-dimensional conversion of the previous block N-1 is the first data. It is sent from the read port RP1A (when executing DCT) or RP2A (when executing IDCT) of the register 74 to the second one-dimensional processing unit 8, and the one-dimensional processing units 7 and 8 each perform one-dimensional conversion six-step operation. And the last result of the previous block N−1 is output unit 8
It is sent from the output terminal of 4 to the external Dout. Block N
When the result of the first one-dimensional conversion of is stored in the first data register 74, the first data register 74
Data is always accessed in the order of column and row compatibility between consecutive blocks. With such a structure, the processing speed can be improved and it can be applied to an application environment with a high byte rate.

There are three basic ideas in the above embodiment, one of which is "forward processing", another is "parallel processing", and the other is "improvement of processing speed.""Sequentialexecution" means that the same hardware is used to perform several sequential executions to achieve a certain task, that is, "to obtain space in time".
Therefore, it means that the hardware is reduced to reduce the cost and the substantial working time is increased.

The "parallel processing" is, in contrast to the forward execution, in "obtaining time in space", that is, in order to achieve a real-time speed under the configuration of the forward execution. This means that two independent units are used to perform parallel processing so as not to extend the work time too much. The "parallel processing" configuration in the above embodiment corresponds to this, and is opposed to the serial configuration of the "improvement in processing speed" described below.

Further, the "improvement in processing speed" is to realize the processing in real time in terms of processing speed when processing at a higher bit rate under the above-mentioned "forward execution" and "parallel processing". In addition, it is necessary to further "obtain time in exchange for space" and belongs to the serial system.

The operation method according to the present invention includes the above-mentioned three ideas, and regardless of whether it is DCT or IDCT, the operation method includes two operation methods in the same order, and each operation has six operations. Including the operation steps, each of the six operation steps can be divided into two types of operations (butterfly operation and multiplication operation), and these operations are performed alternately. That is, this feature forms the configuration and implementation method of the present invention.

For example, in FIG. 1, both features of "forward execution" and "parallel processing" are used.
When CT / IDCT is performed, 12 steps (2 times "1-
"DCT / IDCT") requires "forward execution", but these 12 steps are further divided into 6 steps by "parallel processing" by both independent operation units (butterfly operation unit and multiplication operation unit). Therefore, as shown in FIGS. 2 and 3, it takes about 6 steps to process one block instead of 12 steps, and both arithmetic units can be viewed from any point. Is almost fully operational.

Seen from the execution order, each step has 64 pieces of data (executed in the order of columns or rows, each column or row includes eight pieces of data, and there are a total of eight columns or eight rows). After processing the “plurality of data” in the first step (the “plurality of data” here is slightly different in DCT and IDCT), the second step is It continuously processes the result of the first step, and depends on how long the last step in the previous block (ie the 6th step of "2nd 1-D") is long, if the first one from the beginning In case of processing the blocks, the number of “plurality of data” is 8 at most (one column or one row), and DCT, I
The same is true for DCT. And the third step is the first
Since it belongs to the same kind of operation as that of step 1, the first step completes the processing of 64 pieces of data before connecting, and at this time, the second step always processes a large number of pieces of data. It can be guaranteed to be done and at least eight or more (one column or one row) of data can be processed by the third step without having to wait.

The same applies to the fourth, fifth, and sixth steps, and such an operation method is such that one data is followed by one data, one step is followed by one step, and so on. 1 order (that is, "lst 1-
"D", "2nd 1-D", "1st 1-D" ...
・) It is called pipeline work because it is executed. This pipeline work is performed during both forward operations of one block (ie, "1st1-D" and "2nd1-D".
D)) because the data register unit needs to change the access order during this threshold (column to row, or row to column), and thus "2nd." The first step of "1-D" is always the sixth
The first step of "2nd 1-D" cannot be directly followed by the fifth step of "1st 1-D", because the first step of "2nd 1-D" is This is because the necessary data has not been completely prepared yet. Therefore, even if it is started, it cannot be started. When the first step of "2nD 1-D" is started, the execution order and time are the same as those of "lst 1-D".

Also, the pipeline work between both adjacent blocks is not interrupted, and because the data of the next block comes in from Din, it is not necessary to wait for the first step, Directly in the previous block, "2nd 1
-D ”can be executed subsequent to the fifth step, and the data of the previous block is also successively set to“ 2nd1 ”.
The access order of the data register units also need not be column and row compatible as they are completed and sent to Dout in the sixth step of "-D".

[0033]

As described above, according to the present invention, since the structure is simplified, the space occupied by the integrated circuit can be greatly reduced, which reduces the cost and improves the processing speed. It can be applied to high bit rate application environments that match the requirements of real-time processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an integrated circuit processor for discrete cosine transform / inverse transform according to the present invention.

FIG. 2 is a time chart showing a flow of DCT calculation executed by the processor of FIG.

FIG. 3 is a time chart showing the flow of IDCT calculation executed by the processor of FIG.

FIG. 4 is a block diagram showing another configuration of the discrete cosine transform / inverse transform integrated circuit processor according to the present invention.

5 is a DCT / I implemented by the processor of FIG.
It is a time chart which showed the flow of DCT calculation.

FIG. 6 is an explanatory diagram showing a flow of discrete cosine transform.

7A and 7B are explanatory diagrams showing the definition of each operation used for discrete cosine transform / inverse transform. FIG. 7A is a butterfly operation, FIG. 7B is a simple multiplication operation, and FIG. Calculation, (d) shows the definition of the posterior subtraction multiplication calculation.

FIG. 8 is an explanatory diagram showing a flow of discrete cosine inverse transform.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input unit 2 ... Butterfly operation unit 3 ... Multiplication operation unit 4 ... Data register 5 ... Output unit 6 ... Control unit 31 ... Second front multiplexer 32 ... Auxiliary adder / subtractor 33 ... Multiplier 34 ... Coefficient ROM 35 ... Output selector

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H04N 1/41 B 7/30 H04N 7/133 Z

Claims (8)

[Claims] 1. When performing discrete cosine transform (DCT), input data of a series of pixel data blocks is processed by a 6-step DCT high speed operation method to generate a series of converted data, and the DCT high speed operation is performed. The method includes first, third and fifth steps each including a plurality of butterfly operations, second and fourth steps each including a plurality of pre-addition multiplication operations, and a sixth step including a simple multiplication operation An integrated circuit processor for discrete cosine transform comprising: (a) retrieving the input data from an input unit (1); and (b) the input unit ( 1) to send the input data to the butterfly operation unit (2), and to activate the butterfly operation unit to perform the DCT of the first step.
(C) storing the output data of the first step of the butterfly operation unit (2) in a data register (4); (d) controlling the data register to perform the first operation; The output data of step 1 is sent to the multiplicative arithmetic unit (3), and the multiplicative arithmetic unit is activated to start the D of the second step.
(E) controlling the data register to store the output data of the second step of the multiplication operation unit (3); and (f) controlling the data register. The first and second
The output data of the step of the step 3 is provided to the butterfly operation unit (2), the butterfly operation unit completes execution of the DCT high-speed operation of the first step, and then the butterfly operation unit performs the DCT high-speed operation of the third step. (G) controlling the data register to store the output data of the third step of the butterfly operation unit; (h) controlling the data register to perform the third step. Output data of the third step is stored in the data register (4), and then the multiplicative calculation unit is activated to output the output data of the fourth step. Performing a DCT high speed operation; (i) controlling the data register to perform the fourth step of the multiplication operation unit (3). Phase and to 貯存 force data; (j) said data register control to the third and fourth
The output data of the step of step 5 is provided to the butterfly operation unit (2), the butterfly operation unit executes the DCT high-speed operation of the third step, and then the butterfly operation unit is activated to execute the step of the fifth step. Executing a high-speed DCT operation; (k) controlling the data register to store output data of the butterfly operation unit (2); (l) controlling the data register to output the fifth output. Providing data to the multiplicative arithmetic unit (3) and activating the multiplicative arithmetic unit to perform the DCT high speed operation of the sixth step; (m) a sixth operation of the multiplicative arithmetic unit (3). Extracting the output data of the step from the output unit (5);
And an integrated circuit processor for discrete cosine transform which performs data processing in the order of the steps (a) to (m). 2. A step of controlling the data register (4) to store the output data of the sixth step between the steps (l) and (m), and controlling the data register. The output data of the sixth step is provided to the butterfly operation unit (2), the butterfly operation unit completes the DCT operation of the third step, and then the butterfly operation unit further performs the DCT high-speed operation of the first step. The integrated circuit processor according to claim 1, further comprising: a step of executing an operation; and a step of overlapping in the order of the steps (c) to (l). 3. When performing an inverse discrete cosine transform (IDCT), the input data of a series of pixel data blocks is processed by a 6-step IDCT high speed operation to generate a series of conversion data, and the high speed IDCT operation is performed. A first step including a plurality of simple multiplication operations, a second, a fourth and a sixth step including a plurality of butterfly operations, and a third and a fifth step including a plurality of posterior subtraction multiplication operations, respectively. An integrated circuit processor for discrete cosine inverse transformation, comprising: (a) extracting the input data from an input unit (1); and (b) selecting the input unit. It controls and sends the input data to the multiplicative arithmetic unit (3), and activates the multiplicative arithmetic unit to execute the IDCT high-speed arithmetic of the first step. (C) storing the processing data of the first step of the multiplication operation unit (3) in a data register (4); (d) controlling the data register (4) to store the first data. Butterfly output unit for step output data (2)
And (e) controlling the data register to execute the second step of the IDCT high-speed operation of the butterfly operation unit (2). Storing output data; (f) controlling the data register to provide the output data of the second step to the multiplication operation unit (3),
When the output data of the second step is stored in the data register, activating the multiplicative operation unit to execute the IDCT high-speed operation of the third step; and (g) controlling the data register. Storing the output data of the third step of the multiplicative arithmetic unit (3); and (h) controlling the data register to perform the second and third steps.
Of the output data of the second step I to the butterfly operation unit (2),
Executing the DCT high speed operation and then executing the IDCT high speed operation of the fourth step by the butterfly operation unit; (i) controlling the data register to perform the fourth step of the butterfly operation unit (2). (J) controlling the data register to provide the output data of the fourth step to the multiplication operation unit (3), the output data of the fourth step being Activating the multiplicative arithmetic unit to execute the IDCT high-speed arithmetic operation of the fifth step when the multiplicative arithmetic unit is stored in the data register; Storing the output data of the step 5; (l) controlling the data register to cause the fourth and fifth steps.
To the butterfly operation unit (2), and the butterfly operation unit outputs I
Executing the DCT high speed operation and then executing the IDCT high speed operation of the sixth step by the butterfly operation unit; (m) outputting the output data of the sixth step of the butterfly operation unit (2) to the output unit ( 5) an integrated circuit processor for inverse discrete cosine transformation, which comprises the steps of: (a) to (m). 4. A step of controlling the data register (4) to store the output data of the sixth step between the steps (l) and (m), and the data register (4). The output data of the sixth step is controlled to provide to the multiplicative arithmetic unit (3), and the multiplicative arithmetic unit performs the IDC of the first step.
The integrated circuit processor according to claim 3, further comprising: performing a T high speed operation; and overlapping the steps in the order of (c) to (l). 5. A discrete cosine transform comprising an input unit (1), a butterfly operation unit (2), a multiplicative operation unit (3), a data register (4), an output unit (5), and a control unit (9). And an integrated circuit processor for inverse conversion, wherein the input unit (1) receives input data from the outside; the butterfly operation unit (2) outputs from the input unit (1) and the data register (4). A first pre-multiplexer (721) for selectively outputting the data of
A butterfly computing unit (722) for receiving the output data from the first pre-multiplexer and performing addition and subtraction butterfly computations; the multiplication computation unit (3)
A second pre-multiplexer (731) for selectively outputting data from the input unit and the data register
An auxiliary adder / subtractor (732) connected to the second pre-multiplexer to execute the addition part of the pre-addition operation and the subtraction part of the post-subtraction operation, the second pre-multiplexer and the auxiliary addition-subtraction device A multiplier (7 that is concatenated with and executes the multiplication parts of simple multiplication, pre-addition multiplication and post-subtraction multiplication
33) and a coefficient ROM (734) which is connected to the multiplier and which is accessed as a coefficient part of the multiplication operation and provides another operation input of the multiplier, and is connected to the auxiliary adder / subtractor and the multiplier. And an output selector (735) for selecting the output of the auxiliary adder / subtractor and multiplier and sending it to the data register (4), wherein the data register (4) is the butterfly operation unit (2) and the multiplication. The output unit (5) is connected to the operation unit (3) and accesses the intermediate result of the operation process, and the output unit (5) is connected to the butterfly operation unit (2) and the multiplication operation unit (3). The output data of the arithmetic unit and the multiplicative arithmetic unit are selected and sent to the outside, and the control unit (9) controls the operation sequence of each unit by a control sequence. Configured discrete cosine transform and an integrated circuit processor inverse conversion so as to control the. 6. The input unit (1) is configured to include a demultiplexer, and is configured to select data input by a DCT / IDCT operation and send it to the butterfly operation unit / multiplication operation unit. The integrated circuit processor of claim 5, wherein: 7. A first one-dimensional processing unit (7), a second one
One-dimensional processing unit (8) and control unit (9)
The first one-dimensional processing unit (7) includes an input unit (71), a butterfly operation unit (72), a multiplication operation unit (73), and a first data register (7).
4) is provided, the input unit (71) receives input data from the outside, and the butterfly operation unit (72) selects the data output from the input unit and the first data register. A pre-multiplexer (721) and a butterfly subtracter (722) formed of a pair of adders and subtractors, which receives data from the first pre-multiplexer and executes butterfly operations of addition and subtraction The multiplicative arithmetic unit (73) is connected to the second pre-multiplexer (731) for selecting the data output from the input unit and the first data register, An auxiliary adder / subtractor (732) for executing the addition part of the pre-addition multiplication operation and the subtraction part of the post-subtraction multiplication operation; Plexer and is connected to the auxiliary subtractor simply multiplicative, pre-increment multiplication,
And a multiplier (73 that executes the multiplication part of the post-subtraction multiplication).
3), a coefficient ROM which is connected to the multiplier and is accessed as a coefficient part of a multiplication operation, and which provides another operation input of the multiplier, and an auxiliary adder / subtractor and a multiplier which are connected to the auxiliary adder / subtractor. And the output data of the multiplier is the first
And an output selector (735) for selectively outputting to the data register (74), the first data register (74) is connected to the butterfly operation unit (72) and the multiplication operation unit (73) to perform an operation process. In the second one-dimensional processing unit (8), the butterfly operation unit (81), the multiplication operation unit (82), the second data register (83), And output unit (8
4) is provided, the butterfly operation unit (81) selects a first pre-multiplexer (811) for selecting output data of the first and second data registers (74, 83), and a pair of adders. And a butterfly computing unit (812) formed of a subtractor and receiving data from the first pre-multiplexer to execute addition and subtraction butterfly computations, the multiplication computation unit (82) comprising: And a second pre-multiplexer (821) for selecting data output from the second data register (74, 83), and an addition part of the pre-addition multiplication operation connected to the second pre-multiplexer, Auxiliary adder / subtractor (822) for executing the subtraction part of the post-subtraction multiplication operation, and simple multiplication and pre-addition connected to the second front multiplexer and auxiliary addition / subtraction device. And a multiplier (823) that executes the multiplication part of the post-subtraction multiplication and is also connected to the coefficient ROM of the first one-dimensional processing unit (7) and to the auxiliary adder-subtractor and multiplier. An output selector (824) for selecting the output data of the auxiliary adder / subtractor and multiplier and sending it to the second data register (83), wherein the second data register (83) is the butterfly operation unit ( 81) and the multiplicative arithmetic unit (82) to access the intermediate result in the arithmetic process, and the output unit (84) is connected to the butterfly arithmetic unit (81) and the multiplicative arithmetic unit (82). The output of the arithmetic unit and the multiplicative arithmetic unit is selected to be output data to the outside, and the control unit (9) is the first one-dimensional processing unit. An integrated circuit processor for discrete cosine transform and inverse transform configured to control the execution order of (7) and the second one-dimensional processing unit (8) by a control sequence. 8. The input unit (71) is configured to include a demultiplexer, and selects data input by a DCT / IDCT operation to select a butterfly operation of the second one-dimensional processing unit (8). Unit and first
8. The integrated circuit processor of claim 7, configured to send to a multiplicative arithmetic unit of.