JPH07235670A - Preparation of mos transistor with source / drain region of shallow junction and silicide - Google Patents

Abstract

PURPOSE: To provide a method for manufacturing a MOS transistor having a shallow junction source/drain region, such as a thin silicide film which can simplify steps and can have an improved characteristics. CONSTITUTION: A silicon substrate except for a gate-formed part is exposed, a spacer of a oxide film is formed on a sidewall of a gate, and titanium and titanium nitride are continuously deposited on the entire surface of the substrate to form a thin titanium film 46 and a titanium nitride film 47. Thereafter, the substrate is subjected to a rapid thermal treatment process at a temperature of about 800 deg.C in an ammonium atmosphere, and then subjected by a normal ion-implanting apparatus to an ion-implanting process to implant impurities of a conduction type opposite to that of the substrate into the entire substrate. Finally the substrate is subjected to a heat treatment process at a temperature of 1000 deg.C to diffuse impurities implanted in a titanium silicide film into the substrate, thus forming a shallow junction source/drain region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor, and more particularly to forming a thin film silicide by one metal heat treatment step and forming a shallow junction source / drain region by using an ordinary ion implantation apparatus. To a method for manufacturing a MOS transistor.

[0002]

2. Description of the Related Art The development of semiconductor integration technology has made it possible to integrate MOS transistors of several microns or less. High integration reduces the size of MOS transistors and increases the MO
The junction depth of the source / drain region of the S-transistor also became shallower. Since the sheet resistance of the junction is inversely proportional to the junction depth, if the junction depth of the source / drain region becomes shallower, the sheet resistance of the junction increases and the parasitic resistance (para) of the device is increased.
Sit resistance) increases.

In recent years, in the manufacture of ultra-high integrated circuits, a silicide film is formed in the source / drain regions in order to reduce parasitic resistance and improve device characteristics. The sheet resistance of the junction is proportional to the specific resistance and inversely proportional to the junction depth. For example, the specific resistance of silicon is about 200 μΩcm, and the specific resistance of the silicide film depends on the material, but it is 50 μΩcm.
Before and after.

Therefore, the surface resistance of the junction, which is a parasitic resistance, can be reduced by forming the silicide film in the source / drain region of the shallow junction. As such a silicide film, a titanium silicide film (TiS
i) is widely known. The formation of the silicide in the source / drain region is a result of the reaction with the silicon substrate forming the junction as shown in the following formula.
When the silicide film is formed, the source / drain region made of silicon is consumed by a depth corresponding to the thickness of the film. Ti + 2Si → TiSi ₂

Therefore, since the thickness of the formed silicide film, that is, the consumed portion of the source / drain region is also added to the junction depth, the thickness is thin and stable for manufacturing an ultra-high integration device. A technique for forming a silicide film has been required. Also in the electrical aspect, the silicide film formed in the source / drain region of the shallow junction must have a uniform interface between the silicide and silicon.

Silicide is a polycide (polycid) formed by a reaction between a refractory metal and polysilicon.
de) and salicide formed by the reaction of refractory metal and silicon. 1 to 5 are manufacturing process diagrams of a conventional MOS transistor in which a silicide film is formed in a source / drain region of a shallow junction. Referring to FIG. 1, a low concentration source / drain region 15 and a high concentration source / drain region 17 are formed on a substrate 11 by a general double diffusion method. That is, an element isolation field oxide film 12 is formed on a silicon substrate 11 by using a general field oxidation process, and a gate insulating film 13 and a gate 14 made of a polysilicon film are sequentially formed on a channel region. An impurity having a conductivity type opposite to that of the substrate is ion-implanted using the gate 14 as a mask to form a low concentration source / drain region 15.

The spacer 16 is formed on the side wall of the gate 14 and the spacer 16 is formed on the side wall by a general side wall spacer forming process.
An impurity having a conductivity type opposite to that of the substrate is ion-implanted using the gate 14 as a mask to form a high-concentration source / drain region 17 adjacent to the low-concentration source / drain region 15.

2 and 3 show a titanium silicide film (T
iSi) is a process drawing. Refractory metal over the entire surface of the substrate
After the titanium film (Ti) 18 of 1) is thinly deposited, a primary heat treatment process is performed at a temperature of about 700 ° C. During the heat treatment step, silicon atoms (Si) move to the titanium film 18 and silicon (Si) and titanium (at the interface between the thin titanium film 18 and the silicon substrate 11 and at the interface between the titanium film 18 and the gate film 14). Ti) reacts with each other to form titanium silicide films 19 and 20 having a C ₄₉ phase.

As shown in FIG. 4, the remaining titanium film 18 remaining unreacted except for the titanium silicide films 19 and 20 is removed with an NH ₄ OH / H ₂ O ₂ solution. As a result, the titanium silicide film 19 formed on the source / drain regions 17 is salicide, and the titanium silicide film 19 formed on the gate 14 is polycide. As shown in FIG. 5, a secondary heat treatment process is performed at a temperature of 800 ° C. or higher to form titanium silicide films 19 ′ and 20 ′ having a C ₅₄ phase. Therefore, a MOS transistor having a shallow junction source / drain region 17 and a thin titanium silicide film 19 'can be obtained.

The reason for forming the titanium silicide film by performing the secondary heat treatment step is as follows. When a thin titanium film is formed and then heat-treated at a high temperature, silicon atoms move to the thin titanium film 18, and as shown in FIG.
The C ₅₄ phase titanium silicide film 19 forms not only the surface of the source / drain regions 17 but also unnecessary metal legs 21 along the sidewall spacers 16. Since the metal leg 21 is a conductive material, it causes a short circuit. Therefore, the primary heat treatment is performed at a low temperature to form the titanium silicide film 19 of the C ₄₉ phase only on the surface of the source / drain region 17, and the unreacted titanium film 18 is completely removed. C ₅₄ phase titanium silicide film 19 '
Need to be formed.

There are two homogenous images in the titanium silicide film. One of them is a = 3.62Å, b = 13.7
A titanium silicide film having a C ₄₉ (orthorhombic) structure having a lattice constant of 6Å and c = 3.605Å, and the other one is a = 8.236Å, b = 4.773Å, c = 8.523.
It is a titanium silicide film having a C ₅₄ (orthorhombic) structure having a lattice constant of Å. C ₅₄ T
iSi uses TiSi of C ₅₄ due to the low stable resistivity.

As described above, when the titanium silicide film is formed in the source / drain region 17, since the formed silicide film thickness, that is, the consumed portion is included in the junction depth of the source / drain region, the source / drain region is formed. The area is consumed less. Since the contact resistance increases as the silicide film thickness increases, it is desirable to form the silicide film as thin as 300 Å or less. In order to form a thin silicide film, the titanium film must be thinly deposited in the previous step.

However, since the thermal characteristics of the thin titanium film and the silicide film are unstable, they are agglomerated in the subsequent second heat treatment process.
However, there is a problem that the device characteristics are deteriorated due to the occurrence of the phenomenon. Also,
Since the titanium silicide film formed by the conventional method has a small thickness, it is thermally unstable, so that a sharp bend occurs at the interface between the titanium silicide film 19 'and the source / drain region 17 made of silicon. There was a point.

Among the methods of forming the source / drain region of the shallow junction and the silicide of the thin film, the method of using the silicide as the diffusion source, that is, SADS (Silic)
The As As Diffusion Source) method has been known to be the best. This SADS method is described in J. electrochem. Sec. , 139, 1
96, 1992. Well disclosed in. The SADS method is a method of forming a silicide film on a silicon substrate in advance, ion-implanting a dopant into the silicide film, and performing a heat treatment to diffuse the dopant in the silicide into the silicon substrate to form a shallow source / drain region. is there. The process sequence is different from that of the method of FIGS. 1 to 5 in which the silicide is formed in the source / drain regions after forming the source / drain regions.

7 to 13 are manufacturing process diagrams of a MOS transistor using the conventional SADS process. Referring to FIG. 7, an element isolation field oxide film 32 is formed on a silicon substrate 31 by a general field oxidation process.
A gate 34 made of a gate insulating film 33 and a polysilicon film is sequentially formed on the channel region. Next, a spacer 35 made of an insulating film is formed on the side wall of the gate 34.

8 to 11 show a process of forming a silicide film. This is the same as the step of forming the silicide film shown in FIGS. That is, a thin titanium film 36 is deposited on the entire surface of the substrate, and a primary heat treatment process is performed at a temperature of about 700 ° C. to form a titanium silicide film 37 having a C ₄₉ phase at the interface between the titanium film 36 and the silicon substrate 31. A titanium silicide film 38 is formed at the interface between the gate 34 and the titanium film 36.

The titanium film 36 which does not react is formed into NH ₄ OH.
/ H ₂ O ₂ solution is completely removed, and a second heat treatment process is performed at a temperature of 800 ° C. or higher to form titanium silicide films 37 ′ and 38 ′ having a C ₅₄ phase. Referring to FIG. 12, after forming the titanium silicide films 37 'and 38', an impurity having a conductivity type opposite to that of the substrate is ion-implanted into the titanium silicide film 37 'by utilizing a low acceleration energy of about 10 KeV. At this time, in the case of p-type substrate (NMOS), A
S ⁺ ions are implanted, and in the case of an n-type substrate (PMOS), BF ⁺ ions are implanted.

Referring to FIG. 13, a heat treatment process is performed at a temperature of 1000 ° C. to diffuse the impurities ion-implanted into the titanium silicide film 37 ′ into the substrate 31. As a result, the shallow junction source / drain region 39 is formed, and a MOS transistor having a silicide and a shallow junction source / drain region is obtained. In this SADS method, the dopant immediately after the ion implantation should be distributed only in the titanium silicide film.

The normal ion implantation process can be performed only with an acceleration energy of 30 KeV or more. If the ion implantation energy is too large and the dopant is distributed to the silicon substrate, the leak current will increase due to the knock-on effect during ion implantation. In order to prevent this, a low energy ion implanter of about 10 KeV must be used so that the dopant is distributed only in the thin silicide film of 30 nm or less.

[0020]

However, in such a case, there is a big problem in terms of throughput and stability. That is, in order to distribute the dopant only in the titanium silicide film by using the low energy of about 10 KeV, ions such as Ge ⁺ are first ion-implanted into the substrate to pre-amorphize the substrate.
ation). Further, even when the SADS method is used, since the titanium silicide film is formed by the two heat treatments, the problems of the conventional method of FIGS. 1 to 5 occur. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a method of manufacturing a MOS transistor having a shallow junction source / drain region such as a thin film silicide, which has simplified processes and improved characteristics. There is a purpose.

[0021]

To achieve the above object, according to the present invention, a step of forming a field oxide film for element isolation by a field oxidation process on a silicon substrate, and an insulating film and a poly film on the silicon substrate. Depositing a silicon film, patterning to form a gate insulating film and a gate, exposing the silicon substrate excluding a portion where the gate is formed, forming a spacer made of an oxide film on a sidewall of the gate, A step of continuously depositing a thin titanium film and a titanium nitride film on the entire surface of the substrate and a rapid heat treatment process at a temperature of about 800 ° C. in an ammonia atmosphere are performed to expose the interface between the substrate and the titanium film, the gate and the titanium film. A titanium silicide film is formed at the interface with the film, and a titanium oxide film and a sidewall spacer A step of forming an oxide film at the interface with the titanium film, a step of ion-implanting an impurity of a conductivity type opposite to that of the substrate to the entire surface of the substrate by an ordinary ion-implantation apparatus, and a heat treatment step at a temperature of 1000 ° C. A step of diffusing the ion-implanted impurities into the substrate to form a shallow source / drain region, and selectively removing the remaining titanium film and TixOyNz film with an NH ₄ OH / H ₂ O ₂ solution Step, including thin-film silicide and shallow junction source /
A method for manufacturing a MOS transistor having a drain region is provided.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings. 14 to 18 are manufacturing process diagrams of a MOS transistor having a thin film silicide and a shallow junction source / drain region using the SADS process of the present invention. As shown in FIG. 14, a field oxide film 42 is formed on a silicon substrate 41 by a field oxidation process, and a gate insulating film 43 above a channel region and a gate 44 made of a polysilicon film are sequentially formed. Further, a spacer 45 made of an oxide film is formed on the side wall of the gate 44.

As shown in FIG. 15, 20 is formed over the entire surface of the substrate.
About 0Å titanium film 46 and titanium nitride film (Ti
N) 47 is continuously vapor-deposited without vacuum break. As shown in FIG. 16, an ammonia atmosphere (NH ₃ am
In this case, a heat treatment process is performed at a temperature of 800 ° C. or higher for 20 seconds. During this heat treatment, a C ₅₄ phase titanium silicide film 48 that is salicide is formed at the interface between the substrate 41 and the titanium film 46, and the gate 44 is formed.
At the interface between the titanium film 46 and the titanium film 46, a titanium silicide film 49 of C ₅₄ phase, which is polycide, is formed. Further, at the interface between the sidewall spacer 45 formed of the field oxide film 42 and the oxide film and the titanium film 46, Tix is formed.
The OyNz film 50 is formed.

A titanium film having a thickness of 1 has a thickness of 2.5
Forming a titanium silicide film having. Therefore, in order to obtain a thin titanium silicide film, the thickness of the initially deposited titanium film must be thin. However, the thinner the titanium film is, the more unstable the thermal characteristics of the titanium film are.
Omeration) occurs.

Therefore, according to the present invention, by forming the titanium nitride film 47 having excellent thermal characteristics on the titanium film 36, the interface energy of the titanium film 36 can be lowered and stable titanium silicide films 48, 49 can be obtained. did it. The titanium nitride film 47 blocks oxygen and the like that are contaminated in the atmosphere during the heat treatment so that stable titanium silicide films 48 and 49 can be obtained.

The method of forming the titanium silicide films 48 and 49 by reacting the silicon substrate 41 and the titanium film 36 is as follows. Since the heat treatment proceeds in the ammonia atmosphere, nitrogen atoms (N) pass through the titanium nitride film 47, move to the titanium film 46, and react with the titanium film (Ti), so that the titanium film is converted into the titanium nitride film 46 ′. To be done. At this time, the titanium nitride film has a characteristic that it reacts with silicon during heat treatment to form a titanium silicide film and reacts with an oxide film to form a TixOyNz film, which causes a phase separation phenomenon.
A titanium silicide film 48 which is salicide is formed at the interface with and a titanium silicide film 49 which is polycide is formed at the interface with the gate 44.

At the interface between the field oxide film 32, the side wall spacers 35 and the titanium film 46, TixOy.
The Nz film 50 is formed. This is because the oxidation energy of titanium (Ti) is larger than that of the silicon oxide film (SiO ₂ ). That is, oxygen atoms (O) / nitrogen atoms (N) are dissolved in the thin titanium film 46, and TixOy
The Nz film 50 is formed. This TixOyNz film 50
Suppresses the diffusion of silicon atoms (Si) from the substrate,
Titanium silicide films 48 and 49 are formed only at the interface between the silicon substrate 41 and the titanium film 46.

As shown in FIGS. 15 and 16, the titanium film 46 is also converted into the titanium nitride film 46 'by the dissolution of the nitrogen atom (N), and the last titanium silicide film 4 is formed.
The thickness of 8 becomes thinner. For example, the titanium film 46
And titanium nitride film 47 have an initial thickness of 200Å each
, The titanium silicide film 48 having a thickness of about 500Å is finally formed after the heat treatment.

As shown in FIG. 17, impurities of the opposite conductivity type to the silicon substrate 41 are doped with 30 KeV over the entire surface of the substrate.
Ion implantation is performed using a normal ion implantation apparatus having the above acceleration energy. At this time, the apparent thickness of the titanium nitride film 47 and the titanium silicide film 48 is 700Å
Therefore, all the impurities ion-implanted by utilizing the acceleration energy of 30 KeV or more are titanium nitride film 47.
And in the titanium silicide film 48.

In FIG. 19, the thicknesses of the titanium nitride film 47 and the titanium silicide film 48 are 200 Å and 500, respectively.
In the case of Å, the impurity distribution curve after implanting ions with the acceleration energy of 40 KeV is shown by using TRIM simulation. The figure (A) shows the case when As ⁺ ions are implanted (NMOS), (B). Shows the case where BF ² ions are implanted (PMOS), respectively. As shown in FIGS. 19A and 19B, the titanium film 46
And titanium nitride film 47 obtained by changing the initial deposition thickness of titanium nitride film 47 and titanium nitride film 4
A suitable ion implantation condition at an acceleration energy of 30 KeV or more can be selected according to the thickness of No. 7.

As shown in FIG. 17, a rapid heat treatment process is performed at a temperature of about 1000.degree. C. to diffuse the ion-implanted impurities into the substrate 41 to form a shallow junction source / drain region 51. As shown in FIG.
To form. As shown in FIG. 18, a titanium silicide film 48, ₄ is formed using an NH ₄ OH / H ₂ O ₂ solution or another acid solution.
The remaining titanium nitride films 47 and 46 'except 9
And the TixOyNz film 50 are removed to obtain a MOS transistor having a thin film silicide and a shallow junction source / drain region 51.

[0032]

As described above, according to the method for manufacturing a MOS transistor having a shallow junction source / drain region and a silicide according to the present invention, the phenomenon of titanium nitride film being phase-separated is used to perform a rapid process. Since the silicide film can be formed by various heat treatment processes, the process can be simplified as compared with the conventional two heat treatment processes. Further, consumption of the source / drain region is minimized, and a titanium silicide film suitable for a shallow junction can be obtained, so that an increase in contact resistance is prevented. In addition, due to the phase separation phenomenon, the formation of metal legs is prevented even when a high temperature heat treatment is performed, and the device characteristics can be improved. Moreover, 3
Since the source / drain regions of the shallow junction can be formed by using a normal ion implantation apparatus having an acceleration energy of 0 KeV or more, parasitic resistance such as surface resistance of the junction is reduced, and device characteristics are improved.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a conventional MOS transistor having a shallow junction source / drain region and silicide.

FIG. 2 is a manufacturing process diagram of a conventional MOS transistor having a shallow junction source / drain region and silicide.

FIG. 3 is a manufacturing process diagram of a conventional MOS transistor having a shallow junction source / drain region and silicide.

FIG. 4 is a manufacturing process diagram of a conventional MOS transistor having a shallow junction source / drain region and silicide.

FIG. 5 is a manufacturing process diagram of a conventional MOS transistor having a shallow junction source / drain region and silicide.

FIG. 6 is a diagram for explaining generation of metal legs during formation of a conventional silicide film.

FIG. 7: Conventional SADS (Siliconide As D)
MO using the effect source process
It is a manufacturing process drawing of an S transistor.

FIG. 8: Conventional SADS (Siliconide As D)
MO using the effect source process
It is a manufacturing process drawing of an S transistor.

FIG. 9: Conventional SADS (Siliconide As D)
MO using the effect source process
It is a manufacturing process drawing of an S transistor.

FIG. 10 Conventional SADS (Siliconide As)
M using the Diffusion Source process
It is a manufacturing process drawing of an OS transistor.

FIG. 11 Conventional SADS (Siliconide As)
M using the Diffusion Source process
It is a manufacturing process drawing of an OS transistor.

FIG. 12: Conventional SADS (Siliconide As)
M using the Diffusion Source process
It is a manufacturing process drawing of an OS transistor.

FIG. 13: Conventional SADS (Siliconide As)
M using the Diffusion Source process
It is a manufacturing process drawing of an OS transistor.

FIG. 14 is a manufacturing process diagram of a MOS transistor using the SADS process of the present invention.

FIG. 15 is a manufacturing process diagram of a MOS transistor using the SADS process of the present invention.

FIG. 16 is a manufacturing process diagram of a MOS transistor using the SADS process of the present invention.

FIG. 17 is a manufacturing process diagram of a MOS transistor utilizing the SADS process of the present invention.

FIG. 18 is a manufacturing process diagram of a MOS transistor utilizing the SADS process of the present invention.

FIG. 19 is a view of 4 in manufacturing the MOS transistor of the present invention.
It is a dopant distribution curve figure after implanting ions with an acceleration energy of 0 KeV.

[Explanation of symbols]

 41 substrate 42 field oxide film 43 gate insulating film 44 gate 45 sidewall spacer 46 titanium film 47 titanium nitride film 48, 49 titanium silicide film 50 TixOyNz film 51 source / drain region

Claims (6)

[Claims] 1. A step of forming an element isolation field oxide film (42) on a silicon substrate (41) by a field oxidation step, and an insulating film and a polysilicon film are applied on the silicon substrate (41) and then patterned. A gate insulating film (43) and a gate (44) to expose the other part of the silicon substrate (41), and a spacer (4) made of an oxide film on the sidewall of the gate (44).
5), a step of continuously depositing a thin titanium film (46) and a titanium nitride film (47) on the entire surface of the substrate, and a substrate (41) exposed by performing a rapid heat treatment process. Titanium silicide films (48) and (49) are formed at the interface with the titanium film (46) and at the interface between the gate (44) and the titanium film (46), and the field oxide film (4) is formed.
2) and sidewall spacers (45) and titanium film (46)
A TixOyNz film (50) is formed at the interface with and the remaining titanium film (46) is replaced with a titanium nitride film (4).
6 '), ion implantation of impurities having a conductivity type opposite to that of the substrate into the titanium nitride film (47) and the titanium silicide film (48), and a titanium nitride film (47) and a titanium silicide film ( 48) heat-treating the ion-implanted impurities at a temperature of 1000 ° C. to diffuse into the substrate to form a shallow junction source / drain region (51), and the remaining titanium nitride film (47), (46) ') And T
a method of manufacturing a MOS transistor having a shallow junction source / drain region and a thin film of silicide, including a step of removing the ixOyNz film (50). 2. A MOS transistor having a shallow junction source / drain region and thin film silicide according to claim 1, wherein the titanium (46) and the titanium nitride film (47) are continuously deposited without interruption of vacuum. Production method. 3. The method for manufacturing a MOS transistor having a shallow junction source / drain region and a thin film silicide according to claim 1, wherein the rapid heat treatment step is performed at a high temperature of 800 ° C. or higher. 4. The method of manufacturing a MOS transistor having a shallow junction source / drain region and a thin film of silicide according to claim 1, wherein the rapid heat treatment step is performed in an ammonia atmosphere. 5. The method of manufacturing a MOS transistor having a shallow junction source / drain region and a thin film of silicide according to claim 1, wherein the ion implantation uses a normal ion implantation apparatus having an acceleration energy of 30 KeV or more. 6. A titanium silicide film (48), (4)
9), the remaining titanium nitride film (47),
(46 ') and the TixOyNz film (50) are treated with NH ₄ O.
MOS with shallow junction source / drain regions and thin film silicides as claimed in claim 1, selectively removed using either H / H ₂ O ₂ solution or other acid solution.
Manufacturing method of transistor.