JPH07235553A - Schottky junction field-effect transistor - Google Patents

Abstract

PURPOSE:To improve the characteristics of a MESFET of a BPLDD (buried P-type layer lightly doped drain) structure. CONSTITUTION:A MESFET: of a BPLDD structure is provided.with an operating layer 2 formed on a semiconductor substrate, a Schottky junction gate electrode 4 formed on the layer 2, source and drain regions 7 and 8, which are respectively formed on both sides of the layer 2 and have a concentration higher than that of the layer 2, a source side intermediate concentration layer 5 formed between the layer 2 and the region 7 and a drain side intermediate concentration layer 6 formed between the layer 2 and the region 8 and the layer 6 is formed in a concentration lower than that of the layer 5 and in a layer thicker than the layer 5. Thereby, the breakdown strength of the MESFET can be improved without losing the steepness of the rise of the triode characteristic, which are the merits of the BPLDD structure, and the height of the conductance of a transformer.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a Schottky junction field effect transistor (Schottky Barrier FET, SB FET),
That is, the present invention relates to improvement of a metal-semiconductor junction type field effect transistor (Metal Semiconductor FET, MES FET), and particularly to a Schottky junction type field effect transistor having both high speed operation and high breakdown voltage characteristics.

[0002]

2. Description of the Related Art A Schottky junction field effect transistor having a short gate length and a relatively high threshold voltage of -0.5 V to +0.1 V has been proposed for the purpose of high speed operation (for example, Ishida). IEICE Technical Report ED88-148). A configuration example of such a transistor will be described with reference to FIG. In the figure, 1 is a semi-insulating substrate such as gallium arsenide, 2 is an operating layer (active layer) into which n-type impurities are ion-implanted, 3 is a p-type impurity layer for suppressing the short channel effect, and 4 is Schottky gate electrodes 5 and 6 are low resistance intermediate concentration layers formed by ion-implanting impurities under the same conditions, 7 is a source region to which a source electrode is connected, and 8 is a drain region to which a drain electrode is connected. .

The feature of the transistor of this structure is that the length of the channel region under the gate is shortened as much as possible to enable high speed operation, and the distance between the source region 7 and the drain region 8 is increased. This is where the occurrence of the short channel effect can be suppressed. Source of the above transistor
Drain voltage-drain current characteristics are shown by the dotted line in FIG. When the source-drain voltage is increased under a constant gate voltage, the drain current increases proportionally, but when the drain end of the depletion layer reaches pinch-off due to the potential difference between the source and drain, the drain current saturates, The triode characteristic is shown.

However, as shown in A of FIG. 4, a state in which the drain current further increases and the drain conductance increases is likely to occur without being completely saturated in the saturation region of the drain current. In this state, the drain current output (amplified output) with respect to the gate voltage input is distorted, which is a problem in the characteristics of the amplifier circuit.

In order to solve this problem, a transistor structure has been proposed in which the intermediate concentration layer 6 on the drain side is not formed and a layer having the same impurity concentration profile as the operating layer 2 in the depth direction is left in this portion. (For example, Nagaoka. E
t. al, 1993 International Conference on Solid State
Devices and Materials PD-2-1).

[0006]

However, in this transistor structure, the drain resistance becomes high instead of being able to increase the voltage at which the drain conductance starts to increase, so that the conventional BPLDD (Buried P-layer light) is used.
ly doped drain) structure, which is an advantage of the source-drain voltage vs. drain current characteristics, is that the steep rise of the unsaturated region and the high transconductance characteristics are deteriorated. In particular, MESFE having a threshold voltage near 0 V is deteriorated.
For T, there is a problem that this structure cannot be applied because almost no current flows in the offset portion.

Therefore, the present invention has a high breakdown voltage and a high source-drain voltage without deteriorating the advantages of the BPLDD structure, such as the steep rise of the characteristics in the non-saturation region and the high transconductance characteristics. It is an object of the present invention to provide a field effect transistor having a smaller drain conductance and a better characteristic even in a region.

[0008]

In order to achieve the above object, a Schottky junction field effect transistor of the present invention comprises an operating layer formed on a semiconductor substrate and a Schottky junction type gate formed on the operating layer. An electrode, source and drain regions of higher concentration than the operating layer, formed on both sides of the operating layer, a source-side intermediate concentration layer formed between the operating layer and the source region, and the operating layer A drain-side intermediate concentration layer formed between the drain-side intermediate concentration layer and the drain region, wherein the drain-side intermediate concentration layer is formed as a layer having a lower concentration and a thicker layer than the source-side intermediate concentration layer. And

[0009]

In the MES transistor structure of the present invention, the drain side intermediate concentration layer has a lower concentration and a thicker layer than the source side intermediate concentration layer, so that the drain current density is reduced and carriers are generated due to impact ionization. Suppress.

As a result, it is possible to maintain the advantages of the BPLDD structure and reduce the soft breakdown phenomenon without increasing the drain resistance.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a MES according to the configuration of the present invention.
It is sectional drawing which shows an example of FET. In the figure, 1 is a semi-insulating substrate made of a compound semiconductor such as gallium arsenide GaAs or indium phosphide InP, 2 is an operating layer made of, for example, n-type gallium arsenide, 3 is a different type from the operating layer 2, for example, a p-type. Impurity ion implantation layer, 4 is tungsten nitride W
The Schottky electrode 5 using a gate metal such as Nx or tungsten silicide WSix is the operating layer 2 and the source region 7.
, 6 is a source-side intermediate concentration layer, 6 is a drain-side intermediate concentration layer having a lower concentration and a thicker concentration than the source-side intermediate concentration layer 5, and 7 is a source electrode of a resistive electrode (not shown). The formed source region 8 is a drain region where a drain electrode of a resistive electrode (not shown) is formed.

Next, the MESFET having the above-mentioned structure
The manufacturing process will be described with reference to FIG. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals.
First, p-type impurities are doped on the semi-insulating gallium arsenide GaAs substrate 1 at a peak concentration depth of 0.2 μm and 5 × 1.
Ions are implanted so that the peak concentration is 0 ¹⁶ cm ⁻³ to form the p-type impurity layer 3. The depth of the peak concentration of the n-type impurity is 0.025 μm and the peak concentration is 8 × 10 ¹⁷ c.
The n-type operating layer 2 is formed by ion implantation so that the thickness becomes m ⁻³ . Further, a Schottky gate electrode 4 made of a refractory metal is formed on this operating layer (FIG. 2A).

The drain side region is masked by the resist 10 and the depth of the peak concentration of impurities for forming the n-type layer is 0.03 to 0.06 μm, for example 0.04 μm.
^Is ion-implanted to have a peak concentration of 2 × 10 ¹⁸ cm ⁻³ to form a source-side intermediate concentration layer 5 (see FIG. 2).
(B)).

The source side region is masked with the resist 10,
Under ion implantation conditions such that the effective donor concentration of the n-type layer on the drain side formed at the same time as the operating layer becomes extremely low, the same peak concentration is obtained at the same depth as the operating layer.
Ions of p-type impurities are implanted (FIG. 2C).

With respect to the impurities forming the n-type layer, the depth of the peak concentration is within the range of 0.06 to 0.12 μm, for example, 0.1 μm so that the sheet carrier concentration becomes equal to that of the source side intermediate concentration layer. Ion implantation is performed under the condition that the peak concentration is 8 × 10 ¹⁷ cm ⁻³ to form the drain side intermediate concentration layer 6 (FIG. 2D).

Sidewalls 11 are formed on both sides of the gate electrode to define regions of the source-side intermediate concentration layer and the drain-side intermediate concentration layer. Using this portion as a mask, impurities for forming the n-type layer are ion-implanted so that the peak concentration is 0.1 μm and the peak concentration is 2 × 10 ¹⁸ cm ⁻³ .
A source region 7 and a drain region 8 are formed (FIG. 2).
(E)).

The MESFET thus formed is
The source-drain voltage-drain current characteristic is shown by the solid line in FIG. The device has a gate length of 0.64 μm and a gate width of 10 μm. The gate voltage VG is 0.5 V under the condition that the depletion layer of the operating layer is sufficiently opened, and −0.2 V under the condition that the depletion layer is closed. As shown in the figure, the drain current in the saturation region at the gate voltage VG = -0.2 V is almost the same as the conventional characteristic shown by the dotted line (there is almost no difference). On the other hand, the voltage at which the drain conductance begins to increase is 3.1 V in the BPLDD structure.
On the other hand, it is 4.7 V in the structure of the embodiment. The increase in drain conductance is suppressed to about 1.5 times that of the conventional one. The characteristics in the saturation region when the gate voltage VG = 0.5V is 4V in the configuration of the present invention, whereas the voltage at which the drain conductance starts to increase in the conventional configuration is 2V. Similar to the case of the gate voltage VG = -0.2V, the voltage at which the drain conductance increases increases by about 2V, which is an improvement. Further, the non-saturated region of the present embodiment is preferable because the rise of the current is steeper than that of the conventional example.

The effect obtained by the structure of the present invention can be explained as follows. It is considered that the increase in drain conductance is caused by the generation of new carriers by impact ionization due to the flow of carriers. The impact ionization becomes more remarkable as the electric field strength is higher and the current density is higher, and the amount of new carriers generated increases. Therefore, it is possible to suppress the generation of carriers and reduce the increase in drain conductance by reducing the current density in the portion where the electric field strength is strong.

FIG. 3 shows the result of simulating the carrier generation state of impact ionization in the conventional structure. In the figure, MESFET gate voltage VG =
Under the conditions of −0.2 V and drain voltage Vd = 4.0 V, the generated amount per 1 cm ⁻³ / S is displayed logarithmically and is graphed by contour lines. As a result, carriers are generated by impact ionization in the surface portion of the operating layer, in the vicinity of the boundary between the operating layer and the drain side intermediate concentration layer, in the vicinity of the drain side intermediate region and the boundary region between the drain region and the p-type impurity layer. ing. In particular, it can be seen that a large amount occurs near the operating layer inside the drain side intermediate concentration layer.
Therefore, according to the present invention, the structure of the drain side intermediate concentration layer is such that when the drain voltage is increased, the current density is increased in the drain side intermediate concentration layer in which the electric field strength is highest in the region where the electron current flows inside the MESFET. By lowering and diffusing the current widely in the depth direction, the shape is such that carrier generation can be suppressed as much as possible without increasing drain resistance. That is, by making the drain-side intermediate concentration layer a layer with a lower concentration and a thicker (deeper) layer than the source-side intermediate concentration layer, the drain current density is reduced and carrier generation due to impact ionization is suppressed.

FIG. 4 shows the transistor structure of the above embodiment and the conventional BP using a two-dimensional device simulation.
The results of comparing the current density distributions with the LDD transistor structure are shown. The current density in the depth direction of the drain side intermediate concentration layer at a distance of 0.06 μm from the drain end of the gate electrode to the drain side is shown. The distribution is shown. The gate voltage VG is -0.2 V in both cases, and the drain voltage is 4 V in the BPLDD structure and 6 V in the structure of the present invention as the voltage at which the drain conductance starts to increase in each structure. In the structure of the present invention shown by the solid line in the figure, the maximum value of the current distribution density is reduced to about 1/2 as compared with the BPLDD structure shown by the dotted line, and further, it is widely distributed in the depth direction. There is. Therefore, it is understood that generation of carriers due to impact ionization was suppressed and high breakdown voltage characteristics could be realized without reducing the entire drain current.

[0021]

As described above, according to the present invention,
The generation of carriers due to impact ionization can be suppressed without impairing the high-speed operation characteristics of the short gate MESFET, and more ideal saturation region characteristics can be obtained. Therefore, it is possible to realize an electronic circuit that has high performance and operates stably.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a process drawing showing a process for forming a transistor structure of the present invention.

FIG. 3 is an explanatory diagram showing a carrier generation distribution due to impact ionization in a conventional configuration.

FIG. 4 is a graph showing source-drain voltage vs. drain current characteristics of the MESFET of the present invention and the conventional structure.

FIG. 5 is a graph showing a comparison of current density distributions of the present invention and a conventional MESFET.

FIG. 6 is a cross-sectional view showing a configuration example of a conventional Schottky junction field effect transistor.

[Explanation of symbols]

 1 Semi-Insulating Substrate 2 Operation Layer 3 Impurity Distribution Layer of Different Type from Operation Layer 4 Schottky Gate Electrode 5 Source Side Intermediate Concentration Layer 6 Drain Side Intermediate Concentration Layer 7 Source Region 8 Drain Region

Claims (4)

[Claims] 1. An operating layer formed on a semiconductor substrate, a Schottky junction type gate electrode formed on the operating layer, and a source formed on both sides of the operating layer and having a higher concentration than the operating layer. And a drain region, a source-side intermediate concentration layer formed between the operating layer and the source region, and a drain-side intermediate concentration layer formed between the operating layer and the drain region, The Schottky junction field effect transistor, wherein the drain side intermediate concentration layer is formed in a layer having a lower concentration and a thicker layer than the source side intermediate concentration layer. 2. The Schottky junction field effect transistor according to claim 1, wherein the drain-side intermediate concentration layer has a lower concentration than the operating layer and is thicker than the operating layer at the same depth as the operating layer. A Schottky junction field effect transistor, which is a layer. 3. The Schottky junction field effect transistor according to claim 1, wherein an impurity layer of a type different from that of the operating layer is further formed below the operating layer. Junction field effect transistor. 4. The Schottky junction field effect transistor according to claim 1, wherein a carrier concentration is provided in a region of the drain side intermediate concentration layer having the same thickness as the operating layer. A Schottky junction field effect transistor, which is characterized in that an impurity of a type different from that of the operating layer is ion-implanted so as to lower it.