JPH0723397A - Device and method for decoding picture signal - Google Patents

Abstract

PURPOSE:To attain parallel operation processing without applying restriction such as the encoding of a motion vector by distributing an encoded picture signal to plural decoding means based upon a synchronizing signal added at every slice and decoding the signal respectively. CONSTITUTION:An input bit stream is distributed to code buffers 26 to 29 in the unit of slice and decoded by variable length decoders (IVLCs) 30 to 33. The number of macro blocks per slice is fixed and expected time for synchronizing respective IVLC processing is eliminated to efficiently execute decoding. Decoded data are transferred to a buffer memory group 35 to 38, the parallel processig at every slice is converted into the parallel processing in the unit of 1/2 MB and IQ/IDCT processing blocks 39 to 42 execute processing as in a four-parallel state. Then a picture corresponding to the motion vector in the unit of MB is extracted from a reproduced picture by a frame memory 43, the decoded picture is reproduced along with pictures obtained from the blocks 39 to 42 and the reproduced pictures are stored in the memory 43 again through ST-BUFFs 61 to 64 in four parallel state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording apparatus and an information reproducing apparatus using a storage type moving image medium such as an optical disk and a magnetic tape, and information in a so-called video conference system, moving picture telephone system, broadcasting equipment, etc. The present invention relates to an image decoding device and an image decoding method suitable for being applied to a transmission device / reception device.

[0002]

2. Description of the Related Art When a moving image is digitized and recorded and reproduced, the amount of data becomes enormous, so that the data is compressed. As a method for compressing such a moving image, a so-called MP is used.
EG, encoding using DCT and motion compensated prediction
Decryption is done. FIG. 14 shows a configuration example in the case of reproducing a code obtained by compressing a moving image in this way.

A moving image compression code string input from the input terminal 101 is an inverse VLC circuit 102, an inverse quantization circuit 103,
The image information of each block is restored through the inverse DCT circuit 104, is sequentially stored in the frame memory 107 through the adder 105, and the frame image is reproduced. Also, reverse VL
The C circuit 102 also decodes motion compensation information for motion compensation prediction, and supplies this to the motion compensation circuit 106.
The motion compensation circuit 106 reads predicted image information from the image information previously reproduced in the frame memory 107 according to the motion compensation information or supplies a value of zero to the adder 105. The frame images reproduced in the frame memory 107 are sequentially read and displayed on the display 109 via the D / A converter 108.

However, the number of pixels to be handled is 35 for a videophone.
2x240, NTSC 720x480, HDTV
As the number of systems has increased to 1920 × 1024 and the like, it has become difficult in terms of processing capability to configure a single processor to perform a single processing flow. For this reason, in the past, as shown in FIG.
As shown in FIG. 6, a large screen is divided, a plurality of processors are assigned to each divided screen, and encoding / decoding is performed by parallel processing. FIG. 15 shows a configuration example in the case where a moving image is compressed and recorded / reproduced in this way.

For each of the four divided screen areas, four precoded code strings are input terminals 110-1.
It is supplied to the processors 114 to 117 via 13 and is decoded by using the corresponding frame memories 119 to 122. At this time, for example, the processor 114 writes the decoded image in the frame memory 119, but the switching logic circuit 18 is provided so that the motion compensation can be performed not only from the frame memory 119 but also from the adjacent frame memory 120. It was placed. Further, the switching logic circuit 118 outputs the output image to the D / A converter 123, and the display 1
It was displayed on 24.

4 supplied to processors 114-117
The two code strings will actually be combined into one, but this is achieved by adding a header for multiplexing, and therefore it is separated by 4 before the decoder part.
There was a separating device for returning to one code string.
As an example of realizing the parallelization by dividing the screen as described above, Japanese Patent Laid-Open No. 4-139986 and US Pat.
There is one disclosed in Japanese Patent No. 8,447.

[0007]

In the conventional apparatus, the processing of each processor is divided by thus largely dividing the screen area to realize the parallelization. Then, although it is possible to read from the adjacent screen area to some extent by the switching logic circuit 118, the switching logic circuit 1
Since there is a problem with the scale of 18, the area that can be read is limited due to motion compensation, and not only the compression rate decreases when compressing an image, but also the image quality at the boundary portion of the area changes. There is a problem that the boundary of the area becomes visually unnatural.

In addition, the coding process is performed by dividing the screen into separate regions, and when the division is not performed, the continuous region is coded by using the correlation with the adjacent block. It was not possible and required a different encoding method, which was problematic in terms of compatibility and compression efficiency.

Further, when a new header is added to multiplex a plurality of coded sequences, the overhead for that causes a loss in compression efficiency, and it is necessary to establish a new coding standard. There was a problem.

Therefore, in view of the conventional problems described above,
An object of the present invention is to provide an image signal decoding device and an image signal decoding method capable of operating a plurality of image code data decoding means in parallel while performing the processing while using the conventional encoding method as it is. It is in.

[0011]

The present invention is an image signal decoding apparatus for decoding an encoded coded image signal, wherein a plurality of the coded image signals are added based on a synchronization signal added to each slice. And a plurality of decoding means for respectively decoding the plurality of encoded image signals distributed by the above-mentioned distribution means.

Further, according to the present invention, in an image signal decoding apparatus for decoding a transform-coded coded image signal, a decoding means for serially decoding the coded image signal and the decoding means are provided. It is characterized by comprising parallelization means for converting the decoded serial data into parallel data for each of a plurality of blocks, and a plurality of inverse conversion means for performing inverse conversion in parallel on each of the plurality of blocks. is there. An image signal decoding apparatus according to the present invention includes a distribution unit that distributes the coded image signal into a plurality of units based on a synchronization signal added for each predetermined image unit, and a plurality of codes distributed by the distribution unit. It is characterized in that the encoded image signal is distributed and supplied to a plurality of decoding means.

The present invention also provides an image signal decoding apparatus for decoding a predictive-coded coded image signal.
An output unit that outputs in parallel a plurality of differential block signals that have been predictively coded based on one motion vector; and a plurality of predicted image signals that correspond to the plurality of differential block signals, based on the one motion vector. And a plurality of adding means for adding the plurality of difference block signals and the plurality of predicted image signals, respectively. In the image signal decoding device according to the present invention, the generating means reads from the plurality of memories that are accessed in parallel based on the one motion vector and the plurality of memories based on the one motion vector. Sorting means for sorting the generated data to the corresponding plurality of adding means, and a plurality of reading controls based on the one motion vector for temporarily storing the data read from the plurality of memories It is characterized in that it is provided with a storage means. In the image signal decoding device according to the present invention, the predictive-coded coded image signal is a transform-coded image signal, and the output means serially decodes the coded image signal. Decoding means, parallelizing means for converting the serial data decoded by the decoding means into parallel data for each of a plurality of blocks, and a plurality of inverse transformations for performing inverse transformation in parallel for each of the plurality of blocks. And means. Further, the image signal decoding apparatus according to the present invention comprises a distributing means for distributing the coded image signal into a plurality of parts based on a synchronization signal added for each predetermined image unit, and a plurality of distributing parts by the distributing means. The encoded image signal of is distributed and supplied to a plurality of decoding means.

The present invention is also an image signal decoding method for decoding an encoded coded image signal, wherein the coded image signal is distributed to a plurality of units based on a synchronization signal added to each slice. And a step of decoding each of the distributed encoded image signals.

The present invention is also an image signal decoding method for decoding a transform-coded coded image signal, the method including serially decoding the coded image signal,
It is characterized in that it comprises a step of converting the decoded serial data into parallel data for each of a plurality of blocks, and a step of performing inverse conversion in parallel for each of the plurality of blocks. In the image signal decoding method according to the present invention, the step of serially decoding the coded image signal includes a step of distributing the coded image signal to a plurality of units based on a synchronization signal added for each predetermined image unit. When,
The method further comprises the step of serially decoding each of the distributed encoded image signals.

The present invention is also an image signal decoding method for decoding a predictive-coded coded image signal.
Outputting in parallel a plurality of difference block signals that have been predictively coded based on one motion vector; and a plurality of predicted image signals corresponding to the plurality of difference block signals in parallel based on the one motion vector. It is characterized by including a step of generating and a step of adding the plurality of difference block signals and the plurality of predicted image signals, respectively. In the image signal decoding method according to the present invention, the steps of generating the plurality of predicted image signals in parallel include the steps of accessing a plurality of memories in parallel based on the one motion vector, and Based on the data read from the plurality of memories, a step of temporarily storing the data read from the plurality of memories, and a step of temporarily storing the stored data It has a step of reading out based on the motion vector. In the image signal decoding method according to the present invention, the predictive-coded coded image signal is a transform-coded image signal, and the step of outputting the plurality of difference block signals in parallel is Having a step of serially decoding the encoded image signal, a step of converting the decoded serial data into parallel data for each of a plurality of blocks, and a step of performing inverse conversion in parallel for each of the plurality of blocks. Is characterized by. Further, in the image signal decoding method according to the present invention, the step of serially decoding the coded image signal includes distributing the coded image signal into a plurality of units based on a synchronization signal added for each predetermined image unit. And a step of serially decoding a plurality of distributed encoded image signals.

[0017]

In the image signal decoding apparatus according to the present invention, the coded image signal is distributed to the plurality of decoding means by the distribution means based on the synchronization signal added for each slice, and the plurality of decoding means distributes the plurality of decoding means. Each encoded image signal is decoded.

Further, in the image signal decoding apparatus according to the present invention, the coded image signal is serially decoded by the decoding means, the serial data is converted into parallel data for each of a plurality of blocks by the parallelization means, The inverse transform means of (1) performs inverse transform on each of the blocks in parallel. In this image signal decoding apparatus, the coded image signal is distributed to a plurality of decoding means by the distribution means based on the synchronization signal added for each predetermined image unit, and the plurality of decoding means are distributed to the plurality of decoding means. Each encoded image signal is decoded.

Further, in the image signal decoding apparatus according to the present invention, a plurality of difference block signals predictively coded based on one motion vector are output in parallel from the output means, and based on the one motion vector. A plurality of prediction image signals corresponding to the plurality of difference block signals are generated in parallel by the generation means, and the plurality of difference block signals and the plurality of prediction image signals are respectively added by the plurality of addition means. In this image signal decoding device, the generation means distributes the data read from the plurality of memories accessed in parallel based on the one motion vector to the corresponding plurality of addition means by the distribution means.
The reading of the plurality of storage units for temporarily storing the data read from the plurality of memories is controlled based on the one motion vector. Further, in this image signal decoding device, the output means serially decodes the coded image signal by the decoding means, and the serial data is converted into parallel data for each of a plurality of blocks by the parallelization means. Then, inverse conversion is performed in parallel on each of the plurality of blocks by the plurality of inverse conversion means. Furthermore, in this image signal decoding device, the above-mentioned coded image signal is distributed to a plurality of decoding means by the distribution means based on the synchronization signal added for each predetermined image unit, and each decoding means Each of the encoded image signals is decoded.

Further, in the image signal decoding method according to the present invention, the encoded image signal is divided into a plurality of portions based on the synchronization signal added to each slice, and the plurality of divided encoded image signals are decoded respectively. Turn into.

In the image signal decoding method according to the present invention, the coded image signal is serially decoded, the decoded serial data is converted into parallel data for each of a plurality of blocks, and each of the plurality of blocks is The inverse transformation is performed in parallel with. In this image signal decoding method, in the step of serially decoding the coded image signal, the coded image signal is distributed to a plurality of units based on the synchronization signal added for each predetermined image unit, and the coded image signal is distributed. A plurality of encoded image signals are serially decoded.

Further, in the image signal decoding method according to the present invention, a plurality of differential block signals predictively coded on the basis of one motion vector are output in parallel, and the plurality of difference block signals on the basis of the one motion vector are output. A plurality of predicted image signals corresponding to the differential block signals of 1 are generated in parallel, and the plurality of differential block signals and the plurality of predicted image signals are respectively added. In this image signal decoding method, in the step of generating the plurality of predicted image signals in parallel, the plurality of memories are accessed in parallel based on the one motion vector, and the plurality of memories are accessed based on the one motion vector. The data read from the memory of is divided into a plurality, the data read from the plurality of memories is temporarily stored,
This temporarily stored data is read based on the one motion vector. Further, in this image signal decoding method, the predictive-coded coded image signal is a transform-coded image signal, and the plurality of differential block signals are output in parallel to obtain the coded image signal. Decoding is performed serially, the decoded serial data is converted into parallel data for each of a plurality of blocks, and inverse conversion is performed in parallel for each of the plurality of blocks. Further, in this image signal decoding method, in the step of serially decoding the coded image signal, the coded image signal is distributed to a plurality of units based on a synchronization signal added for each predetermined image unit, The plurality of encoded image signals thus generated are serially decoded.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an MPE to which the present invention is applied.
It is a block diagram which shows the whole structure of the G system high-definition moving image signal decoding apparatus.

The input bit stream is coded by the demultiplexer (DEMUX) 25 into slices (SLICE) in units of code buffers (CODE-BUFF1 to CODE-BUFF4) 26 to 29.
Be assigned to. FIG. 2 shows an example of an image image when an input bit stream is distributed into slices (SLICE). At this time, since the slice header in the bitstream has a byte-aligned structure in advance, the slice header in the bitstream can be easily sorted by searching for each byte.

The motion vector of each macroblock, the DC coefficient of each block, etc. are basically only the difference from the motion vector of the adjacent macroblock in the same slice and the DC coefficient of the adjacent block in order to improve the coding efficiency. Is encoded.

In this way, the code buffer (CODE-B
UFF1) 26 includes slice 1, slice 5, slice 9,
... is stored in the variable length decoder (IVLC1) 3
Decrypt with 0. Similarly, code buffer (CODE-BUFF2) 2
7 includes slice 2, slice 6, slice 10, ...
However, the code buffer (CODE-BUFF3) 28 has slice 3,
Slice 7, slice 11, ... Are code buffers
The (CODE-BUFF4) 29 stores slice 4, slice 8, slice 12, ... And these are decoded by the variable length decoders (IVLC2, IVLC3, IVLC4) 31, 32, 33, respectively.

At this time, by fixing the number of macroblocks (MB) per slice, it is possible to eliminate the waiting time of the IVLC due to the synchronization of the IVLC processes and to perform the decoding efficiently. Details of the IVLC processing will be described later.

The data decoded by the variable length decoder is transferred by the switcher 34 to the buffer memory groups 35 to 38 in the subsequent stage. FIG. 3 shows the data transferred to the buffer memory groups 35 to 38 and the data output from the buffer memory groups 35 to 38. Here, the parallel processing, which has been performed for each slice up to now, is performed in units of 1/2 MB (4 blocks). Convert to parallel processing. For example, in the case of the 4: 2: 2 format, four luminance blocks in one macroblock are processed in parallel and four color difference blocks are processed in parallel. Each variable length decoder (IVLC1
..- IVLC4) 30-33 simultaneously output block 1 of slice 1 to slice 4, but store this for 4 blocks in the buffer memory group (35-38). By simultaneously reading blocks 1 to 4 of slice 1 from the buffer memory groups 35 to 38, the subsequent processing can be performed in parallel processing in units of 1/2 MB. Further, here, the inverse conversion of the zigzag scan can also be performed for some time. Here, the structure of the buffer memory per processing system is 4 blocks × 2 banks.

Inverse Quantization (IQ) and Discrete Cosine Inverse Transform (IDCT) processing blocks (IQ / IDCT1 to IQ / IDCT4)
In 39 to 42, the processing is performed in block units, so that the processing is performed in four parallels as it is.

Next, the motion compensation (MC) process is also performed in four parallels. An image corresponding to the motion vector is extracted in MB units from the image reproduced in the frame memory 43, and IQ / IDCT processing blocks (IQ / IDCT1 to IQ / IDCT) are extracted.
4) The decoded image is reproduced together with the image data output from 39 to 42. Here, the motion compensation processing is 1/2 MB
Since processing is performed for each (4 blocks), the vectors given from the motion compensation processing block (MC1) 53 to the motion compensation processing block (MC4) 56 are always the same. Thereby M
C buffer memory (MC-BUFF1 to MC-BUFF4) Each motion compensation processing block (MC1 to MC4) by switching the data bus with the MC switcher 52 for the data transferred to 48 to 51.
The MC processing can be realized without overlapping the RAM accesses 3 to 56 and limiting the MC search range. Details of the MC processing will be described later.

The decoded images reproduced here are stored in 4 parallel memory buffer memories (ST-BUFF1 to ST-BUFF4) 6 in the same manner as above.
It is again stored in the frame memory 43 via 1 to 64.

The image reproduced on the frame memory 43 is displayed in the display buffer memories (DISP-BUFF1 to DIP).
The display switcher 98 is switched according to the display timing via the SP-BUFF4) 94 to 97 and output to the D / A converter 99 and displayed on the display 100.

Here, FIG. 4 is a block diagram showing a concrete configuration example of the periphery of the variable length decoder in this image signal decoding apparatus.

In FIG. 4, reference numeral 65 is an input terminal for inputting a bit stream, and 66 is a demultiplexer (DEM) that divides the bit stream into slices (SLICE).
UX), 67 to 70 are code buffer memories (CODE-BUFF1 to CODE-BUFF1 to store a bitstream in units of slices (SLICE))
CODE-BUFF4), 71 to 74 are variable length decoders (IVLC) for decoding a bit stream which is a variable length code, 75 to
Reference numeral 78 is an output terminal for outputting the decoded data.

Each operation will be described below with reference to the timing chart of FIG.

The input bit stream input from the terminal 65 is divided by the demultiplexer (DEMUX) 66 into slices (SLICE). Since the bitstream contains a sync signal (Slice-Start-Code) for each of multiple macroblocks (this is called a slice (SLICE)), this is detected to slice the bitstream (SLIC).
E) Divide into units.

As shown in FIG. 5, the bit stream for each slice (SLICE) is divided into a code buffer memory (CODE-BUFF1) 67 and a code buffer memory (CODE-BU).
FF2) 68, code buffer memory (CODE-BUFF3) 69, and code buffer memory (CODE-BUFF4) 70 are written separately. That is, the code buffer memory (CODE-BUFF1) 6
7 includes slice 1, slice 5, slice 9. ． ． But,
The code buffer memory (CODE-BUFF2) 68 has slice 2, slice 6, slice 10. ． ． Is in the code buffer memory (CODE-BUFF3) 69, slice 3, slice 7,
Slice 11. ． ． However, the code buffer memory (CODE-BU
FF4) 70 has slice 4, slice 8, slice 1
2. ． ． Are written respectively.

Further, four variable length decoders (IVLC) 71, 72, 73 and 74 prepared in parallel are respectively provided with code buffer memories (CODE-BUFF1 to CODE-BUFF4) when the bit stream of slice 4 is written. ) 67,68,6
The contents of 9 and 70 are read, and at the same time, decoding is started.

Each variable length decoder (IVLC) 71, 72, 73,
74 completes the decoding process of one macroblock within the same time. The decoding result of the variable length decoder (IVLC) 71 is to the terminal 75, the decoding result of the variable length decoder (IVLC) 72 is to the terminal 76, the decoding result of the variable length decoder (IVLC) 73 is to the terminal 77, the variable length The decoding result of the decoder (IVLC) 74 is output to the terminal 78 and input to the switcher 34. Also, the decoded motion vector data is MC
Switcher 52 and motion compensation processing block (MC1, MC2, MC
3, MC4) Input to 53,54,55,56.

In FIG. 5, a variable length decoder (IVLC)
1-1 of 71 outputs indicates the first block in slice 1. Similarly, the variable length decoder (IVLC) 74 output 4-1
Indicates the first block in slice 4.

Next, FIG. 6 is a block diagram showing another concrete example of the configuration around the variable length decoder (IVLC) in this image signal decoding apparatus.

In FIG. 6, reference numeral 65 is an input terminal to which a bit stream is input, and 79 is a demultiplexer (DEM) that divides the bit stream into slices (SLICE).
UX), 80 is a code buffer memory (Code-Buff) that stores a bitstream by dividing it into slices (SLICEs)
er), 90 to 93 are Sl for the variable length decoder (IVLC) in the subsequent stage.
A buffer memory (Buffer) for storing a bitstream in units of ice, 71 to 74 are variable length decoders (IVLC) for decoding a bitstream which is a variable length code, 75 to 7
Reference numeral 8 is an output terminal for outputting the decoded data.

Each operation will be described below with reference to the timing chart of FIG.

The input bit stream input from the terminal 65 is Sli in the demultiplexer (DEMUX) 79.
It is divided into ce units. Multiple macroblocks in a bitstream (this is called a slice)
Since a synchronization signal (Slice-Start-Code) is included for each, the bit stream is divided into slices (SLICE) by detecting this.

As shown in FIG. 7, the bitstream for each slice is divided into four areas, that is, the area 1, the area 2, the area 3, and the area 4 of the code-buffer memory 80. It is written separately. That is, slice 1, slice 5, slice 9. ． ． However, in area 2, slice 2, slice 6, slice 10. ． ． However, in region 3, slice 3, slice 7, slice 11. ． ． However, in the region 4, slice 4, slice 8, slice 12. ． ． Are written respectively.

When the bit stream of slice 4 is written, four areas are sequentially read from the code buffer memory (Code-Buffer) 80. At this time, the contents of area 1 (slice 1, slice 5, slice 9 ...) Are stored in the buffer memory (Buffer) 90, and the contents of area 2 (slice 2, slice 6, slice 10 .. Buffer 91, the contents of area 3 (slice 3, slice 7, slice 11 ...) Are stored in the buffer memory (Buffer).
In 92, the contents of the area 4 (slice 4, slice 8, slice 12 ...) Are written in the buffer memory 93.

Four variable length decoders (IVL
C) 71, 72, 73, 74 are buffer memories (Buffer)
When the contents of the area 4 are written in 93, a buffer memory (Buffer) 90, a buffer memory (Buffer) 91,
Buffer memory 92, Buffer memory
The contents of 93 are read out, and at the same time, decoding is started.

Each variable length decoder (IVLC) 71, 72, 73,
74 completes the decoding process of one macroblock within the same time. The decoding result of the variable length decoder (IVLC) 71 is to the terminal 75, the decoding result of the variable length decoder (IVLC) 72 is to the terminal 76, the decoding result of the variable length decoder (IVLC) 73 is to the terminal 77, the variable length The decoding result of the decoder (IVLC) 74 is output to the terminal 78 and input to the switcher 34. Also, the decoded motion vector data is
MC switcher 52 and motion compensation processing block (MC1, MC
2.MC3, MC4) 53, 54, 55, 56 are input.

In FIG. 7, a variable length decoder (IVLC) is used.
1-1 of 71 outputs indicates the first block in slice 1. Similarly, the variable length decoder (IVLC) 74 output 4-1
Indicates the first block in slice 4.

If the bit stream contains parameters used for decoding the slices and below in a layer above the slice as a data format (image format), in FIG. Memory (Code-Buffer) 67, 68,
The method of writing the upper layer bit stream to 69 and 70 at the same time and using them in parallel in the variable length decoders (IVLC) 71, 72, 73 and 74, or one of four code buffer memories (Code-Buffer) The upper layer bitstream is written to and one of the four variable length decoders (IVLC) decodes it and the other variable length decoder
A method of setting parameters in (IVLC), a method of setting a parameter in four variable length decoders (IVLC) by another processor decoding a bit stream of an upper layer, and the like can be adopted.

In FIG. 6, the upper layer bit stream is written in one of the four areas of the code buffer memory (Code-Buffer) 80, and the buffer memories 90, 91, 92, Write to 93 simultaneously, variable length decoder (IVLC) 71, 72, 7
3 or 74 to use in parallel, or write the upper layer bitstream in one of the four areas of the code buffer memory (Code-Buffer) 80, in the same manner as in the four buffer memories 90 to 93. Write it to one of them and one of the four variable length decoders (IVLC) decodes it and the other variable length decoder (IVL)
C) method to set the parameter, or another processor decodes the upper layer bitstream,
A method to set parameters in four variable length decoders (IVLC), or a demultiplexer (DEMUX) 79 repeatedly writes the upper layer bit stream to four areas of the code buffer memory (Code-Buffer) 80. , When reading this area, the buffer memories 90, 9
Write to 1,92,93 simultaneously, variable length decoder (IVLC)
71, 72, 73, 74 can be used in parallel.

Next, a specific processing operation of motion compensation will be described.

FIG. 8 shows the distribution of the predicted reference image to each DRAM (frame memory), and the distribution to each DRAM has a checkered pattern.

The motion vector 82 is given to the current frame processing MB 81, and the macroblock (M
B) It is assumed that the position of 83 starts from the area of the DRAM 4 as shown in A of FIG. In the motion compensation process, the blocks MC1, MC2, MC3 and MC4 set the read addresses of the DRAMs 1, 2, 3 and 4 according to the motion vector 82. As a result, the MB of the prediction reference frame
The area of DRAM1 in 83 is transferred to the MC buffer memory (MC-BUFF1) in the configuration of B of FIG.
The area of is the MC buffer memory (MC-BUFF2) and the DRAM3
The area of is the MC buffer memory (MC-BUFF3), DRAM4
Areas are transferred to the MC buffer memory (MC-BUFF4). This completes the transfer of the MB83 of the prediction frame, but the MC buffer memory (MC-BUFF) and the MC-processed prediction image are out of position with respect to the adder to be supplied. 8B) and the adder (57, 58, 59, 60 in FIG. 1) between the switcher 52.
Which MC buffer memory (MC-BUF
Select which adder the data of F) is supplied to. In addition, motion compensation processing blocks MC1, MC2, MC3, M
C4 cooperates with switcher 52 to coordinate motion vector 82.
MC-BUFF1, MC-BUFF2, M
The read addresses of the C-BUFF3 and MC-BUFF4 are controlled so that the data supplied to the adders 57, 58, 59 and 60 become C in FIG.

FIG. 9 shows the switching timing of the switcher 52 between the MC buffer memory (MC-BUFF) and the adder.
When a motion vector as shown in A of FIG. 8 is given, the switcher 52 performs switching so that the MC buffer memory (MC-BUFF4) first accesses the adder 59 at time t1. Similarly, in the switcher 52, the MC buffer memory (MC-BUFF3) is an adder 58, the MC buffer memory (MC-BUFF2) is an adder 59, and the MC buffer memory (M
The switch is set so that C-BUFF1) accesses the adder 60. Next, the switch is switched so that the MC buffer memory (MC-BUFF3) accesses the adder 57 at an intermediate time t2 when accessing one line. Similarly, the MC buffer memory (MC-BUFF4) stores the adder 58 in the MC buffer memory.
(MC-BUFF1) adds the adder 59 to the MC buffer memory (MC-BU
The switch is switched so that FF2) accesses the adder 60. At time t3, the switcher 52 returns the switch to the initial state (starting state of t1) after completing the access of one line, and repeats this operation. Next, n at time t4
When the line ends, this time the MC buffer memory (MC-
BUFF2) switches the switch to access the adder 57. Similarly, the MC buffer memory (MC-BUFF1) is the adder 58, and the MC buffer memory (MC-BUFF4) is the adder 59.
, The switch is switched so that the MC buffer memory (MC-BUFF3) accesses the adder 60, and the n + 1 line is started. At time t5 in the middle of the (n + 1) th line, the switcher 52 switches the switch so that the MC buffer memory (MC-BUFF1) accesses the adder 57 again. Similarly,
Switch the switch so that the MC buffer memory (MC-BUFF2) accesses the adder 58, the MC buffer memory (MC-BUFF3) accesses the adder 59, and the MC buffer memory (MC-BUFF4) accesses the adder 60. When the access to the (n + 1) th line is completed, the switch is returned to the state at time t4,
Thereafter, this operation is repeated until the end of 8 lines at time t7.

This completes the MC processing for 1 MB and starts the processing for the next MB. In this way, the memory access overlaps by switching the MC buffer memory (B in FIG. 8) and the switcher (52 in FIG. 1) between the adders 57, 58, 59 and 60 at the same time when the memory access area is switched. It is possible to realize the motion compensation processing without using it.

In this motion compensation process, as shown in FIG. 1, MC buffer memories (MC-BUFF4 to MC-BUFF4) 48 to
By providing a switcher 52 between the 51 and the adders 57 to 60, which MC buffer memory (MC-BUFF4 to MC-BUF
F4) Which adder the data of 48 to 51 should be supplied to is selected, but as shown in FIG. 10, each of the DRAMs 44 to 47 and the MC buffer memory (MC-
This method can also be realized by providing a switcher 52 between BUFF1 to MC-BUFF4) 48 to 51.

FIG. 11A shows the distribution of the predicted reference image to each DRAM (frame memory), and the distribution to each DRAM has a checkered pattern.

The same motion vector 85 as in the case of the above-described motion compensation processing is given, so that the position of MB86 of the predicted reference frame starts from the area of DRAM4 as shown in A of FIG. 11 with respect to the current frame processing MB84. I was supposed to. The motion compensation processing blocks MC1 to MC4 set the read addresses of the DRAMs 1 to 4 in accordance with the motion vector 85. As a result, the MB of the prediction reference frame
The area to be supplied to the adder 57 in 86 is B in FIG.
Like the MC buffer memory (MC-BUFF1) DRAM4,
The data is transferred in the order of DRAM3, DRAM2, and DRAM1. Similarly, the areas to be supplied to the adder 58 are the DRAM 3, DRAM 4, and DR in the MC buffer memory (MC-BUFF2).
The areas to be supplied to the adder 59 in the order of AM1 and DRAM2 are the MC buffer memory (MC-BUFF3) DRAM2,
Adder 6 in the order of DRAM1, DRAM4, and DRAM3
The area to be supplied to 0 is the MC buffer memory (MC-BUFF
4) DRAM1, DRAM2, DRAM3, DRAM4
Are transferred in this order. In this way, each DRAM and M
By switching the switcher between the C buffer memories, data can be transferred to each MC buffer memory (MC-BUFF1 to MC-BUFF4) without overlapping memory accesses.

As a result, the data to be supplied to the adder 57 is already stored in the MC buffer memory (MC-BUFF1), and the data to be supplied to the adder 58 is already stored in the MC buffer memory.
The data to be supplied to the adder 59 is (M-BUFF2) M
Since the data to be supplied to the adder 60 are stored in the C buffer memory (MC-BUFF3) and the MC buffer memory (MC-BUFF4) respectively, the motion compensation processing can be performed without overlapping memory accesses (see FIG. 11). C) can be realized.

In such motion compensation processing, as shown in FIG.
Each DR that constitutes the frame memory 43 as shown in FIG.
AM44 to 47 and MC buffer memory (MC-BUFF1 to MC-B
UFF1) This method was realized by providing a switcher 52 between 48 and 51. In this case, each DRAM 44
This method can also be realized by distributing data to ~ 47 (frame memory) as follows.

FIG. 12A shows the distribution of the predicted reference image to each of the DRAMs 44 to 47 (frame memory), and the structure is such that each of the DRAMs 44 to 47 is distributed line by line. Current frame processing MB
It is assumed that the motion vector 88 is given to 87 and the position of MB 89 of the prediction reference frame starts from the area of RAM 4 as shown in the figure. The motion compensation processing blocks MC1, MC2, MC3 and MC4 are respectively DRAM1,
Set 2, 3, and 4 read addresses.

Adder 5 in MB 89 of prediction reference frame
The area (B in FIG. 12) to be supplied to the MC buffer memory 7 is in accordance with the timing shown in FIG.
BUFF1) to DRAM4, DRAM1, DRAM2, DRA
M3 ... are transferred in this order.

At this time, if the area to be supplied to the adder 58 is to be transferred from the beginning, the MC buffer memory (MC-
Since it overlaps with the access of BUFF1), the transfer is started from the position shifted by one line from the area to be supplied to the adder 57. That is, the area to be supplied to the adder 58 is the MC buffer memory (MC-BUFF2) and the DRAM 3 and DR.
The areas to be supplied to the adder 59 in the order of AM4, DRAM1, DRAM2 ...
(MC-BUFF3) is shifted by 2 lines from the area to be supplied to the adder 57, and then DRAM2, DRAM3, DR
Similarly, the areas to be supplied to the adder 60 in the order of AM4, DRAM1 ... Are shifted from the area to be supplied to the adder 57 in the MC buffer memory (MC-BUFF4) by 3 lines, DRAM in memory (MC-BUFF4)
1, DRAM2, DRAM3, DRAM4, ... Thus, each DRA shown in FIG.
M44 to 47 and MC buffer memory (MC-BUFF1 to MC-BUF
F4) Set the switcher 52 between 48 and 51 to TIME SLO
MC buffer memory (MC-BUFF1 to MC-BUFF4) without switching memory access by switching every T
Data can be transferred to 48-51.

As a result, the data to be supplied to the adder 57 has already been stored in the MC buffer memory (MC-BUFF1).
The data to be supplied to the adder 58 is to the MC buffer memory (MC-BUFF2), the data to be supplied to the adder 59 is to the MC buffer memory (MC-BUFF3), and the data to be supplied to the adder 60 is. Since each is stored in the MC buffer memory (MC-BUFF4), motion compensation processing can be realized without overlapping memory accesses.

Although an example of a decoder has been described in the above embodiments, the present invention can be applied to a local decoder of an encoder.

[0067]

According to the image signal decoding apparatus of the present invention,
Since the coded image signal is distributed to the plurality of decoding means by the distribution means based on the synchronization signal added to each slice and each of the plurality of coded image signals is decoded by each decoding means, There is no restriction on the encoding method that takes the difference in. Therefore, the method is limited to a coding method that spans blocks, such as a motion vector coding and a DC coefficient coding of each block, that is different from the previous block that is performed in the section between the synchronization codes. It is possible to perform processing by operating a plurality of image code data decoding means in parallel while using the conventional encoding method as it is without adding.

Further, in the image signal decoding apparatus according to the present invention, the coded image signal is serially decoded by the decoding means, and the serial data is converted into parallel data for each of a plurality of blocks by the parallelization means. Since the inverse transform means performs inverse transform on each of the plurality of blocks in parallel, the encoded image signal that has been transform-encoded can be reproduced at high speed by using the conventional encoding method as it is.

Further, in the image signal decoding apparatus according to the present invention, a plurality of differential block signals which are predictively coded based on one motion vector are output in parallel from the output means,
Based on the one motion vector, a plurality of prediction image signals corresponding to the plurality of difference block signals are generated in parallel by the generation means, and the plurality of difference block signals and the plurality of prediction image signals are added to a plurality of addition means. By each of the above, the predictive-coded coded image signal can be quickly decoded.

Further, in the image signal decoding method according to the present invention, the coded image signal is divided into a plurality of parts based on the synchronization signal added to each slice, and the plurality of distributed coded image signals are respectively decoded. By using the conventional encoding method, it is possible to reproduce image code data using the conventional encoding method as it is at high speed.

In the image signal decoding method according to the present invention, the coded image signal is serially decoded, the decoded serial data is converted into parallel data for each of a plurality of blocks, and each of the plurality of blocks is Since the inverse conversion is performed in parallel, the encoded image signal that has been converted and encoded can be reproduced at high speed by parallel processing using the conventional encoding method as it is.

Further, in the image signal decoding method according to the present invention, a plurality of differential block signals that are predictively coded based on one motion vector are output in parallel, and the plurality of difference block signals based on the one motion vector are output. A plurality of predictive image signals corresponding to the differential block signal in parallel, and by adding the plurality of differential block signals and the plurality of predictive image signals respectively, the predictive encoded coded image signal can be quickly obtained. It can be decrypted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image signal decoding device according to the present invention.

FIG. 2 is a diagram for explaining the structure of image data handled by the image signal decoding apparatus according to the present invention.

FIG. 3 is a timing diagram for explaining the operation of the buffer memory in the image signal decoding device according to the present invention.

FIG. 4 is a block diagram showing a specific configuration example around a variable length decoder in the image signal decoding device according to the present invention.

5 is a timing chart for explaining the operation of the specific configuration example shown in FIG.

FIG. 6 is a block diagram showing another specific configuration example around the variable length decoder in the image signal decoding device according to the present invention.

FIG. 7 is a timing chart for explaining the operation of the specific configuration example shown in FIG.

FIG. 8 is a diagram for explaining a specific operation example of motion compensation in the image signal decoding device according to the present invention.

FIG. 9 is a timing diagram for explaining a specific operation example of motion compensation in the image signal decoding device according to the present invention.

FIG. 10 is a block diagram showing another configuration example of the image signal decoding apparatus according to the present invention.

FIG. 11 is a diagram for explaining another specific operation example of motion compensation in the image signal decoding device according to the present invention.

FIG. 12 is a diagram for explaining another specific operation example of motion compensation in the image signal decoding device according to the present invention.

FIG. 13 is a timing diagram for explaining another specific operation example of motion compensation in the image signal decoding device according to the present invention.

FIG. 14 is a block diagram showing a configuration of a conventional image signal decoding device.

FIG. 15 is a block diagram showing a configuration of a conventional image signal decoding parallel processing device.

FIG. 16 is a diagram for explaining a conventional image signal decoding parallel processing method.

[Explanation of symbols]

25 ... Demultiplexer (DEMUX) 26-29 ... Code buffer memory (CODE-BUFF1 ...
CODE-BUFF4) 30-33 ... Variable length decoder (IVLC1-IVLC4) 34, 52 ... Switcher 35-38 ... Buffer memory 39-42 ... IQ / IDCT processing block (IQ / IDCT)
1 to IQ / IDCT4) 43 ... Frame memory 44 to 47 ... DRAM1 to DRAM4 48 to 51 ... MC buffer memory (MC-BUFF1 to MC-B)
UFF4) 53 to 56 ... Motion compensation processing block (MC1 to MC4) 57 to 60 ... Adder 61 to 64 ... Store buffer memory (ST-BUFF1 ...
ST-BUFF4) 65 ... Bitstream input terminal 66 .. Demultiplexer (DEMUX) 67 to 70 ... Code buffer memory (CODE-BUFF1 to
CODE-BUFF4) 71 to 74 ... Variable length decoder (IVLC1 to IVLC4) 75 to 79 ... Output terminal 79 ... Demultiplexer (DEMUX) 80 ... Code buffer memory ( Code-Buffer) 90-93 ... Buffer memory 94-97 ... Display buffer memory (DISP-
BUFF1 ~ DISP-BUFF4) 98 ・ ・ ・ ・ ・ ・ Display switcher 99 ・ ・ ・ ・ ・ ・ D / A converter 100 ・ ・ ・ ・ ・ Display

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number for FI Technical indication H04N 7/15 7251-5C 11/04 B 7337-5C 8420-5L G06F 15/66 330 D (72 ) Inventor Toru Wada 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (14)

[Claims] 1. An image signal decoding apparatus for decoding an encoded coded image signal, wherein the coded image signal is distributed to a plurality of units based on a synchronization signal added to each slice, and An image signal decoding apparatus, comprising: a plurality of decoding means for respectively decoding a plurality of encoded image signals distributed by the distributing means. 2. An image signal decoding apparatus for decoding a transform-coded coded image signal, comprising: decoding means for serially decoding the coded image signal; and decoding by the decoding means. An image signal decoding apparatus comprising: a parallelization unit that converts serial data into parallel data for each of a plurality of blocks; and a plurality of inverse conversion units that perform inverse conversion in parallel for each of the plurality of blocks. 3. A distribution unit for distributing the coded image signal into a plurality of units based on a synchronization signal added for each predetermined image unit, and a plurality of the coded image signals distributed by the distribution unit. The image signal decoding apparatus according to claim 2, wherein the image signal decoding apparatus distributes and supplies the decoding signal to the decoding means. 4. An image signal decoding apparatus for decoding a predictively encoded coded image signal, comprising: an output means for outputting in parallel a plurality of differential block signals predictively coded based on one motion vector. Generating means for generating in parallel a plurality of prediction image signals corresponding to the plurality of difference block signals based on the one motion vector, and adding the plurality of difference block signals and the plurality of prediction image signals, respectively. An image signal decoding apparatus comprising a plurality of adding means. 5. The generating means associates a plurality of memories that are accessed in parallel based on the one motion vector with the data read from the plurality of memories based on the one motion vector. And a plurality of storing means for temporarily storing the data read from the plurality of memories, the reading means being controlled based on the one motion vector. The image signal decoding device according to claim 4, wherein 6. The predictive-coded coded image signal is a transform-coded image signal, and the output means includes decoding means for serially decoding the coded image signal, and the decoding means. Parallelizing means for converting serial data decoded by the converting means into parallel data for each of a plurality of blocks, and a plurality of inverse converting means for performing inverse conversion in parallel on each of the plurality of blocks. The image signal decoding apparatus according to claim 4, characterized in that 7. A distribution unit for distributing the coded image signal into a plurality of units based on a synchronization signal added for each predetermined image unit, and a plurality of the coded image signals distributed by the unit. 7. The image signal decoding apparatus according to claim 6, wherein the image signal decoding apparatus distributes and supplies the decoding means. 8. An image signal decoding method for decoding an encoded coded image signal, comprising: distributing the coded image signal into a plurality of slices based on a synchronization signal added to each slice. And a step of decoding each of a plurality of distributed encoded image signals. 9. An image signal decoding method for decoding a transform-coded coded image signal, the method comprising: serially decoding the coded image signal; An image signal decoding method comprising: a step of converting each block into parallel data; and a step of inversely converting each of the plurality of blocks in parallel. 10. The step of serially decoding the coded image signal includes a step of distributing the coded image signal to a plurality of units based on a synchronization signal added for each predetermined image unit, and a plurality of the plurality of distributed image signals. 10. The image signal decoding method according to claim 9, further comprising the step of serially decoding each of the coded image signals of. 11. An image signal decoding method for decoding a predictive-coded coded image signal, comprising: outputting in parallel a plurality of predictive-coded difference block signals based on one motion vector. And a step of parallelly generating a plurality of prediction image signals corresponding to the plurality of difference block signals based on the one motion vector; and adding the plurality of difference block signals and the plurality of prediction image signals, respectively. An image signal decoding method comprising steps. 12. The step of generating the plurality of predicted image signals in parallel includes the steps of accessing a plurality of memories in parallel based on the one motion vector, and the plurality of memory cells based on the one motion vector. Distributing the data read from the memory into a plurality of steps, temporarily storing the data read from the plurality of memories, and reading the temporarily stored data based on the one motion vector The image signal decoding method according to claim 11, further comprising steps. 13. The predictive-coded coded image signal is a transform-coded image signal, and the step of outputting the plurality of difference block signals in parallel decodes the coded image signal serially. 12. The method according to claim 11, further comprising: a step of converting the decoded serial data into parallel data for each of a plurality of blocks; and a step of inversely converting each of the plurality of blocks in parallel. Image signal decoding method. 14. The step of serially decoding the coded image signal includes a step of distributing the coded image signal to a plurality of units based on a synchronization signal added for each predetermined image unit, and a plurality of the plurality of distributed image signals. 14. The image signal decoding method according to claim 13, further comprising the step of serially decoding each of the coded image signals of.