JPH0723290U - EB test equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] The present invention uses signals from the IC tester side to
The purpose is to separate the PASS waveform and the FAIL waveform so that the correct waveform can always be measured. [Structure] A repeated test pattern of the IC tester 11 is applied to a device under test. Then, the trigger signal 12 of the IC tester is input to the timing control section 13 and given as a sampling reference time. Then, the output signal of the secondary electron detector 19 is given to the sampling control unit,
Input as sampling data. And the I
The FAIL signal 17 and the PASS signal 18 of the C tester are given to the sampling controller 21 so that the FAIL condition, PASS
Writing to the waveform memory 22 is controlled according to the conditions.
The sampling data output of the sampling controller is output to the waveform memory 22 and stored therein.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an EB test apparatus which receives a PASS / FAIL signal from the IC tester side in an EB test apparatus and correctly measures a FAIL waveform generated intermittently.

[0002]

[Prior art]

 First, an outline of the conventional EB test apparatus will be described with reference to an example of a block diagram of a configuration of a conventional EB test apparatus and an example of a measurement waveform at the time of PASS / FAIL in FIG.

First, the operation of measuring the waveform of the DUT (device under test) will be described. The method of measuring the waveform with the EB test equipment is the same as that of the sampling oscilloscope, and the repeated test pattern 11a from the IC tester 11 side is applied to the DUT 10 and at the timing position of interest. Issue the trigger signal 12.

On the other hand, the EB test apparatus side first sets the position of the electron beam to a position where the waveform on the wiring pattern on the DUT chip is to be observed. Then, the trigger signal 12 is input to the timing control unit 13 to generate various timing synchronization signals. First, the timing signal 13b is given to the deflection controller 14 to determine the generation timing of the electron beam 16. Secondly, the timing signal 13a is given to the sampling control section 21, and after the analog signal 19a which is the secondary electron detected by the secondary electron detector 19 is AD-converted, it is digitally synchronized with the timing signal. The data is transferred to the waveform memory 22 and output. Here, the timing signal 13a is sampled while increasing the delay (for example, 100 ps) by a unit time for each input of the trigger signal 12. As a result, waveform data on the time axis are measured and realized. Further, the above data may be used multiple times to use averaged data. Then, the measured waveform data is saved as a data file on a hard disk or the like, and then displayed and used on the waveform screen if necessary.

By the way, there are the following problems in waveform measurement. There is no problem when the DUT is repeatedly and stably operating normally (PASS) or defective operation (FAIL), but in the case of defective operation that occurs intermittently, there is a disadvantage that correct measurement cannot be performed. In general, the EB test apparatus is often used for performance evaluation and yield evaluation measurement of IC chips, and thus device evaluation is often performed by setting the performance limit point of the DUT.

This problem will be described by showing an example of measurement under such condition setting as an example of the observed waveform in FIG.

It is assumed that the waveform when the DUT circuit operates normally is a waveform 31 when PASS, and the waveform when the circuit malfunctions is a waveform 32 when FAIL, which is intermittently generated. . The result of measurement with an EB tester is a waveform 33 in the conventional case. The reason for the waveforms 33a and 33b is that the EB tester uses the sampling method. Due to the repeated test pattern 41, the waveform at the observation point becomes 31a or 32a each time the test pattern is repeated. Since it is an unstable state that changes with time, such a waveform can naturally be obtained even from the principle of the sampling method.

This waveform output cannot be said to be the original waveform anymore, and is a neck to be noted in measurement. Further, in order to improve the measurement accuracy and the like, so-called averaging measurement is often performed, in which measurement is performed multiple times and the average value is used as measurement data. Even in this case, the waveform after averaging becomes the waveform of 34a, which is different from the actual measured waveform, which is not preferable.

[0009]

[Problems to be Solved by the Invention] As described above, when the test pattern is repeated and in an unstable state that is not constant, due to the principle of the sampling method, the waveform is different from the actual measured waveform, which is inconvenient for practical use. It was not preferable. Also, the user must keep this in mind. This was a drawback that could lead to providing incorrect judgment data and measurement results in some cases.

Therefore, the problem to be solved by the present invention is to separate the PASS waveform and the FAIL waveform by using the signal on the IC tester side, and to improve so that a correct waveform can always be measured. To do.

[0011]

[Means for solving the problem]

 (Solution Means of FIG. 1) In order to solve the above problems, in the configuration of the present invention, the repeated test pattern of the IC tester 11 is applied to the device under test (DUT). Then, the trigger signal 12 of the IC tester is input to the timing control unit 13 and given as the sampling reference time. Then, the output signal of the secondary electron detector 19 is given to the sampling control section and used as sampling data. Then, the FAIL signal 17 and the PASS signal 18 of the IC tester are given to the sampling controller 21, and the writing control to the waveform memory 22 is controlled according to the FAIL condition and the P ASS condition. The sampling data output of the sampling control section is output to the waveform memory 22 and stored therein.

(Solution Means of FIG. 2) Further, as shown in FIG. 2, in the above structure, instead of the waveform memory 22, a waveform memory 22a for storing FAIL and a waveform memory 22b for storing PASS are provided. The constituent means is to store the waveform data in two states at the same time.

[0013]

[Action]

 Depending on the FAIL signal, the storage in the waveform memory can be ON / OFF controlled, or can be stored in a separate memory, and the correct waveform data can be obtained.

[0014]

【Example】

 (Embodiment 1) Regarding the embodiment of the present invention, an example of a configuration block diagram of an EB test apparatus of FIG. 1, a time chart diagram of a trigger signal and PASS / FAIL of FIG. 3, and an observed waveform of FIG. An example will be described with reference to.

An outline of implementation of this embodiment will be described. There is a function of comparing the DUT output from the IC tester side with the expected value pattern 11b 11c to judge PASS / FAIL. The FAIL signal 17 and the PASS signal 18, which are the determination results, are supplied to the EB tester side. In the present embodiment, this is controlled by the sampling controller 21 so that the sampling data is stored in the waveform memory 22 only during FAIL (or PASS), so that the FAIL time (or PASS time) occurs intermittently. In this case, however, it is realized by accurately loading the target waveform into the waveform memory 22.

In addition, when the FAIL signal 17 is generated, the sampling control unit 21 is initialized in advance to determine the period from which to the period as the period of the FAIL data. For example, the ± 50 ns section of the FAIL signal is set as the FAIL period, the ± 100 ns section of both PAS S / FAIL signals is set as the FAIL period, or an arbitrarily set section using the trigger signal 12 as the reference time is set as the FAIL period. Therefore, the FAIL detection period is initially set in the sampling control unit under various conditions. Actually, the IC tester 11 side is controlled so that the initial setting time of -100 ns or the like is before the addition of the propagation delay time of the circuit, wiring, etc., and the trigger signal 12 is generated.

This will be specifically and sequentially described. In FIG. 3, acquisition of waveform data after Ta and Tb time will be described. First, in the PASS side data acquisition mode, since the FAIL signal 44a does not exist at the Ta point 42a in the normal state, the sampling data 19a at this time is stored in the sampling control unit 21 of the data storage unit 23. Are stored in the waveform memory 22 via. Next, at the point Tb 42b at the time of failure, the sampling control unit 21 prohibits the sampling data 19a from being stored in the waveform memory 22 by the FAIL signal 44b. In this way, the result of repeated sampling measurement while increasing the delay (eg, 100 ps) by the unit time for each input of the trigger signal 12 becomes the PASS waveform 35 of FIG. 4, and the same waveform as the original PASS waveform 31 is obtained. Will be done.

Secondly, in the FAIL side data acquisition mode, since the FAIL signal 44a is not output at the Ta point 42a in the normal state, the sampling data 19a at this time is stored in the waveform memory 22. Is prohibited. Next, at the point 42b at the Tb point during failure (at the time of FAIL), the sampling data 19a at this time is stored in the waveform memory 22 by the FAIL signal 44b. In this way, the result of repeated sampling measurement while increasing the delay (for example, 100 ps) by the unit time for each input of the trigger signal 12 becomes the FAIL waveform 36a of FIG. 4, and the same waveform as the original FAIL waveform 32a is obtained. Will be done.

Since the waveform immediately before FAIL is usually related to FAIL, in order to determine whether it is a waveform at the time of FAIL, the sampling control unit concerned compares this FAIL period, and if there is a FAIL signal, the waveform memory stores it. Control the stored output of. By the way, the repetition rate of the test pattern applied to the DUT changes depending on the content of the pattern to be tested, but if the periodic rate cannot be supported by the EB test equipment, the trigger signal 12 output is controlled or the timing control unit is controlled. In 13, the sampling measurement is performed intermittently as appropriate. The sampling control unit 21 acquires the sampling data 19a once in this measurement cycle, compares and determines from the time relationship with the FAIL signal whether it is the FAIL period, and then writes and outputs it to the waveform memory 22.

When the averaging function is used, the data from the waveform memory 22 is read out, the averaging operation is performed with the new sampling data input 19a, and then stored in the waveform memory.

(Embodiment 2) In the present embodiment, in the data storage unit 23, the waveform memories are provided with independent waveform memories 22a and 22b, respectively, and the sampling data at the time of PASS and the sampling data at the time of FAIL are separated from each other. Store in memory. This is a structure that can be used more effectively in failure analysis.

An embodiment of the present invention will be described with reference to an example of a block diagram of FIG. 2 in which both PASS / FAIL waveform memories are stored in the data storage section.

Acquisition of waveform data after Ta and Tb in FIG. 3 will be described. Since the FAIL signal 44a is not output at the point 42a of Ta in the normal state, the sampling data 19a is stored in the waveform memory 22a side at this time. In addition, except for the FAIL period, all are stored in this memory. Next, at the point 42b of Tb at the time of failure, the FAIL signal 44b is output, and at this time, the sampling data 19a is stored in the sampling control section 21 in the waveform memory 22b side as the waveform data of only the FAIL period. .

In this way, as the result of repeated measurement, the waveform data of the FAIL period 36c in the FAIL waveform 36 of FIG. 4 is extracted. On the other hand, the waveform during PASS becomes the waveform 35a, and both waveforms are normally extracted. Therefore, the waveforms 31a and 32a at the time of the original FAIL and at the time of PASS are correctly separated and obtained.

[0025]

EFFECTS OF THE INVENTION Since the present invention is configured as described above, it has the following effects. In the past, when the waveform changed, the user would have to keep this in mind because the sampling method would cause a difference from the actual measured waveform. In the past, the user may have made a judgment based on incorrect judgment data / measurement results, but the present invention has the effect of eliminating this problem by acquiring correct waveform data. To be

ON / OFF control of storage in the waveform memory can be performed by the FAIL signal, or storage in separate memories can be performed, and the effect that correct waveform data can be stored in the memory is obtained. Further, by linking with the fail map information on the IC tester side, there is an advantage that it can be used as a more accurate analysis reference material.

By providing the two waveform memories 22a and 22b, the effect that the normal waveform at the time of PASS and the defective waveform at the time of FAIL can be separately stored by the FAIL signal can be obtained. Further, as a result, by comparing and analyzing the waveform memory data of both, the effect that can be more effectively used as a chip evaluation / analysis means can be obtained.

Further, it is possible to detect whether or not there is a change by comparing the waveform memory data of the both. As a result, it is possible to clearly determine whether or not the measured wiring pattern on the chip is in the circuit related to the FAIL signal condition, which is an effective means for chip evaluation and analysis. can get.

[0029]

[Brief description of drawings]

FIG. 1 is an example of a configuration block diagram of an EB test apparatus according to the present invention.

FIG. 2 is a block diagram of the data storage unit of the present invention, in which PASS / FAI is used.
FIG. 6 is an example of a block diagram for storing both L waveform memories.

FIG. 3 is a time chart diagram of a trigger signal and PASS / FAIL.

FIG. 4 is an example of an observed waveform.

[Explanation of symbols]

 11 IC tester 11a Test pattern 11b Expected value pattern 11c Comparison 12 Trigger signal 13 Timing control unit 14 Deflection control unit 16 Electron beam 17 FAIL signal 18 PASS signal 19 Secondary electron detector 21 Sampling control unit 22, 22a, 22b Waveform memory 23 Data storage

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[Procedure amendment]

[Submission date] February 18, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is an example of a configuration block diagram of an EB test apparatus according to the present invention.

FIG. 2 is a block diagram of the data storage unit of the present invention, in which PASS / FAI is used.
FIG. 6 is an example of a block diagram for storing both L waveform memories.

FIG. 3 is a time chart diagram of a trigger signal and PASS / FAIL.

FIG. 4 is an example of an observed waveform.

FIG. 5 is an example of a configuration block diagram of a conventional EB test apparatus.

Claims (2)

[Scope of utility model registration request] 1. In an EB test apparatus, a test pattern of an IC tester (11) is applied to a device under test (DUT), a trigger signal (12) of the IC tester is applied to a timing control section (13), and the IC The FAIL signal (17) and PASS signal (18) of the tester are given to the sampling controller (21), the output signal of the secondary electron detector (19) is given to the sampling controller, and the output of the sampling controller is An EB test apparatus characterized by being output to and stored in a memory (22) and having the above. 2. The waveform memory (22) is replaced by F
The EB test apparatus according to claim 1, further comprising a waveform memory (22a) for storing during AIL and a waveform memory (22b) for storing during PASS.