JPH0723284A - Automatic image quality adjusting device - Google Patents

Abstract

PURPOSE:To provide an automatic image quality adjusting device which is capable of correcting the brightness of a high luminance part or a low luminance part so that the parts may not be white blur or black blur even if the high luminance part or the low luminance part exists in one screen. CONSTITUTION:This device is provided with a monitor circuit 1 dividing one- screen part into plural areas and forming the accumulation data of a digital video signal in every area, an offset coefficient generation means 2 comparing the accumulation data and upper and lower thresholds and calculating the prescribed offset value and the coefficient value according to a difference, a delay circuit 3 delaying the digital video signal and a contrast control circuit 4 where a level shift is performed for the low frequency components of the digital video signal and the digital video signal whose high frequency components are emphasized is outputted, according to the offset value and the coefficient value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image digital signal processing circuit, and more particularly to an image device such as a video camera, a television or a VTR.

[0002]

2. Description of the Related Art Conventionally, as an example of automatic image quality adjustment in video signal processing, there is auto iris adjustment of a video camera. In particular, digital signal processing has recently been adopted for video signal processing, and digital processing has also been adopted for auto iris adjustment of video cameras.

An automatic iris adjusting device in a conventional digital camera will be described with reference to the drawings. FIG. 6 is a block diagram of an auto iris adjusting device for a conventional digital video camera, and FIG. 7 is a diagram for explaining the operation of the auto iris device for a conventional digital video camera. The two-dimensional image to be captured is divided into nine areas 9A to 9I. Is divided into

The conventional auto iris device for a digital camera includes an image sensor 30, an iris device 31, an input amplifier 32, an A / D converter 33, an adder 34, a horizontal counter 35 (hereinafter also referred to as "H counter"), and a vertical counter. The direction counter 36 (hereinafter also referred to as "V counter"), a decoder 37, a latch 38, a microcomputer 39, a data latch 40, three registers 41A, 41B, 41C, and three gates 42A, 42B, 42C.

The output of the image pickup device 30 is supplied to an input amplifier 32, amplified to a predetermined level, and then supplied to an A / D converter 33, for example, converted into a video signal of 1 sample 8 bits. The 8-bit video signal output from the A / D converter 33 is supplied to the adder 34, and the output from the adder 34 is supplied to the data latch 40 and the three registers 41A, 41B, 41C. Register 41
The outputs of A, 41B and 41C are three gates 4 respectively.
2A, 42B, 42C, the gate 42A,
The outputs of 42B and 42C are supplied to the adder 34, and the output of the data latch 40 is supplied to the latch 38.

The register 41A has an area 9A in FIG.
9D and 9G are registers for storing addition outputs of image data included in the respective areas. Similarly, the register 41B relates to the areas 9B, 9E and 9H, and the register 41C relates to the areas 9C, 9F and 9I. .

H counter 3 for counting the number of pixels in the horizontal direction
The output of the V counter 36 that counts 5 and the number of lines in the vertical direction is supplied to the decoder 37. A clear pulse for resetting the data latch 40 is supplied from the decoder 37 to the data latch 40, and three registers 41 are provided.
A control pulse is supplied to each of A, 41B, and 41C,
A gate pulse is supplied to each of the three gates 42A, 42B, and 42C, and a latch pulse is supplied to the latch 38.

The added output for each area, that is, the average value data for each area, which is the output of the latch 38, is supplied to the microcomputer 39, data processing is performed according to a predetermined program, and an iris control signal is sent to the iris device 31. Supply. The iris device 31 adjusts the diaphragm according to the iris control signal output from the microcomputer 39.

The formation of the average value data for each block will be described in detail. When the A / D converter 33 sequentially outputs the first line, the second line, and the video signal in accordance with the horizontal scanning of the image, the adder 34 performs accumulation for each area of each line. The accumulation result of the first line of the area 9A is stored in the register 41A, and then the data latch 40 is reset by the clear pulse of the decoder 37. Is stored in the register 41B, and the area 9
The accumulation result of the first line of C is stored in the register 41C.

In the case of the accumulation of the second line, in the area 9A, the gate 42A is turned on, the data of the register 41A is supplied to the adder 34, and the accumulation result of the first line in the area 9A is compared with the first line. Two lines of data are further accumulated.
Similarly, in the region 9B, the gate 42B is turned on, the data in the register 41B is supplied to the adder 34,
The data of the second line is further accumulated with respect to the accumulation result of the first line in the area 9B. Similarly, in the area 9C, the gate 42C is turned on, the data of the register 41C is supplied to the adder 34, and the data of the second line is further accumulated with respect to the accumulation result of the first line in the area 9C. .

The same operation is repeated after the third line, and at the timing when the accumulation of the last line in the area 9A is completed, the data latch 40 forms a result of accumulating all the data in the area 9A. The latch pulse generated from the decoder at this timing
The latch 38 stores the accumulation result of the data in the area 9A. Further, the data stored in the latch 38 is the microcomputer 39
Is supplied to. Thereafter, by the same operation, the areas 9B and 9C
The respective accumulation results of (3) are also formed in the data latch 40 at a predetermined timing, and are supplied to the microcomputer 39 via the latch 38.

When the accumulation is completed for the regions 9A, 9B, 9C, the same operation is repeated for the regions 9D, 9E, 9F, and then for the regions 9G, 9H, 9I.

As described above, in the conventional digital video camera, the optimum iris control signal is output from the microcomputer 39 according to the state of each area of the screen, the iris is adjusted in the iris device, and the image quality is automatically adjusted. .

[0014]

As described above, in the conventional automatic iris adjusting device which is the image quality automatic adjusting device, the screen is divided into a plurality of areas, and the state of the entire screen is judged by the average value of each area. I am adjusting the aperture. However, in this case, since the aperture value is constant for the entire screen, when a high-luminance portion and a low-luminance portion are mixed in one screen, the aperture value for either the high-luminance portion or the low-luminance portion, or both of them is high. In some cases it was not optimal. Therefore, the contrast in the high-intensity or low-intensity part cannot be sufficiently obtained, and the high-intensity part is crushed by white,
There was a risk that the low-luminance portion would be blackened.

Therefore, an object of the present invention is to correct the brightness of a high-luminance or low-luminance portion so that white or black is not crushed even if there is a high-luminance portion or a low-luminance portion in one screen. It is an object of the present invention to provide an automatic image quality device that can be used.

[0016]

According to the present invention, one screen of a digital video signal is divided into a plurality of areas, and image data contained in each area is accumulated to obtain accumulated data for each area. A monitor circuit that outputs the accumulated data, an upper threshold value input terminal for inputting an upper threshold value, and a lower threshold value input terminal for inputting a lower threshold value. The accumulated data for each area output from the above is compared with the upper threshold value and the lower threshold value, a predetermined offset value and a coefficient value corresponding to the difference are calculated, and the offset value and the coefficient value are output. Offset coefficient generating means, a delay circuit for delaying the digital video signal while the monitor circuit and the offset coefficient generating means perform an operation, and a low frequency band of the digital video signal delayed by the delay circuit. The offset value is added to the wave number component, the high frequency component of the digital video signal delayed by the delay circuit is multiplied by the coefficient value, and the low frequency component is changed according to the offset value and the coefficient value. A contrast control circuit that outputs a digital video signal that is level-shifted and in which the high-frequency component is emphasized is provided.

Further, according to the present invention, the offset coefficient generating means performs a comparison operation on whether the output of the monitor circuit is larger than the upper threshold value or whether the output of the monitor circuit is smaller than the lower threshold value. Correlating means for generating a predetermined offset value for correcting the video level based on the output of the coring means, and a high frequency band based on the output of the coring means. There is provided an automatic image quality adjusting apparatus, comprising: a coefficient generating unit that generates a predetermined coefficient value for emphasizing a component.

Further, according to the present invention, the contrast control circuit extracts a low frequency component from a low frequency component of the digital video signal input from the delay circuit, and a high frequency component of the digital video signal. High frequency component extracting means for extracting, a first adder for adding the output of the low frequency component extracting means and the offset value, and an output of the high frequency component extracting means for multiplying the coefficient value There is provided an automatic image quality adjustment device comprising: a multiplier; and a second adder that adds the output of the first adder and the output of the multiplier.

The present invention further comprises horizontal and vertical low frequency component extraction means between the offset coefficient generation means and the contrast control circuit, wherein the horizontal and vertical low frequency component extraction means generates the offset coefficient. There is provided an automatic image quality adjusting device characterized by extracting low-frequency components of respective values in a horizontal direction and a vertical direction of a screen with respect to the offset value and the coefficient value outputted from the means.

[0020]

The present invention divides one screen into a plurality of areas,
The average value of the brightness is calculated for each area, the brightness is suppressed in the area that is too bright, the brightness is adjusted in the area that is too dark, and the contrast is adjusted to prevent the underexposure or underexposure. Further, the high-frequency component in the too bright region or too dark region is amplified to correct the contour of the image to improve the image quality in this region.

In the second embodiment, the HV-L
By adding the PF, the contrast in the vicinity of the boundary is smoothly changed so that the contrast does not change rapidly at the boundary of each region.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a first embodiment of the present invention,
2 is a block diagram of the embodiment of the contrast control circuit of the present embodiment, FIG. 3 is a block diagram of the embodiment of the offset coefficient generating means of the present embodiment, and FIG. 7 is a diagram for explaining the operation of the present embodiment. , The captured two-dimensional image is divided into nine areas 9A to 9I.

In this embodiment, as shown in FIG. 1, a monitor circuit 1, an offset coefficient generating means 2, a delay circuit 3, a contrast control circuit 4, a video signal input terminal 6, an upper threshold value input terminal 7 and a lowering circuit. The contrast control circuit 4 of this embodiment is composed of a threshold value input terminal 8 and a video signal output terminal 9.
2, the low frequency component extracting means 10 (hereinafter also referred to as “LPF”) and the high frequency component extracting means 11 as shown in FIG.
(Hereinafter also referred to as “HPF”), a first adder 12, a second adder 14, and a multiplier 13. The offset coefficient generating means 2 of the present embodiment has a coring means 20, as shown in FIG. It is composed of an offset generating means 21 and a coefficient generating means 22.

The digital video signal YI input to the video signal input terminal 6 is supplied to the monitor circuit 1 and the delay circuit 3. In the monitor circuit 1, for example, as shown in FIG.
The screen is divided into nine areas 9A to 9I, and accumulated data in each area is calculated.

The video signal input terminal 6 of the embodiment of the present invention corresponds to the output of the conventional A / D converter 33, that is, the input of the adder 34. As for the signal, any digital video signal can be used.

Since the monitor circuit 1 of this embodiment divides one screen into a plurality of areas and accumulates image data contained in each area for each area, in the conventional example, the adder 34, the H counter 35, V counter 36, decoder 37, data clutch 40, registers 41A, 41B, 41C, gate 4
It corresponds to 2A, 42B, 42C.

The output MOUT of the monitor circuit 1, the upper threshold value HI input to the upper threshold value input terminal 7 and the lower threshold value LO supplied to the lower threshold value input terminal 8 are offset as shown in FIG. Is supplied to the coring means 20 in the coefficient generating means 2,
Accumulated data MOUT of 9A to 9I output from the monitor circuit 1
And the upper threshold value HI and the lower threshold value LO are compared. The output of the coring means 20 is supplied to the offset generating means 21 and the coefficient generating means 22.

The coring means 20, for example, in a preferred embodiment, as shown in FIG.
1, NOR gate 52, AND gate 53, adder 54
The output MOUT of the monitor circuit 1 and the upper threshold value input terminal 7 are connected to the subtractor 50, and the output MOUT of the monitor circuit 1 and the lower threshold value input terminal 8 are connected to the subtractor 51. The output of the subtractor 50 is supplied to the NOR gate 52,
The output of the subtractor 51 is supplied to the AND gate 53 and NO
The outputs of the R gate 52 and the AND gate 53 are added by the adder 54.
It is configured to be supplied to.

The offset generating means 21 is, for example, RO
When the accumulated data of a certain area is larger than the upper threshold value HI at the output of the coring means 20, the predetermined negative offset value OF corresponding to the difference is generated, and If the accumulated data is smaller than the lower threshold LO, a predetermined positive offset value according to the difference
OF is generated, and 0 is generated as the offset value OF in other cases. The coefficient generating means 22 is composed of, for example, a ROM, and in the output of the coring means 20, when the accumulated data of a certain area is larger than the upper threshold value HI or smaller than the lower threshold value LO, the difference between them is obtained. Predetermined coefficient according to
CE is generated, otherwise, 1 is generated as the coefficient CE.

The input signal of the digital video signal YI supplied to the delay circuit 3 is delayed for the same period of time from the input of the digital video signal YI to the monitor circuit 1 to the output from the offset coefficient generating means 2. .

As shown in FIG. 2, the output of the delay circuit 3
DY, the offset value OF of the output of the offset coefficient generating means 2 and the coefficient CE are supplied to the contrast control circuit 4.
The output DY of the delay circuit 3 is supplied to the LPF 10 and the HPF 11 of the contrast control circuit 4, and the LPF 10 extracts the low frequency component of the output of the delay circuit 3 and the HPF 11 extracts the high frequency component.

LP which is the low frequency component of the input video signal
The offset value OF of the output of F10 and the output of the offset coefficient generating means 2 is supplied to the first adder 12 and added. The coefficient CE of the output of the HPF 11 which is the high frequency component of the input video signal and the output CE of the offset coefficient generating means 2 are calculated by the multiplier 13
To be multiplied by. The output of the first adder 12 and the output of the multiplier 13 are supplied to the second adder 14 and added. The output of the contrast control circuit 4 is output via the video signal output terminal 9.

For example, in FIG. 7, when the area 9A is too bright and the area 9I is dark, that is, the accumulated data of the area 9A is larger than the upper threshold HI and the accumulated data of the area 9I is smaller than the lower threshold LO. In this case, the offset coefficient generating means 2
Outputs a negative offset value OF and a coefficient CE in the area 9A according to the difference from the upper threshold HI, and outputs a positive offset value OF in the area 9I according to the difference from the lower threshold LO. Output the coefficient CE. The offset value OF and the coefficient CE are supplied to the contrast control circuit 4.

In the bright area 9A, the negative offset value OF is added to the low frequency component of the input video signal. Therefore, the brightness of the too bright area 9A is suppressed to a predetermined level, and the coefficient value CE is further multiplied by the high frequency component of the input video signal, so that the edge in the image is emphasized to the predetermined level and the outline of the image is enhanced. Emphasis is made.

In the dark area 9I, the positive offset value OF is added to the low frequency component of the input video signal, so that the dark area 9A raises the brightness to a predetermined level. Further, since the coefficient value CE is multiplied by the high frequency component of the input video signal, the edge in the image is emphasized to a predetermined level.

As described above, in this embodiment, the monitor circuit 1 detects an excessively bright area and a dark area from an area obtained by dividing one screen into nine areas, and the contrast control circuit 4 detects the brightness of the excessively bright area. By suppressing and making the dark region bright and further emphasizing the edge component of the image, it is possible to improve the contrast according to each region even when a dark portion and an excessively bright portion are mixed in one screen.

The output of the automatic image quality adjusting device of the present invention can be connected to a receiver, and an image with a white or black shadow recorded by a video camera is appropriately corrected to improve the image quality. It can also be played back.

Next, a second embodiment of the present invention will be described with reference to the drawings. 5 is a configuration diagram of a second embodiment of the present invention, FIG. 2 is a configuration diagram of an embodiment of a contrast control circuit of the present embodiment, and FIG. 3 is a configuration diagram of an embodiment of an offset coefficient generating means of the present embodiment. is there. This embodiment comprises a monitor circuit 1, an offset coefficient generating means 2, a delay circuit 3, a contrast control circuit 4, and a horizontal and vertical low frequency component extracting means 5 (hereinafter also referred to as "HV-LPF").

The contrast control circuit 4 of this embodiment is composed of an LPF 10, an HPF 11, a first adder 12, a second adder 14 and a multiplier 13 as in the case of the first embodiment. The means 2 is also similar to the first embodiment,
It comprises a coring means 20, an offset generating means 21, and a coefficient generating means 22. The HV-LPF 5 has a configuration in which a horizontal LPF and a vertical LPF are connected in series.

In this embodiment, the offset value OF and the coefficient CE of the output of the offset coefficient generating means 2 are HV-LPF5.
And the low frequency components in the horizontal and vertical directions of the offset value OF and the coefficient CE are extracted. HV-LP
Low-frequency component LOF of offset value of output of F5 and coefficient C
The low frequency component LCE of E is supplied to the contrast control circuit 4, the low frequency offset value LOF is supplied to the first adder 12, and the low frequency coefficient LCE is supplied to the multiplier 13. H
The blocks other than the V-LPF 5 have the same connection and operation as those of the first embodiment.

In the first embodiment of the present invention, since the offset value and the coefficient value are determined for each area of the image, the offset value and the coefficient value are constant within the area and the signal value having a step at the boundary of the area. Becomes Therefore, in the second embodiment, this signal value is passed through the horizontal and vertical LPFs,
The high frequency components in the stepped portion are deleted, and the offset value LOF and the coefficient value LCE are set so that the boundary portion of the area becomes smooth.

Therefore, in this embodiment, the HV-LPF5 is used.
In order to extract the low frequency components from the signal values of the offset value OF and the coefficient CE generated by the offset coefficient generating means 2 according to the state of each area of the screen, the offset value OF and the coefficient CE are It is possible to suppress sudden changes. For this reason, the contrast gradually changes at the boundary of each region, which enables more natural contrast control.

[0043]

As described above, according to the present invention, an offset coefficient generating means detects an excessively bright area and a dark area from an area obtained by dividing one screen in a monitor circuit, and an offset corresponding to each area is detected. By generating a coefficient, the contrast control circuit suppresses the brightness in an area that is too bright in one screen, brightens it in a dark area, and further emphasizes the edge component of the image according to the state of each area. Even when a dark portion and an excessively bright portion are mixed on one screen, it is possible to improve the contrast and enhance the contour of the image according to each area.

Further, by providing an HV-LPF for extracting the low frequency components from the offset value and coefficient value signals, it is possible to moderate the change in contrast at the boundary of each region within one screen. For this reason,
A more natural contrast control can be realized.

As described above, conventionally, when a dark portion and a bright portion are mixed in one screen, the black portion is crushed in the dark portion or the white portion is crushed in the bright portion depending on the state of the diaphragm. Since one screen is divided into a plurality of areas and the contrast can be controlled according to the state of each area, it is possible to suppress the black underexposure in the dark part and the underexposure in the bright part to ensure the contrast. Has advantages not found in.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a contrast control circuit according to first and second embodiments of the present invention.

FIG. 3 is a configuration diagram of offset coefficient generating means according to the first and second embodiments of the present invention.

FIG. 4 is a circuit configuration diagram of coring means of the present invention.

FIG. 5 is a configuration diagram of a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional example relating to an auto iris device.

FIG. 7 is a diagram for explaining the operation of the first and second embodiments of the present invention and the conventional example.

[Explanation of symbols]

 1 Monitor Circuit 2 Offset Coefficient Generating Means 3 Delay Circuit 4 Contrast Control Circuit 5 HV-LPF 6 Video Signal Input Terminal 7 Upper Threshold Input Terminal 8 Lower Threshold Input Terminal 9 Video Signal Output Terminal 10 Low Frequency Component Extracting Means Reference Signs List 11 high frequency component extraction means 12 first adder 13 multiplier 14 second adder 20 coring means 21 offset generation means 22 coefficient generation means 30 image sensor 31 iris device 32 input amplifier 33 A / D converter 34 adder 35 H counter 36 V counter 37 Decoder 38 Latch 39 Microcomputer 40 Data latch 41A, 41B, 41C Register 42A, 42B, 42C Gate

Claims (4)

[Claims] 1. A screen of a digital video signal is divided into a plurality of areas, and image data contained in each area is accumulated to form accumulated data for each area. A monitor circuit for outputting, an upper threshold value input terminal for inputting an upper threshold value, and a lower threshold value input terminal for inputting a lower threshold value, and each of the regions output from the monitor circuit An offset coefficient generating unit that compares accumulated data with the upper threshold value and the lower threshold value, calculates a predetermined offset value and a coefficient value according to the difference, and outputs the offset value and the coefficient value, A delay circuit that delays the digital video signal while the monitor circuit and the offset coefficient generating means perform the calculation, and the offset to the low frequency component of the digital video signal delayed by the delay circuit. In addition to adding the values, the high frequency components of the digital video signal delayed by the delay circuit are multiplied by the coefficient value, and the low frequency components are level-shifted according to the offset value and the coefficient value. An automatic image quality adjusting apparatus, comprising: a contrast control circuit that outputs a digital video signal in which the high frequency components are emphasized. 2. The offset coefficient generating means is configured such that the output of the monitor circuit is larger than the upper threshold value,
Alternatively, coring means for comparing and calculating whether the output of the monitor circuit is smaller than the lower threshold value, and a predetermined offset value for correcting the video level are generated based on the output of the coring means. 2. The offset generating means for generating, and the coefficient generating means for generating a predetermined coefficient value for emphasizing a high frequency component based on the output of the coring means. Automatic image quality adjustment device. 3. The low-frequency component extracting means for extracting low-frequency components of the digital video signal input from the delay circuit, and the high-frequency component for extracting high-frequency components of the digital video signal. High frequency component extraction means, a first adder for adding the output of the low frequency component extraction means and the offset value, and a multiplier for multiplying the output of the high frequency component extraction means by the coefficient value The second image adder that adds the output of the first adder and the output of the multiplier, the automatic image quality adjustment apparatus according to claim 1, further comprising: 4. A horizontal / vertical low frequency component extraction unit is provided between the offset coefficient generation unit and the contrast control circuit, and the horizontal / vertical low frequency component extraction unit outputs from the offset coefficient generation unit. 4. The low frequency component of each of the offset value and the coefficient value in the horizontal direction and the vertical direction of the screen is extracted with respect to the offset value and the coefficient value according to claim 1. The automatic image quality adjustment device described in 1.