JP2872005B2 - Automatic image quality adjustment device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing circuit, and more particularly to a video device such as a video camera, a television and a VTR.

[0002]

2. Description of the Related Art Conventionally, as an example of automatic image quality adjustment in video signal processing, there is an auto iris adjustment of a video camera. In particular, digital signal processing has been adopted in recent video signal processing, and digital processing has also been adopted in auto iris adjustment of video cameras.

A conventional auto iris adjusting device in a digital camera will be described with reference to the drawings. FIG. 6 is a configuration diagram of a conventional auto iris adjustment device of a digital video camera, and FIG. 7 is a diagram for explaining the operation of the conventional auto iris device of a digital video camera. A two-dimensional image to be captured is divided into nine areas 9A to 9I. Is divided into

A conventional auto iris device of a digital camera includes an image pickup device 30, an iris device 31, an input amplifier 32, an A / D converter 33, an adder 34, a horizontal counter 35 (hereinafter also referred to as "H counter"), and a vertical A direction counter 36 (hereinafter also referred to as a “V counter”), a decoder 37, a latch 38, a microcomputer 39, a data latch 40, three registers 41A, 41B, 41C, and three gates 42A, 42B, 42C.

The output of the image sensor 30 is supplied to an input amplifier 32, amplified to a predetermined level, supplied to an A / D converter 33, and converted into a video signal of, for example, 8 bits per sample. The 8-bit video signal output from the A / D converter 33 is supplied to an adder 34, and the output of the adder 34 is supplied to a data latch 40 and three registers 41A, 41B, and 41C. Register 41
The outputs of A, 41B, and 41C are three gates 4 respectively.
2A, 42B, and 42C.
The outputs of 42B and 42C are supplied to the adder 34, and the output of the data latch 40 is supplied to the latch 38.

[0006] The register 41A is a region 9A in FIG.
9D and 9G are registers for storing the added output of the image data included in each area. Similarly, the register 41B is related to the areas 9B, 9E and 9H, and the register 41C is related to the areas 9C, 9F and 9I. .

H counter 3 for counting the number of pixels in the horizontal direction
The output of the V counter 36 for counting 5 and the number of lines in the vertical direction is supplied to a decoder 37. A clear pulse for resetting the data latch 40 is supplied from the decoder 37 to the data latch 40, and the three registers 41
A, 41B and 41C are supplied with control pulses, respectively.
A gate pulse is supplied to each of the three gates 42A, 42B, and 42C, and a latch pulse is supplied to the latch 38.

The output of the latch 38, that is, the addition output of each area, that is, the average value data of each area, is supplied to a microcomputer 39, which performs data processing according to a predetermined program, and sends an iris control signal to the iris device 31. Supply. The iris device 31 adjusts the aperture according to an iris control signal output from the microcomputer 39.

The formation of the average value data for each block will be described in detail. When the A / D converter 33 sequentially outputs the first line, the second line, and the like in accordance with the horizontal scanning of the image, the adder 34 performs accumulation for each area of each line. The accumulation result of the first line of the area 9A is stored in the register 41A, and then, after the data latch 40 is reset by the clear pulse of the decoder 37, the accumulation result of the first line of the area 9B is obtained by the same operation. Is stored in the register 41B.
The accumulation result of the first line of C is stored in the register 41C.

In the case of accumulation of the second line, in the area 9A, the gate 42A is turned on, the data of the register 41A is supplied to the adder 34, and the accumulation result of the first line in the area 9A is compared with the accumulation result of the first line. Two lines of data are further accumulated.
Similarly, in the area 9B, the gate 42B is turned on, and the data of the register 41B is supplied to the adder 34,
The data of the second line is further accumulated with respect to the accumulation result of the first line in the area 9B. Similarly, in the area 9C, the gate 42C is turned on, the data of the register 41C is supplied to the adder 34, and the data of the second line is further accumulated with respect to the accumulation result of the first line in the area 9C. .

The same operation is repeated from the third line onward, and at the timing when the accumulation of the last line in the area 9A is completed, the result obtained by accumulating all the data in the area 9A is formed in the data latch 40. At this timing, the latch pulse generated by the decoder at this timing
The accumulation result of the data in area 9A is stored in latch 38. Further, the data stored in the latch 38 is
Supplied to Thereafter, by the same operation, the areas 9B, 9C
Are also formed in the data latch 40 at a predetermined timing, and are supplied to the microcomputer 39 via the latch 38.

When the accumulation is completed for the areas 9A, 9B and 9C, the same operation is repeated for the areas 9D, 9E and 9F, and then for the areas 9G, 9H and 9I.

As described above, in the conventional digital video camera, the microcomputer 39 outputs an optimum iris control signal according to the state of each area of the screen, the iris is adjusted in the iris device, and the image quality is automatically adjusted. .

[0014]

As described above, in a conventional automatic iris adjusting device which is an automatic image quality adjusting device, a screen is divided into a plurality of regions, and the state of the entire screen is determined based on an average value of each region. Then the aperture is adjusted. However, in this case, the aperture value is constant for one entire screen, so when a high-luminance part and a low-luminance part are mixed in one screen, the aperture value is determined for one or both of the high-luminance part and the low-luminance part. Sometimes it was not optimal. Therefore, the contrast in the high-brightness or low-brightness portion cannot be sufficiently obtained, and the high-brightness portion loses whiteness.
There was a possibility that black portions would be lost in the low luminance portion.

Accordingly, an object of the present invention is to correct the brightness of a high luminance or low luminance portion so that even if there is a high luminance portion or a low luminance portion in one screen, the image does not become overexposed or underexposed. It is an object of the present invention to provide an automatic image quality device capable of performing the above.

[0016]

According to the present invention, one screen of a digital video signal is divided into a plurality of areas, and the brightness of each area is reduced.
A monitor circuit for monitoring the brightness, and a luminance for each of the regions.
Generates a brightness adjustment signal independently for each area in comparison with the reference value
Brightness adjustment signal generating means for performing
And a contrast control circuit for controlling the luminance of the corresponding area to output a digital video signal.

Further, according to the present invention, in the monitor circuit,
Each area is accumulated by accumulating the image data contained in the area.
The accumulated data is formed for each area, and this accumulated data is
And the brightness adjustment signal generating means outputs
Upper threshold value input means as means for inputting the reference value;
And a lower threshold input means, and output from the monitor circuit.
Is larger than the upper threshold value.
Negative offset value for the high brightness area,
Positive offset value for low brightness areas smaller than
Correcting the brightness for the high brightness area and the low brightness area
Coefficients are calculated using the accumulated data, the upper threshold and the lower threshold.
Brightness adjustment according to the difference of the comparison result comparing the values
The contrast control circuit outputs the signal as a signal.
The above offset value is added to the low frequency component of the digital video signal.
And a high frequency component of the digital video signal.
By multiplying the minute by the coefficient,
To reduce the brightness, increase the brightness for the low brightness area,
Amplifies high-frequency components in high and low brightness areas and images
To provide an automatic image quality adjustment device according to claim also be output from the digital video signal in which the edge enhancement of the.

Further, the present invention relates to the positive and negative offsets.
Values and coefficients are obtained through horizontal and vertical low frequency component extraction means.
Supplied to the contrast control circuit,
Band frequency component extraction means
The positive and negative offset values and coefficients change rapidly between regions
Remove high frequency components so that only low frequency components
Is extracted and transmitted to the contrast control circuit.
To provide an automatic image quality adjustment device.

Further, according to the present invention , an input to the monitor circuit is provided.
Digital video signal is delayed via a delay circuit.
And input to the contrast control circuit,
And an automatic image quality adjusting device that performs a multiplication process .

[0020]

According to the present invention, one screen is divided into a plurality of areas,
The average value of the brightness is calculated for each region, the brightness is suppressed for the region that is too bright, the contrast is adjusted by brightening the region that is too dark, and white or black loss is prevented for each region. Furthermore, high-frequency components in a region that is too bright or a region that is too dark are amplified to correct the contour of the image, thereby improving the image quality in this region.

In the second embodiment, HV-L
By adding the PF, the contrast near the boundary is smoothly changed so that the contrast does not change sharply at the boundary of each area.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a first embodiment of the present invention,
FIG. 2 is a block diagram of an embodiment of the contrast control circuit of the present embodiment, FIG. 3 is a block diagram of an embodiment of the offset coefficient generating means of the present embodiment, and FIG. 7 is a diagram for explaining the operation of the present embodiment. The two-dimensional image to be captured is divided into nine regions 9A to 9I.

In this embodiment, as shown in FIG. 1, a monitor circuit 1, an offset coefficient generating means 2, a delay circuit 3, a contrast control circuit 4, a video signal input terminal 6, an upper threshold input terminal 7, and a lower circuit The contrast control circuit 4 according to the present embodiment comprises a threshold value input terminal 8 and a video signal output terminal 9.
As shown in FIG. 2, low frequency component extracting means 10 (hereinafter also referred to as “LPF”) and high frequency component extracting means 11
(Hereinafter, also referred to as “HPF”), a first adder 12, a second adder 14, and a multiplier 13. The offset coefficient generating means 2 of the present embodiment, as shown in FIG. It comprises an offset generating means 21 and a coefficient generating means 22.

The digital video signal YI input to the video signal input terminal 6 is supplied to the monitor circuit 1 and the delay circuit 3, and the monitor circuit 1 outputs the digital video signal YI as shown in FIG.
The accumulated data in each area obtained by dividing the screen into nine areas 9A to 9I is calculated.

The video signal input terminal 6 according to the embodiment of the present invention corresponds to the output of the conventional A / D converter 33, that is, the input of the adder 34. However, the input signal is not limited to a video camera and is not limited to a video camera. Any signal can be used as long as it is a digital video signal.

The monitor circuit 1 of this embodiment divides one screen into a plurality of areas and accumulates image data included in each area for each area. Therefore, in the conventional example, an adder 34, an H counter 35, V counter 36, decoder 37, data clutch 40, registers 41A, 41B, 41C, gate 4
2A, 42B, and 42C.

The output MOUT of the monitor circuit 1, the upper threshold HI input to the upper threshold input terminal 7, and the lower threshold LO supplied to the lower threshold input terminal 8 are offset by the offset shown in FIG. Supplied to the coring means 20 in the coefficient generating means 2;
Cumulative data MOUT of 9A to 9I output from monitor circuit 1
And the upper threshold HI and the lower threshold LO are compared. The output of the coring means 20 is supplied to an offset generating means 21 and a coefficient generating means 22.

The coring means 20, for example, as shown in FIG.
1, NOR gate 52, AND gate 53, adder 54
The output MOUT of the monitor circuit 1 and the upper threshold input terminal 7 are connected to a subtractor 50, and the output MOUT of the monitor circuit 1 and the lower threshold input terminal 8 are connected to a subtractor 51, The output of the subtractor 50 is supplied to a NOR gate 52,
The output of the subtractor 51 is supplied to an AND gate 53,
Outputs of the R gate 52 and the AND gate 53 are added to an adder 54.
Is supplied to the system. In the circuit shown in FIG.
The sign bit indicates whether the result of the subtraction is positive or negative.
And the AND gate 52 and the AND gate
Output data according to the operation result from the port 53, or
Output or switch. That is, the subtractor 50
Subtracts between MOUT and the upper threshold HI, and MOUT
If the difference is larger, the sign bit becomes 0 and the result of the subtraction is
The inverted data is output from the NOR gate 52. one
On the other hand, if MOUT is less than HI, the sign bit will be 1,
Regardless of the data of the operation result, the output of the NOR gate 52
The force goes to zero. Same for the subtractor 51 and AND gate 53
Then, subtract between MOUT and LO, and if MOUT is greater than LO,
In this case, the sign bit becomes 0 and the output of the AND gate 53
Becomes 0. On the other hand, if MOUT is smaller than LO,
Is 1 and the data of the subtraction result is output to the AND gate 53.
Output from Therefore, the output of the adder 54 is MOUT HI.
If it is larger than the value, add the inverted data of the result of subtracting MOUT and HI.
Output from the arithmetic unit 54, and when MOUT is smaller than LO, MOUT
And LO are output from the adder 54.
In this case, the adder 54 outputs 0.

The offset generating means 21 is, for example, RO
M, when the accumulated data in a certain area is larger than the upper threshold HI in the output of the coring means 20, a predetermined negative offset value OF corresponding to the difference is generated, and If the accumulated data is smaller than the lower threshold LO, a predetermined positive offset value corresponding to the difference
OF is generated, and in other cases, 0 is generated as the offset value OF. The coefficient generating means 22 is constituted by, for example, a ROM, and when the accumulated data of a certain area is larger than the upper threshold value HI or smaller than the lower threshold value LO in the output of the coring means 20, the difference is calculated. Predetermined coefficient according to
Generate CE, otherwise generate 1 as coefficient CE.

The digital video signal YI supplied to the delay circuit 3 is delayed by the same time as the digital video signal YI is input to the monitor circuit 1 and output from the offset coefficient generating means 2. .

As shown in FIG. 2, the output of the delay circuit 3
DY and the offset value OF and the coefficient CE of the output of the offset coefficient generating means 2 are supplied to a contrast control circuit 4.
The output DY of the delay circuit 3 is supplied to the LPF 10 and the HPF 11 of the contrast control circuit 4, and the LPF 10 extracts a low frequency component of the output of the delay circuit 3, and the HPF 11 extracts a high frequency component.

LP which is a low frequency component of the input video signal
The offset value OF between the output of F10 and the output of the offset coefficient generating means 2 is supplied to the first adder 12 and added. The coefficient CE of the output of the HPF 11, which is the high frequency component of the input video signal, and the coefficient CE of the output of the offset coefficient generation means 2 are
And is multiplied. The output of the first adder 12 and the output of the multiplier 13 are supplied to a second adder 14 and added. The output of the contrast control circuit 4 is output via a video signal output terminal 9.

For example, in FIG. 7, when the area 9A is too bright and the area 9I is dark, that is, the accumulated data of the area 9A is larger than the upper threshold HI and the accumulated data of the area 9I is smaller than the lower threshold LO. In the case, the offset coefficient generating means 2
Outputs a negative offset value OF and a coefficient CE corresponding to the difference from the upper threshold HI in the area 9A, and outputs a positive offset value OF corresponding to the difference from the lower threshold LO in the area 9I. Output coefficient CE. These offset value OF and coefficient CE are supplied to the contrast control circuit 4.

In the bright area 9A, the negative offset value OF is added to the low frequency component of the input video signal. For this reason, the luminance of the region 9A that is too bright is suppressed to a predetermined level, and the coefficient value CE is further multiplied by the high frequency component of the input video signal. Emphasis is made.

In the dark area 9I, the above-mentioned positive offset value OF is added to the low frequency components of the input video signal, so that the brightness of the dark area 9A is increased to a predetermined level. Further, since the high frequency component of the input video signal is multiplied by the coefficient value CE, the edges in the image are emphasized to a predetermined level.

As described above, in the present embodiment, the monitor circuit 1 detects an area that is too bright and a dark area from the area obtained by dividing one screen into nine parts, and the area that is too bright in the contrast control circuit 4 determines the brightness. Suppressing, brightening the dark areas, and further enhancing the edge components of the image can improve the contrast according to each area even when one screen contains both dark and overbright parts.

The output of the automatic image quality adjusting device of the present invention can be connected to a receiver, and an image having a black or white loss recorded by a video camera is appropriately corrected to improve the image quality. You can also play.

Next, a second embodiment of the present invention will be described with reference to the drawings. 5 is a configuration diagram of a second embodiment of the present invention, FIG. 2 is a configuration diagram of an embodiment of a contrast control circuit of the present embodiment, and FIG. 3 is a configuration diagram of an embodiment of an offset coefficient generating unit of the present embodiment. is there. This embodiment includes a monitor circuit 1, an offset coefficient generating means 2, a delay circuit 3, a contrast control circuit 4, and a horizontal / vertical low frequency component extracting means 5 (hereinafter also referred to as "HV-LPF").

As in the first embodiment, the contrast control circuit 4 of the present embodiment includes an LPF 10, an HPF 11, a first adder 12, a second adder 14, and a multiplier 13, and generates an offset coefficient according to the present embodiment. Means 2 is also similar to the first embodiment,
It comprises coring means 20, offset generating means 21, and coefficient generating means 22. The HV-LPF 5 has a configuration in which a horizontal LPF and a vertical LPF are connected in series.

In this embodiment, the offset value OF and the coefficient CE of the output of the offset coefficient generating means 2 are equal to the HV-LPF5.
To extract low frequency components in the horizontal and vertical directions of the offset value OF and the coefficient CE, respectively. HV-LP
Low frequency component LOF and coefficient C of the offset value of the output of F5
The low frequency component LCE of E is supplied to the contrast control circuit 4, the low frequency offset value LOF is supplied to the first adder 12, and the low frequency coefficient LCE is supplied to the multiplier 13. H
The connection and operation of the blocks other than the V-LPF 5 are the same as those of the first embodiment.

In the first embodiment of the present invention, since the offset value and the coefficient value are determined for each area of the image, the offset value and the coefficient value are constant within the area, and the signal value having a step at the boundary of the area. Becomes Therefore, in the second embodiment, this signal value is passed through LPFs in the horizontal and vertical directions,
The offset value LOF and the coefficient value LCE are determined so that the high frequency components at the steps are deleted and the boundary of the region becomes smooth.

Therefore, the present embodiment uses the HV-LPF5
In order to extract the low frequency components from the offset value OF and the signal value of the coefficient CE according to the state of each area of the screen generated by the offset coefficient generating means 2, the offset value OF and the coefficient CE Rapid change can be suppressed. For this reason, the contrast gradually changes at the boundary of each region, and more natural contrast control is possible.

[0043]

As described above, according to the present invention, an over-bright area and a dark area are detected by an offset coefficient generating means from an area obtained by dividing one screen in a monitor circuit, and an offset and an offset corresponding to each area are detected. By generating a coefficient, the contrast control circuit suppresses the brightness in an area that is too bright in one screen, increases the brightness in a dark area, and further enhances the edge components of the image according to the state of each area. Even when a dark portion and a too bright portion are mixed in one screen, the contrast can be improved and the outline of the image can be enhanced according to each region.

Further, by providing an HV-LPF for extracting a low-frequency component from the signal of the offset value and the coefficient value, it is possible to moderate the change in contrast at the boundary of each area in one screen. For this reason,
More natural contrast control can be realized.

As described above, conventionally, when a dark portion and a bright portion coexist in one screen, the dark portion is lost in the dark portion or the bright portion is lost in the white portion depending on the aperture state. Conventionally, since one screen is divided into a plurality of areas and the contrast can be controlled in accordance with the state of each area, it is possible to suppress darkening of dark areas and darkening of bright areas and maintain contrast. It has advantages not found in

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a contrast control circuit according to first and second embodiments of the present invention.

FIG. 3 is a configuration diagram of an offset coefficient generation unit according to the first and second embodiments of the present invention.

FIG. 4 is a circuit diagram of the coring means of the present invention.

FIG. 5 is a configuration diagram of a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional example relating to an auto iris device.

FIG. 7 is a diagram for explaining operations of the first and second embodiments of the present invention and a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Monitor circuit 2 Offset coefficient generation means 3 Delay circuit 4 Contrast control circuit 5 HV-LPF 6 Video signal input terminal 7 Upper threshold input terminal 8 Lower threshold input terminal 9 Video signal output terminal 10 Low frequency component extraction means DESCRIPTION OF SYMBOLS 11 High frequency component extraction means 12 1st adder 13 Multiplier 14 2nd adder 20 Coring means 21 Offset generation means 22 Coefficient generation means 30 Image sensor 31 Iris device 32 Input amplifier 33 A / D converter 34 Adder 35 H counter 36 V counter 37 Decoder 38 Latch 39 Microcomputer 40 Data latch 41A, 41B, 41C Register 42A, 42B, 42C Gate

Claims (4)

(57) [Claims] 1. A monitor circuit for dividing one screen of a digital video signal into a plurality of areas and monitoring the brightness of each area, comparing the brightness of each area with a reference value, and generating a brightness adjustment signal.
An automatic image , comprising: a brightness adjustment signal generating unit that is generated independently for each area; and a contrast control circuit that outputs a digital video signal by controlling the brightness of the corresponding area by the brightness adjustment signal. Adjustment device. 2. The image processing apparatus according to claim 1, wherein the monitor circuit includes an image included in each area.
By accumulating image data, accumulated data for each area
And output the accumulated data as the luminance for each area.
The brightness adjustment signal generating means is a means for inputting the reference value.
Upper threshold input means and lower threshold input means as stages
Is provided, and the accumulation for each of the areas output from the monitor circuit is provided.
Calculation data for a high-luminance area larger than the upper threshold
Negative offset value, low brightness smaller than the lower threshold
Positive offset value for the region, the high brightness region and the low
A coefficient for correcting the luminance for the luminance area is calculated by the accumulation data.
Data and the comparison result of comparing the upper threshold value and the lower threshold value
Are output as luminance adjustment signals in accordance with the differences between the digital video signals.
While adding the offset value to the low frequency component,
Multiply the high frequency component of the digital video signal by the coefficient
By doing so , the brightness is suppressed for the high brightness area, and
Brightness is increased, and high-frequency
Digital video signal with amplified image outline
Automatic image quality adjustment device according to claim 1, characterized in also be output from the. 3. The positive and negative offset values and coefficients are horizontal.
The contrast via the vertical low frequency component extraction means
The control circuit supplies the horizontal and vertical low frequency components
The means is provided between the horizontally and vertically adjacent areas with the positive and
Negative offset value, high frequency so that coefficient does not change suddenly
Remove the wave components, extract only the low frequency components, and
3. The automatic image quality adjusting device according to claim 2, wherein the signal is transmitted to a last control circuit . 4. A digital video input to the monitor circuit.
The image signal is delayed through a delay circuit,
Input to the test control circuit to perform the addition and multiplication processing.
The automatic image quality adjustment device according to claim 2, wherein: