JPH07230699A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent voltage drop at a remote side from a power source supply end and to surely perform operation in each memory cell in the direction of a row by dividing a common power source line and connecting them through a power source voltage supplying means performing an amplifying function. CONSTITUTION:Divided points of divided power source lines 2a, 2b to which a common power source line 2 is divided are connected to a power source voltage supplying means 11. The means 11 is constituted by connecting a CMOS inverter 11a and 11b in cascade, a PMOS transistor is arranged at a power source Vcc side, and a Vcc level is obtained at an output end of the CMOS inverter. A potential holding means 12 is connected to a power source line 2a between a fuse 4 connected to a supply terminal 3 of the Vcc and a memory cell 1. The Vcc level is continuously supplied to the means 12 from the terminal 3 through the fuse 4 in a state in which the fuse 4 is not cut, and a node 12b is made a ground level. On the other hand, when a defect of leakage is detected in either of the cell 1, the fuse 4 is cut, and a defective cell is substituted with a redundant cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory having a redundant cell for relieving a defective memory cell, and is particularly used for a memory which requires a reduction in standby current.

[0002]

2. Description of the Related Art In semiconductor memories, it is often required to reduce current consumption during standby (standby). That is, in the memory cell, there is a case where the leakage current flows more than the allowable value although it operates normally and there is no functional problem. If such a memory cell exists, the standby current will increase, so it is desirable to consider it as a defective memory cell and disuse it, and switch it to a redundant memory cell.

FIG. 7 shows a conventional means for preventing such an inconvenience. In FIG. 7, 1 is a memory cell arranged in the row direction, 2 is a common power supply line like a cell, 3 is a power supply voltage V
Power supply terminals 4 for supplying cc to the common power supply line 2 are fuses.

Here, a memory cell in which a leak current exceeding a permissible value is generated is found by using a tester, and the laser fuse 4 connected between the memory cell and the power supply terminal 3 which can be regarded as a defect is blown. As a result, the leak path is cut off and replaced with a spare (redundant) memory cell. Recently, the memory capacity has been increased. Therefore, if the wiring resistance of the common power supply line 2 increases, the power supply voltage to each memory cell 1 becomes far from the terminal 3. As a result, the operating margin is reduced, which is a problem. That is, there is a problem in that the memory capacity has recently been increased and the common power supply line 2 is lengthened.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and in a semiconductor memory having a memory cell array in which memory cells are arranged in a matrix, power is supplied to the memory cells arranged in the row direction. It is possible to replace a memory cell with a leak current larger than the allowable value with a redundant cell and to expect a stable operation without lowering the power supply voltage and increasing the chip size due to an increase in the wiring resistance of the common power supply line to be supplied. It was done like this.

[0006]

According to the present invention, in a semiconductor memory having a memory cell array in which memory cells are arranged in a matrix, power is commonly supplied to a plurality of memory cells in a row direction. Is divided into N (N is an integer of 1 or more), and a common power supply line for supplying power from one end side to the other end side and each divided power supply line obtained by dividing this common power supply line by N are respectively adjacent to each other. The power supply voltage level obtained by amplifying the voltage from the divided power supply line which is interposed and is adjacent to the near side as seen from the one end side for supplying the power supply,
A power supply voltage supply means for supplying the adjacent divided power supply lines farther from the power supply end, a power supply end on one end side of the common power supply line, and a division located first from the power supply end. A fuse interposed between the power supply line and a potential holding means for holding the common power supply line at the ground potential after cutting the fuse, and a line after the fuse is cut, instead of the line where the fuse is cut. A semiconductor memory comprising a redundant cell to be used.

That is, the present invention divides the common power supply line into N,
A power supply voltage supply means for increasing the side effect is provided so as to connect them at each boundary of the division points, and the power supply voltage drop from the divided power supply line closer to the power supply end as seen from the means is increased to the power supply voltage before the drop. By raising the voltage and preventing the voltage drop on the side far from the power supply terminal, the power supply voltage to each memory cell in the row direction is kept high. For this reason, the operation in each memory cell is ensured, the fluctuation of the power supply can be suppressed even in the transient response of the operation, and the common power supply line is kept at the ground potential after the fuse is blown. Stabilization of operation can be expected by eliminating the floating state of the common power supply line after disconnecting. Further, for the plurality of row selection lines, one common power supply line and one fuse can be used, so that the area occupied by the chip can be reduced and the number of fuses to be cut is extremely small. Reliability is improved. This is because the number of memory cells attached to a single common power supply line and row selection line increases under the recent trend toward large-capacity memory. This can also be said that the reliability decreases as the number of times increases.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows only one column of a common power supply line accompanied by memory cells in the row direction in a memory cell array in which memory cells are arranged in a matrix. Is an example of. Therefore, in FIG. 1, parts corresponding to those in FIG. 7 are designated by the same reference numerals.

FIG. 1 shows an example in which the common power supply line 2 is divided into two. The boundary between the dividing points of the divided power supply lines 2a and 2b is connected by the power supply voltage supply means 11. This means 1
1 uses here CMOS inverters 11a and 11b connected in cascade. CMOS inverter
Normally, a PMOS transistor is arranged on the side of the power supply Vcc, so that the power supply Vcc is connected to the output terminal of the CMOS inverter.
A level is obtained and it is preferable.

On the divided power supply line 2a between the fuse 4 connected to the supply terminal 3 of the power supply Vcc and the memory cell 1 closest to the fuse 4, the potential holding means 12 for holding the common power supply line 2 at the ground potential. Is connected to the output terminal 12a. This means 12 is composed of a flip-flop portion of transistors 13 to 15 and a coupling capacitor 16. The operation of this means 12 is such that, in a state where the fuse 4 is not cut, the power source Vc is supplied from the terminal 3 through the fuse 4.
The c (“1”) level is continuously supplied, and the node 1 on the opposite side is supplied.
2b is at "0" level. On the other hand, when a leak defect is detected in any of the memory cells 1 in FIG. 1, the fuse 4 is cut by laser fusing or the like to switch to the redundant cell. When disconnecting the fuse 4,
No power supply Vcc is applied. Therefore, when the power supply Vcc is turned on again after the fuse 4 is cut off, the capacitance 1
The node 12b goes to "1" level via 6 and the node 12a is kept at "0", that is, the ground level, and the common power supply line 2 is kept at the ground level.

2 and 3 are for explaining the operation and effect of the configuration of FIG. Here, FIG. 2A does not include the power supply voltage supply means 11 of FIG. 1, and is equivalent to a conventional example. FIG. 2B shows an equivalent circuit of FIG. Where L is the length of the common power supply line 2,
L / 2 is the length of the divided power supply lines 2a and 2b, i is the current flowing through the common power supply line 2, R is the wiring resistance of the common power supply line, and Va and Va 'are shown in FIGS. 2A and 2B, respectively. ) Is the far-end side voltage. FIG. 3 shows a voltage drop state due to the resistance of the power supply line 2.

That is, as shown in FIG. 2 (b), by dividing the common power supply line 2 into two and arranging a power supply voltage supply means 11 by amplification, the means 11 allows the divided power supply line 2b from its start end to its end. To the contrary, by supplying Vcc again, the voltage drop becomes Va ′ = Va / 2 as shown in FIG. 3 as compared with the conventional example, and the voltage drop can be half that of the conventional example.
Therefore, each memory cell 1 can be supplied with a relatively high power supply voltage with less voltage effect than the conventional example. Therefore, the fluctuation of the power supply is small even in the transient response of the operation, and the operation margin is improved. In addition, since the common power supply line 2 is held at the ground level, stabilization of the operation can be expected.

4 and 5 show a memory cell array (for one common power supply line) when the memory capacity is increased and the wiring resistance of the common power supply line is increased. FIG. 4 shows an embodiment in which the present invention is further embodied, and FIG. 5 uses a common power supply line voltage drop prevention means (Vcc supply via fuse 4), which is conceivable using ordinary means. Indicates. 4 and 5, the common power supply line that can be integrated in the present invention is divided into N parts.

4 and 5, 21, 21, ... Are row selection circuits (row decoders), 22, 22, ... Are row selection lines, that is, word lines, and 23, 23 ,. 2, 2, ... Also indicate power supply lines divided into N. Further, the memory cells 1, 1, ... Are assumed to be static RAM cells having a flip-flop configuration here. The memory cells 1, 1, ... Have common power lines 23, 23 ,.
(FIG. 4), and 2, 2, ... (FIG. 5) respectively, paying attention to one memory cell 1, one of the two lines connected to the row line 22 is stored data of the memory cell 1. For controlling the opening and closing of a switch (transfer gate) (not shown) for energizing a bit line (not shown).
The other of the lines is for controlling the opening / closing of a switch for energizing a bit line (not shown) having a complementary relationship with the stored data and a data having a complementary relationship with the bit line.

Although the memory capacity has recently been increased, since the memory of FIG. 5 is a large capacity memory, the number of common power supply lines 2 and the number of fuses 4 associated therewith and the number of row selection lines 22 are increased. The number of chips increases, the length of one common power supply line and row selection line also increases, and the number of memory cells 1 in these lines also increases, increasing the chip occupying area and increasing the size of one common power supply. There is a high possibility that a leaky memory cell exists in the line or row selection line. Therefore, it becomes necessary to blow a plurality of fuses 4 in the cell array, which causes a reliability problem. However, in the case of FIG. 4, the common power supply line 23 common to each row selection line 22 can be regarded as one, and moreover, only one fuse 4 at the Vcc supply end is required to be cut off, so that the chip occupation area is reduced. The increase is small, and the reliability at the time of cutting the fuse is also improved.

FIG. 6 shows a different embodiment of the power supply means 11. As in the case of the previous embodiment, this means 11 is also arranged so as to divide the common power supply line 23, and the power supply voltage which is about to drop before this line 23 is supplied to the CMOS inverter 3
1. Raise to Vcc by the PMOS transistor 32.

In the case of FIG. 6, the circuit can be made smaller than the two-stage inverter of FIG. 1, and since the power supply voltage Vcc is transmitted to the power supply line 23 via the PMOS transistor 32, the voltage Vcc passes through the transistor 32. Also, the power supply voltage value as it is can be transmitted to the power supply line 23.

[0018]

As described above, according to the present invention, in a semiconductor memory having a memory cell array in which memory cells are arranged in a matrix, a wiring resistance of a common power supply line for supplying power to memory cells arranged in a row direction. It is possible to replace a memory cell having a leak current larger than an allowable value with a redundant cell and to expect a stable operation, without causing a decrease in power supply voltage and an increase in chip size due to an increase in power consumption.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory view of the function and effect of FIG.

FIG. 3 is an explanatory view of the function and effect of FIG.

FIG. 4 is a circuit configuration diagram of an embodiment in which FIG. 1 is further embodied.

5 is a circuit diagram in which a conventional example is improved for comparison with the circuit in FIG.

FIG. 6 is a circuit diagram of a main part of another embodiment of the present invention.

FIG. 7 is a conventional memory circuit diagram.

[Explanation of symbols]

1 ... Memory cell, 2, 23 ... Common power supply line, 2a, 2b ...
Divided power supply lines, 3 ... Power supply terminals, 4 ... Fuse, 11 ... Power supply voltage supply means, 12 ... Potential holding means, 21 ... Row decoder, 22 ... Row selection lines.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/112

Claims (5)

[Claims] 1. In a semiconductor memory having a memory cell array in which memory cells are arranged in a matrix, N (N is an integer of 1 or more) is commonly supplied to a plurality of memory cells in a row direction. A common power supply line for a memory cell, which is divided and supplies power from one end side to the other end side, and each divided power supply line obtained by dividing the common power supply line by N are respectively interposed between the common power supply line and the common power supply line. The power supply voltage level obtained by amplifying the voltage from the adjacent divided power supply line closer to the one end side from which power is supplied is supplied to the adjacent divided power supply line farther from the power supply supply end. The fuse interposed between the power supply voltage supply means, the power supply end on the one end side of the common power supply line, and the divided power supply line located first from the power supply end, and the fuse being cut off , The common power The semiconductor memory for the potential holding means for holding the line at the ground potential, after cutting of the fuse, characterized by comprising a redundancy cell used in place of the line cut the fuse. 2. The semiconductor memory according to claim 1, wherein the fuse is blown for a common power supply line in which a memory cell having a leak current in a standby state exceeds an allowable value. 3. The semiconductor memory according to claim 1, wherein the number of divisions of the common power supply line corresponds to the number of row selection lines for memory cells associated with the common power supply line. 4. The semiconductor memory according to claim 1, wherein the power supply voltage supply means supplies power to the divided power supply lines via PMOS transistors. 5. The semiconductor memory according to claim 1, wherein the memory cell is a static cell having a flip-flop configuration.