JP3545575B2 - Semiconductor memory device and defect repair method therefor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a circuit configuration of a semiconductor memory device such as a static RAM (hereinafter, referred to as an SRAM), and particularly to a technique for suppressing generation of a leak current inside the semiconductor memory device.
[0002]
[Prior art]
A conventional semiconductor memory device includes a redundant circuit, and when a failure (function failure) that prevents normal reading / writing of a memory cell occurs, a row address unit, a column address unit, or each memory cell unit is used. Then, the defective memory cell is replaced. By providing such a redundant circuit in an amount corresponding to the defect rate of the memory cell, the manufacturing yield of the semiconductor memory device can be improved.
[0003]
FIG. 10 is a layout diagram of a conventional semiconductor memory device. The semiconductor memory device of FIG. 10 is divided into four blocks B1 to B4, and a redundant circuit RD1 in the column direction and a redundant circuit RD2 in the row direction are provided in each of the blocks B1 to B4. In the column direction, a plurality of section areas SEC0 to SEC7 are provided for each column address, and replacement with the redundant circuit RD1 is performed for each of the section areas SEC0 to SEC7.
[0004]
FIG. 11 is an enlarged view of one block of FIG. 11 correspond to the section areas SEC0 to SEC7, and a word line drive circuit WSL is provided between two adjacent section areas. A cell ground power supply line VSS is provided in each of the section areas SEC0 to SEC7, and these cell ground power supply lines VSS are respectively connected to pad ground power supply lines VSS 'formed outside the section areas SEC0 to SEC7. .
[0005]
One end of each section area SEC0 to SEC7 is connected to a sense amplifier S / A0 to S / A7 for amplifying a read signal from a memory cell. These sense amplifiers S / A0 to S / A7 are formed at symmetrical positions with respect to an alternate long and short dash line shown in FIGS.
[0006]
[Problems to be solved by the invention]
By the way, when the fine processing technology advances as in recent years, the wiring width and the wiring interval are correspondingly reduced, so that a failure (standby failure) in which a signal line such as a bit line and the ground line VSS are short-circuited easily occurs. Become. When such a standby failure occurs, a through current flows from the power supply line VCC to the ground line VSS, and the power consumption of the semiconductor memory device increases.
[0007]
However, the redundancy circuits RD1 and RD2 shown in FIGS. 10 and 11 can relieve a function failure but cannot relieve a standby failure. Even if a memory cell having a standby failure is replaced with the redundant circuits RD1 and RD2, a leak current flows, and the manufacturing yield cannot be improved.
[0008]
The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor memory device capable of reliably relieving a standby failure in which a leak current flows through a ground line. .
[0009]
In order to solve the above-described problem, the present invention is directed to a semiconductor memory device including a redundant circuit capable of replacing a defective memory cell, wherein the semiconductor memory device is formed inside each section area which is an address unit in a column direction. A cell ground power supply line connected to the ground terminals of all memory cells in the memory, a pad ground power supply line formed outside each section area, and a corresponding cell ground power supply line provided for each section area. And a plurality of fuses interposed in parallel with each other between the pad ground power supply line and a sense amplifier connected to one end of the section region, wherein the pad ground power supply line and the plurality of fuses are It is formed on the side facing the sense amplifier with the memory cell region in the section region interposed.
[0010]
The present invention provides a semiconductor memory device having a redundant circuit capable of replacing a defective memory cell, wherein the semiconductor memory device is formed inside each section area, which is an address unit in a column direction, and is connected to ground terminals of all memory cells in the section area. A connected cell ground power supply line, a pad ground power supply line formed outside each of the section areas, and a corresponding one of the cell ground power supply lines and the pad ground power supply line provided for each section area. A plurality of fuses interposed in parallel with each other, and a sense amplifier connected to one end of the section region, wherein the pad ground power supply line and the plurality of fuses are connected to a memory cell region in the section region. It is formed between the sense amplifier.
[0011]
The present invention provides a semiconductor memory device having a redundant circuit capable of replacing a defective memory cell, wherein the semiconductor memory device is formed inside each section area, which is an address unit in a column direction, and is connected to ground terminals of all memory cells in the section area. A connected cell ground power supply line, a pad ground power supply line formed outside each of the section areas, and a corresponding one of the cell ground power supply lines and the pad ground power supply line provided for each section area. A plurality of fuses interposed in parallel with each other, wherein the pad ground power supply line is formed on both sides of the tip of the cell ground power supply line, and the tip of the cell ground power supply line, The plurality of fuses are connected in parallel with the pad ground power supply lines formed on both sides.
[0014]
According to the present invention, the number of fuses connected in parallel is set so that the potential difference between both ends of the plurality of fuses connected in parallel is equal to or less than a predetermined voltage.
[0015]
According to the present invention, the section circuit can be replaced with the redundant circuit in units of the section area, and when a failure occurs in which leakage current flows through the cell ground power supply line in the section area, the section area is replaced with the redundant circuit. The fuse is replaced with a circuit, and all the fuses corresponding to the section area are cut.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a semiconductor memory device to which the present invention is applied will be specifically described with reference to the drawings. Hereinafter, an SRAM will be described as an example of a semiconductor memory device.
[0017]
[First Embodiment]
FIG. 1 is a layout diagram of a first embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is an enlarged view of one block of FIG. The semiconductor memory device of FIG. 1 is divided into four blocks B1 to B4 as shown in FIG. 1A, and each of the blocks B1 to B4 has a plurality of section areas SEC0 to SEC0 as shown in FIG. SEC7, redundant circuit RD1 for replacing defective cells in section units, redundant circuit RD2 for replacing defective cells in row address units, fuse groups FUSE0 to FUSE7 provided for each section area, and word lines provided between section areas And a selection circuit WSL.
[0018]
The section areas SEC0 to SEC7 are provided in units of addresses in the column direction, and each section area is formed with a cell ground power supply line VSS circumferentially. These cell ground power lines VSS are connected to the ground terminals of all the memory cells in the section area. Outside the section areas SEC0 to SEC7, pad ground power supply lines VSS 'are formed in parallel with the direction in which the section areas are arranged. Each cell ground power supply line VSS and pad ground power supply line VSS' are connected to a fuse group. They are connected via FUSE0 to FUSE7.
[0019]
Further, sense amplifiers S / A0 to S / A7 for amplifying a read signal from a memory cell are connected to one end of each of the section areas SEC0 to SEC7 symmetrically with respect to an alternate long and short dash line L as in FIG. I have.
[0020]
As shown in detail in FIG. 2, the fuse groups FUSE0 to FUSE7 are formed at positions facing the sense amplifiers S / A0 to S / A7 with the memory cell region SEL in each section region SEC0 to SEC7 interposed therebetween. I have. As shown in detail in FIG. 2, the fuse groups FUSE0 to FUSE7 have a plurality of fuses F connected in parallel between the cell ground power supply line VSS and the pad ground power supply line VSS '.
[0021]
Next, the operation of the semiconductor memory device of FIG. 1 will be described. When all the memory cells in the section area are normal, all the fuses F corresponding to the section area are conductive, and the cell ground power supply line VSS and the pad ground power supply line VSS 'are conductive.
[0022]
On the other hand, when a defective memory cell is included in a part of the section area, for example, the section area SEC7 in FIG. 1B, the address of the section area SEC7 is set in a decoding circuit described later. Accordingly, when this address is input from the outside, the redundancy circuit RD1 is selected without selecting the section area SEC7.
[0023]
At this time, by cutting all the fuses F corresponding to the section region SEC7, the cell ground power supply line VSS is disconnected from the pad ground power supply line VSS '. Therefore, even if a standby failure occurs in the section area SEC7, no leak current flows through the cell ground power supply line VSS and the pad ground power supply line VSS '.
[0024]
By the way, since the fuse F shown in FIG. 2 is generally formed using polysilicon, its resistance is higher than that of a metal wiring such as Al or Au. For example, the sheet resistance of the fuse element layer is r (Ω / μm ² ), the fuse area is S = L (μm) × W (μm), the cell current passing through the transfer gate in the memory cell is Ic (μA), and the section is When the number of parallel connections of the fuse F per area is Nx and the number of columns per section area is Nc, the voltage rise ΔV of the ground line VSS of the memory cell is expressed by the following equation (1).
ΔV = (r × L / W) / Nx × Ic × Nc (1)
In the equation (1), sheet resistance r = 15 (Ω · m), fuse area S = 13.6 μm × 1.2 μm, cell current Ic passing through a transfer gate in a memory cell = 170 ± 20 μA, one section area The relationship between the voltage rise ΔV of the ground line VSS of the memory cell and the number Nx of fuses connected in parallel when the number of columns per unit Nc = 64 is represented by a curve as shown in FIG.
[0025]
As is apparent from FIG. 3, in order to suppress the voltage rise ΔV within 0.05 V, it is necessary to set the number of parallel connections Nx of the fuse F to 50 or more, and to suppress the voltage rise ΔV within 0.1 V. , The number Nx of fuses connected in parallel needs to be 20 or more. If the voltage rise ΔV is suppressed to within 0.1 V, no practical problem will occur. Therefore, it is sufficient to connect at least 20 fuses F in parallel.
[0026]
FIG. 4 is a circuit diagram showing an example of a decode circuit in the semiconductor memory device of FIG. The decoding circuit in FIG. 4 includes a row decoding unit 11 for decoding a row address, a column switch unit 12 for switching between selection / non-selection in a column direction, and a redundancy decoding unit 13 for decoding an address to be replaced with a redundancy circuit RD1. And a section decoding section 14 for decoding a section area.
[0027]
When replacing with the redundant circuit RD1, the fuse of the section decode unit 14 in FIG. 4 is cut and a part of the fuse of the redundant decode unit 13 is cut to replace the section area including the defective memory cell. The redundant circuit RD1 is selected.
[0028]
In the decoding circuit of FIG. 4, a redundant decoding unit 13 is arranged adjacent to a row decoding unit 11 and a section decoding unit 14 that perform normal decoding, and the circuit configuration of the redundant decoding unit 13 is changed to the row decoding unit 11 or the section. Since it is the same as the decoding unit 14, the time until the external address signal reaches the memory cell can be made substantially constant regardless of whether replacement with the redundant circuit RD1 is performed.
[0029]
FIG. 5 is a circuit diagram showing another configuration example of the decoding circuit. In the decoding circuit shown in FIG. 5, a redundant decoding unit 13 is arranged at a place apart from the row decoding unit 11 and the section decoding unit 14. In this case, there is a possibility that the time required for the external address signal to reach the memory cell may be shifted between the case where replacement with the redundant circuit RD1 is performed and the case where replacement is not performed. Thus, the delay times can be made substantially equal.
[0030]
As described above, in the first embodiment, the plurality of fuses F are connected in parallel between the cell ground power supply line in the section area and the pad ground power supply line outside the section area, and the standby is performed in the section area. When a failure occurs, replacement with the redundant circuit RD1 is performed, and all the corresponding fuses are cut, so that the standby failure can be relieved.
[0031]
[Second embodiment]
In the second embodiment, fuse groups FUSE0 to FUSE7 are formed at different locations from the first embodiment.
[0032]
FIG. 6 is a layout diagram of the second embodiment, showing one block constituting a part of the semiconductor memory device in an enlarged manner. As shown in FIG. 6, the fuse groups FUSE0 to FUSE7 are provided below the section areas SEC0 to SEC7, that is, the memory cells SEL and the sense amplifiers S / A0 to S / A7 in each section area SEC0 to SEC7. It is formed between. As shown in FIG. 7, each of the fuse groups FUSE0 to FUSE7 includes a plurality of fuses F connected in parallel between a cell ground power supply line VSS and a pad ground power supply line VSS '.
[0033]
Also in the second embodiment, when a standby failure occurs in each of the section areas SEC0 to SEC7, replacement with the redundant circuit RD1 is performed, and all the fuses F provided corresponding to the section area are replaced. Disconnect. As a result, no leak current flows through the cell ground power supply line VSS in the section region.
[0034]
The decoding circuit according to the second embodiment may be configured as shown in FIGS.
[0035]
[Third embodiment]
In the third embodiment, a large number of fuses are stacked so that many fuses can be connected in parallel even in a narrow area.
[0036]
FIG. 8 is a layout diagram of the third embodiment, showing one block constituting a part of the semiconductor memory device in an enlarged manner. The third embodiment includes redundant circuits RD2 and RD1 in the row direction and the column direction, respectively, as in the first and second embodiments. In the column direction, replacement of memory cells is performed in section units.
[0037]
In each of the section areas SEC0 to SEC7 of the third embodiment, similarly to the first and second embodiments, a cell ground power supply line VSS is formed circumferentially, and the tip of the cell ground power supply line VSS is formed. Pad ground power supply lines VSS 'are arranged on both sides. That is, the pad ground power supply line VSS 'is disposed so as to sandwich the tip of the cell ground power supply line VSS from both sides, and is provided between the cell ground power supply line VSS and the pad ground power supply lines VSS' disposed on both sides thereof. As shown in FIG. 9, a plurality of fuses F are connected in parallel.
[0038]
With such a structure, even when the width in the word line direction is narrow, a large number of fuses F can be connected in parallel, and the potential difference between both ends of the fuses can be reduced.
[0039]
FIG. 9 illustrates an example in which the fuses F are stacked in two stages. However, if there is room in the vertical direction of the chip, the fuses F may be stacked in three or more stages.
[0040]
The decoding circuit according to the third embodiment may be configured as shown in FIGS.
[0041]
By the way, in the above-described first to third embodiments, an example has been described in which a total of eight section areas are provided. However, the number of section areas, the number of blocks, and the number of replaceable redundant circuits RD1 and RD2 are limited. Is not particularly limited. In particular, if the number of redundant circuits RD1 and RD2 is increased, a plurality of row address areas and section areas can be replaced at the same time, so that the yield can be improved.
[0042]
Further, the present invention can be applied to various semiconductor storage devices such as a DRAM and an EEPROM other than the SRAM.
[0043]
【The invention's effect】
As described above in detail, according to the present invention, a plurality of fuses are connected in parallel between a cell ground power supply line formed inside each section region and a pad ground power supply line formed outside the section region. Since the fuses are cut, leakage current does not flow through the ground line by cutting these fuses, and standby failure can be reliably relieved.
[Brief description of the drawings]
FIG. 1 is a layout diagram of a first embodiment of a semiconductor memory device according to the present invention.
FIG. 2 is a diagram illustrating an arrangement of fuses according to the first embodiment.
FIG. 3 is a diagram showing a relationship between the number NX of fuses connected in parallel and a voltage rise ΔV of a cell ground power line VSS.
FIG. 4 is a circuit diagram showing an example of a decode circuit in the semiconductor memory device of FIG. 1;
FIG. 5 is a circuit diagram showing another configuration example of a decoding circuit.
FIG. 6 is a layout diagram of a second embodiment.
FIG. 7 is a diagram showing an arrangement of fuses according to the second embodiment.
FIG. 8 is a layout diagram of a third embodiment.
FIG. 9 is a diagram illustrating an arrangement of fuses according to a third embodiment.
FIG. 10 is a layout diagram of a conventional semiconductor memory device.
FIG. 11 is an enlarged view of one block shown in FIG. 10;
[Explanation of symbols]
11 Row Decode Unit 12 Column Switch Unit 13 Redundant Decode Unit 14 Section Decode Units B1 to B4 Block F Fuse FUSE0 to 7 Fuse Group RD1, RD2 Redundant Circuit SEC0 to 7 Section Area VSS Cell Ground Power Supply Line VSS 'Pad Ground Power Supply Line

Claims (5)

In a semiconductor memory device having a redundant circuit capable of replacing a defective memory cell,
A cell ground power supply line formed inside each section area, which is an address unit in the column direction, and connected to the ground terminals of all memory cells in the section area;
A pad ground power supply line formed outside each section area;
A plurality of fuses provided for each section area and interposed in parallel between the corresponding cell ground power supply line and the pad ground power supply line,
A sense amplifier connected to one end of the section area,
The semiconductor memory device according to claim 1, wherein the pad ground power supply line and the plurality of fuses are formed on a side facing the sense amplifier with a memory cell region in the section region interposed therebetween. In a semiconductor memory device having a redundant circuit capable of replacing a defective memory cell,
A cell ground power supply line formed inside each section area, which is an address unit in the column direction, and connected to the ground terminals of all memory cells in the section area;
A pad ground power supply line formed outside each section area;
A plurality of fuses provided for each section area and interposed in parallel between the corresponding cell ground power supply line and the pad ground power supply line,
A sense amplifier connected to one end of the section area,
The semiconductor memory device according to claim 1, wherein said pad ground power supply line and said plurality of fuses are formed between a memory cell region in said section region and said sense amplifier. In a semiconductor memory device having a redundant circuit capable of replacing a defective memory cell,
A cell ground power supply line formed inside each section area, which is an address unit in the column direction, and connected to the ground terminals of all memory cells in the section area;
A pad ground power supply line formed outside each section area;
A plurality of fuses provided for each section area and interposed in parallel with each other between the corresponding cell ground power supply line and the pad ground power supply line ,
The pad ground power supply line is formed on both sides of the tip of the cell ground power supply line,
2. The semiconductor memory device according to claim 1, wherein the plurality of fuses are connected in parallel between a leading end of the cell ground power supply line and the pad ground power supply lines formed on both sides thereof. 4. The semiconductor memory device according to claim 1, wherein the number of the fuses connected in parallel is set so that a potential difference between both ends of the plurality of fuses connected in parallel is equal to or less than a predetermined voltage. Replacement with the redundant circuit is possible in units of the section area,
In the case where a defect in which a leak current flows through the cell ground power supply line occurs in the section area, the section area is replaced with the redundant circuit, and all the fuses corresponding to the section area are cut. 5. The method of remedying a defect in a semiconductor memory device according to claim 1, wherein:

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