KR0167676B1 - Semiconductor memory device being able to block queing current by defect - Google Patents

Abstract

Technical Field [0001] The present invention relates to a semiconductor memory device which deactivates a core circuit region for redundancy to a defect.

2. Technical problem to be solved by the present invention: The present invention improves the redundancy efficiency, disables the defective core circuit area in the test, eliminates the generation of standby current due to process defects, and eliminates the defective core circuit area. A replaceable semiconductor memory device is provided.

3. Summary of Solution to Invention

The present invention relates to a plurality of sub-memory arrays arranged in a matrix and having a plurality of word lines, and a plurality of equalization circuits and sense amplifiers arranged in a row direction between the sub-memory arrays and the sub-memory arrays. A semiconductor memory device having a plurality of word line driving blocks arranged in a column direction and having a plurality of sub word line drivers, the plurality of global word lines and the sub memory extending in a column direction between the sub memory arrays. A plurality of global equalization lines extending in a column direction between the arrays, a plurality of global sense amplifier control lines extending in a column or row direction between the sub-memory arrays, and between the sub-memory arrays. A plurality of rows or columns Global ground voltage lines, local lines connected to at least one of the equalization circuits and sense amplifiers, the subword line drivers, and the global ground voltage lines, the global lines, and the local lines. And core isolation control circuitry that controls the electrical connections between the lines.

4. Significant Uses of the Invention The present invention is suitably used in semiconductor memory devices that include redundancy for defects.

Description

Semiconductor memory device that can block standby current caused by a fault

1 is a view showing a conventional semiconductor memory device performing a redundancy function for a sub-memory array when a bridge type defect occurs.

2 is a diagram illustrating a configuration of a sub memory array of a semiconductor memory device according to the present invention.

3 shows a schematic configuration of a periphery of one core separation control circuit according to the present invention.

4 is a block diagram showing a configuration of a core separation control circuit according to the present invention.

5 is a circuit diagram of the core separation enable circuit of FIG.

6A is a circuit diagram of the word line drive switch of FIG.

6b is a circuit diagram of the ground voltage switch circuit of FIG.

6C is a circuit diagram of a word line driver controlled by a word line driver switch circuit and a ground voltage switch circuit.

FIG. 7 is a circuit diagram illustrating a connection state between the sense amplifier switch and the sense amplifier of FIG. 4.

8 is a circuit diagram showing a connection state between an equalization switch circuit and an equalization circuit of FIG.

* Explanation of symbols for main parts of the drawings

XG: Global word line driving circuit 100: Core separation control circuit

RD: Low Decoder 10: Core Separation Activation Circuit

EQ: Equalization circuit 30: Word line drive switch circuit

SA: Sense amplifier 50: Ground voltage switch circuit

WD: Word line drive block 70: Sense amplifier switch circuit

SWD: Subword Line Driver 90: Equalization Switch Circuit

SB: Sub memory block ψF / ψFB: Separate signal

ψXiG: Global word line drive signal ψXiL: Local word line drive signal

ψEQG: Global equalization signal ψNG: Global sense amplifier control signal

LA, LAB: Local sense amplifier control signal GVss: Global ground voltage

LVss: Local Ground Voltage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test for redundancy of a semiconductor memory device, and more particularly to a semiconductor for deactivating a corresponding core circuit region when a defect occurs in a core circuit around a memory cell that controls data write and read operations for the memory cell. It relates to a memory device.

In general, in a semiconductor memory device, for example, a large-capacity, high-density semiconductor memory device of 256 Mb or more, the size of the chip increases, while the design rule becomes more fine, which makes the process more complicated. This is because the limit of design rule is set to a fine line width of 0.5 μm or less, and defects such as a bridge (short phenomenon between conductive lines caused by dust particles) are caused by relatively smaller dust particles. It became frequent. This bridge defect is a factor that causes unnecessary current to flow even when the semiconductor memory device is in a standby state because it always electrically undesirably connects the conductive lines (or signal transmission lines) arranged at a high density. This, in turn, lowers the yield of the semiconductor memory device and increases the manufacturing cost.

After the manufacturing process is completed, the defective part cannot perform normal operation, so it is a spare element that blocks the path of control signal, voltage and data by using fuse cutting method and performs the same configuration and function. Will be replaced. This is called redundancy.

Known defect repair techniques, that is, redundancy technology, block redundancy replaced by memory block units, low redundancy replaced by word lines, column redundancy replaced by bit lines (or data lines), and redundancy by memory cell units Etc. Such redundancy technology has been continuously developed in a direction to improve redundancy efficiency.

FIG. 1 is a redundancy technique proposed by Hitachi of Japan to ISSCC issued on February 24, 1993, and shows a redundancy method for submemory array relief applicable to 256 Mb dynamic RAM. If the word line WL and the data line DL (or the bit line) are shorted in the sub memory array 3 of any of the plurality of divided sub memory arrays due to the above-described bridge defect, the word is in the standby state. Since the line WL has a potential of OV and the data line DL has a potential of Vcc / 2, current of the word line flows from the data line. Since the precharge voltage of Vcc / 2 applied to the data line is supplied to each sub-memory array from the Vcc / 2 voltage generation circuit arranged independently in the peripheral circuit area, as a result, the data line (DL) from the power supply of Vcc / 2 is supplied. A current path leading to a) -word line WL-ground voltage Vss is formed. Thus, in FIG. 1, the fuse ROM 11 does not transmit the Vcc / 2 voltage line HVD and the self-rate line voltage line VPL supplied to the sub memory array 3 to the sub memory array 3. Power switch 5 controlled by fuse ROM 9 with a spare memory array 1 having its connection disconnected at the controlled power switch 7 and having the same number of memory cells as sub-memory array 3. Connect the cell plate voltage line (VPL) and Vcc / 2 voltage line (HVD) through. The simultaneous connection of the cell plate voltage line VPL is because the possibility of bridge defects between the cell plate 2 and the word line WL and the data line DL during the memory cell process is also great.

Thus, the conventional redundancy technique shown in FIG. 1 can be replaced with a spare memory array when a bridge defect in the sub memory array occurs. However, in a semiconductor memory device having a capacity of 256 Mb or more, the area of the core circuits in the column direction such as sense amplifiers, separation gates, and equalization circuits is relatively larger than the area occupied by the memory cells.

In addition, since the vertical height of the core circuit region is relatively lower than that of the memory cell region in which word lines and bit lines including the stacked cell capacitor structure are formed in respective layers, dust particles are formed during the process. More are gathered into the core circuit area. Therefore, more frequent bridge defects may occur in the core circuit area. In addition, the signal transmission lines arranged in the core circuit region have a larger number of metal lines or silicide lines having greater electrical conductivity than the signal conductance of the memory cell region, so that a larger standby current flows in the memory cell region. do.

As such, despite the need for relief of core circuit areas in which bridge defects caused by dust particles are substantially more serious, the conventional reader redundancy technique as shown in FIG. 1 has not provided a solution.

As such, even if a bridge defect is found in the core circuit area as described above in the test procedure, the conventional technology has no choice but to replace the entire sub memory array including the defective core circuit area. In fact, even though only a part of the defective core circuit area in one sub-memory array is prevented from using the entire sub-memory array, there is a disadvantage in not only waste of manufacturing cost but also redundancy efficiency.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of improving redundancy efficiency. Another object of the present invention is to provide a semiconductor memory device capable of deactivating a defective core circuit region in a test of the semiconductor memory device. Another object of the present invention is to provide a semiconductor memory device capable of eliminating the generation of standby current due to a process defect. It is another object of the present invention to provide a semiconductor memory device which can replace a defective core circuit region. In order to achieve the object of the present invention, the present invention provides a plurality of sub-memory arrays arranged in a matrix and having a plurality of word lines, and a plurality of equalization circuits arranged in a row direction between the sub-memory arrays. And a plurality of word line driving blocks arranged in a column direction between sense amplifiers and the sub memory arrays, the plurality of word line driving blocks comprising a plurality of sub word line drivers. A plurality of global word lines extending in a row, a plurality of global equalization lines extending in a column direction between the sub memory arrays, and a plurality of glows extending in a column or row direction between the sub memory arrays Full sense amplifier control lines and the sub-memory arrays. A plurality of global ground voltage lines extending in a row or column direction, and connected to at least one of the equalization circuits and sense amplifiers, the subword line drivers, and the global ground voltage lines. And a core separation control circuit for controlling electrical connections between the global lines and the local lines.

According to the present invention, it is possible to suppress the generation of wasted standby current due to bridge defects or the like and to improve the reliability of the semiconductor memory device by enabling the application of a new redundancy method.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the core circuit area refers to a data area between memory cells and word lines and bit lines in the memory array area, that is, between memory cells and peripheral circuits (areas in which buffers, decoders, and input / output circuits are arranged). It refers to the circuit elements that sense and amplify and transmit the circuit, including word line driving circuits, sense amplifiers, equalization and precharge circuits, circuit areas corresponding to the separation gates, and signal transmission lines for electrical connection therebetween. It must be understood. In addition, the present invention relates to a device for preventing the use of a core circuit area when a defective core circuit area is found in a test process, and to the extent that it is replaced with another core circuit area in a spare memory array. Related information will not be provided in the Examples.

However, the technology for replacing the defective core circuit area with the spare core circuit area may be easily applied by those skilled in the art with reference to the known redundancy technology.

2 shows a configuration of a sub memory array according to the present invention. In FIG. 2, signal transmission lines, input / output lines, and separation gates related to memory cell selection and word line driving are not shown. The memory array shown in FIG. 2 should be regarded as one memory bank 64Mb if the semiconductor memory device to which the present invention is applied is 256Mb of dynamic RAM divided into four 64Mb memory banks (or memory mats). . Therefore, each sub memory array (SB-) SMS has a storage capacity of 512 Kb (512 word lines and 1024 bit lines). Each of the row decoders RDD-RD15 arranged in the row direction generates low decoding signals for selecting word lines of eight sub-memory arrays arranged in the column direction.

According to the split word-line drive scheme employed in high-density dynamic rams, one low decoding signal is a word line drive block (WD) arranged between sub-memory arrays arranged in each column direction. In one block, 512 subword line drivers are arranged, and four subword line drivers are controlled. The global word line driver circuit XG- arranged in the row direction with the row decoders supplies a word line drive signal to the subword line driver in the word line drive block WD-. Sense amplifiers SA- and equalization circuits EQ- shared by adjacent sub-memory arrays are arranged between the sub-memory arrays in the row direction in the column direction.

In the memory array according to the present invention, the core separation control circuit 100 is disposed between the word line driving blocks WD- in the row direction to cover four sub memory arrays, and the sense amplifier and the equalization circuit in the column direction. It is located between the areas where is located. That is, one core separation control circuit 100 controls core circuits related to four sub memory arrays adjacent to each other.

3 shows four sub memory arrays (SB2 / 2, SB2 / 3, SB3 / 3) and two word line driving blocks (WD2) in FIG. 2 to show the core isolation control circuit 100 and its surroundings in detail. / 3, WD3 / 3) is shown as an example. The low decoding line ψ NWEi (which uses the same reference numerals for the signal and the line through which the signal is transmitted) that extends the sub-memory array and the top of the word line driving block in the column direction is a strap located in the area of the word line driving block. Four subword line drivers (not shown in FIG. 3) are connected through the ping region 12. As shown in FIG. 3, one word line driving block (WD2 / 3 or WD3 / 3) is connected to two neighboring sub-memory arrays (SB2 / 2 and SB3 / 2, or SB2 / 3 and SB3 / 3). It is designed to drive one-half of the word lines (256 if one sub-memory array has 512 word lines). The strapping region 14 displayed on the word line driving block is a portion in which one word line WL is connected to one subword line driver (one word line corresponds to one subword line driver). On top of the equalizing circuits (EQ3 / 1, EQ3 / 2) and sense amplifiers SA3 / 1, SA3 / 2 disposed between the sub-memory arrays SB2 / 2 and SB3 / 2 and between SB2 / 3 and SB3 / 3, respectively. The global sense amplifier control line? XiB, the global equalization line? EQG and the global sense amplifier control line? NG extend. ψXiB, ψEQG and ψNG are connected to the core separation control circuit 100 through the respective strapping regions 16, 18 and 22 at the top of the core separation control circuit 100.

In addition, the global ground voltage line GVss extends in the low direction on the core separation control circuit 100 and the word line driving blocks WD2 / 3 and WD3 / 3, and the core separation control is performed through the strapping region 24. Is connected to the circuit 100. The local equalization signal? EQiL outputted from the core separation control circuit 100, the local sense amplifier control signal LA / LAB, the word line drive signal? XiL, and the local ground voltage line LVss are equalization circuits (EQ3 / 1, EQ3 / 2) sense amplifiers, respectively. (SA3 / 1, SA3 / 2) and word line drive blocks (WD2 / 3, WD3 / 3). When the core separation control circuit 100 has a defect in the core circuit region (hereinafter referred to as a core circuit unit) shown in FIG. 3, the global lines ψEQG, ψNG, ψXiG, GVss and the local lines ψEQiL, LA / LAB, ψLVs) is to intervene.

4 shows the internal structure of the core separation control circuit 100. As shown in FIG. 4, the separation signal? F / ψFB generated from the core separation activation circuit 10 is a word line driving switch circuit 30, a ground voltage switch circuit 50, a sense amplifier switch circuit 70, and the like. Commonly applied to the equalizing switch circuit 90. The signal ψ R input to the core isolation activation circuit 10 is a signal corresponding to the low address strobe signal RASB, and is activated at a high level in response to the RASB being activated at a low level. The word line drive switch circuit 30 interrupts the connection between? XiG and? Xil under the control of? F /? FB. The ground voltage switch circuit 50 controls the connection between the GVss and the LVss under the control of? F /? FB. The sense amplifier switch circuit 70 controls the connection between ψNG and LA / LAB by controlling ψF / ψFB. The equalization switch circuit 90 interrupts the connection between ψEQG and ψEQL under the control of ψF / ψFB.

Referring to FIG. 5, the core isolation activation circuit 10 is connected between the fuse 21 connected between the power supply voltage and the fuse detection node 23, the fuse detection node 23 and the ground voltage, and a gate is connected to ψR. The defect state is detected by using the connected NMOS transistor 25. Controlling the cutting of the fuse 21 is made by a combination signal of row and column addresses related to the defect.

The gate of the MOS transistor 26 connected between the fuse detection node 23 and the ground voltage is connected to the output terminal of the inverter 27 which inverts the logic level of the fuse detection node 23. The output of inverter 17 is generated at ψ F through two inverters 28, 29 connected in series. ψ FB is generated as the output of the inverter 28. As shown in Fig. 6A, the word line drive switch circuit 30 has a common input between the inverter 32 for inputting ψXiG, the inverter 34 for outputting the inverter 32, and the inverters 32, 34. It is made up of an MOS transistor 38 connected between the source node 36 and the ground voltage and having a gate connected to ψ FB. Ψ XiLB (logic inversion signal of ψ XiLB) is generated from the output terminal of the inverter 32 and ψ XiL is generated from the output terminal of the inverter 34. While ψFB is active at a low level, the isolation signal ψFB (the logic inversion signal of ψF) controls the turn-on and turn-off of the MOS transistor 38 which connects the inverters 32, 34 to ground voltage. In this case, since the word line drive switch 30 does not operate, the global word line drive signal? XiG is not supplied to the local word line drive signal? XiL.

Referring to FIG. 6B, the ground voltage switch circuit 50 is connected to the MOS transistor 52 for a switch in which a channel path is connected between the global ground voltage line GVss and the local ground voltage line LVss, and the gate is connected to ψ FB. Is done. Here again, when ψ FB is activated at a low level, since the MOS transistor 52 is turned off, the global ground voltage is not supplied to the local ground voltage.

FIG. 6C is a subword connected to the local word line drive signals? XiL and? XiLB supplied through the word line driver circuit 30 of FIG. 6A and the local ground voltage LVss supplied through the ground voltage switch circuit 50 of FIG. 6B. Show the line driver (SWD). A source of the PMOS transistor 55 whose gate is connected to the loading coding signal? NWEB is connected to the local word line driving signal? XiL and the drain is connected to the word line WS. A source of the MOS transistor 57 having a drain connected to the word line WL and a gate connected to ψNEWB is connected to the local ground voltage line LVss.

In addition, the gate of the NMOS transistor 58 having a drain connected to the word line WL is connected to ψXiLB and the source is connected to LVss.

In the sense amplifier switch circuit 70, as shown in FIG. 7, the gate of the switching enmo MOS transistor 72 whose drain is connected to the global sense amplifier control signal? NG is connected to the disconnection signal? B.

Between the switching node 74 located on the source side of the MOS transistor 72 and the ground voltage, an MOS transistor 76 having a gate connected to ψ F is connected.

The gate of the NMOS transistor 78 connected between the control node 79 of the sense amplifier 200 (SA: N-type sense amplifier) and the ground voltage is connected to the switching node 74.

Therefore, when the separation signal ψ F is activated to a high level, the sense amplifier 200 does not operate because the ENMO transistor 76 is turned on and the ENMO transistor 78 is turned off. (The local sense amplifier control signal LAB is Inactive)

In FIG. 7, only the configuration of the n-type sense amplifier is shown, but the local sense amplifier control signal LA may not be driven when ψF is activated to a high level even in the case of the type sense amplifier.

The equalization switch circuit 90 shown in FIG. 8 is configured in the same manner as the word line drive switch circuit 30 of FIG. 6A. That is, the global equalization signal ψEQG is generated as the local equalization signal ψEQL through two series-connected inverters 92 and 94 and is connected between the common source node 96 and the ground voltage of the inverters 92 and 94. Is connected to the separation signal ψ FB.

The local equalization signal? EQL supplied through the inverter 94 is commonly connected to the gates of the MOS transistors constituting the known local equalization circuit 300.

Similarly to the word line drive switch circuit 30 described above, the equalization switch circuit 90 is connected to the gate of the enmo transistor 98, so that FB is brought to a low level by address information related to a defect. When activated, it is deactivated and thus prevents the global equalization signal? EQG from being supplied to the local equalization circuit 300.

As described above, the present invention provides a memory array capable of interrupting a current path to a corresponding core circuit unit (the range of this unit can be set by adjusting appropriately) when a defect due to bridge phenomenon or the like is found in the core circuit area. It has the effect of providing a structure.

Therefore, it is possible to suppress the generation of the standby current caused by the bridge defect and the like, and to enable the application of the new redundancy scheme to improve the reliability of the semiconductor memory device.

The core isolation activation circuits and the switch circuits presented in the above-described embodiments of the present invention are merely examples and may be configured in other ways.

In addition, the present invention can be implemented not only for the above-described ground voltage line, but also for local connection control of other power lines used therein.

For example, in the case of carrying out the present invention with respect to the power supply voltage line, in FIG. 6B, the separation control may be performed by using a pio transistor whose gate is connected to [phi] F instead of the enMOS transistor 52.

Therefore, the present invention can be usefully used to solve the problem of circuit defects (consumption of quiescent current, etc.) due to in-process defects in high-density integrated circuits forming signal line arrays using global lines and local lines. Should be understood.

Claims (2)

A plurality of sub-memory arrays arranged in a matrix and having a plurality of word lines and a plurality of equalization circuits and sense amplifiers arranged in a row direction between the sub-memory arrays, and a column direction between the sub-memory arrays. A semiconductor memory device having a plurality of word line driving blocks arranged in a plurality of sub word line drivers, wherein the plurality of global word lines and the sub memory arrays extend in a column direction between the sub memory arrays. Row or column direction between the plurality of global equalization lines extending in the column direction between the sub memory arrays and the plurality of global sense amplifier control lines extending in the column or row direction between the sub memory arrays. Plural globals Local lines connected to at least one of ground voltage lines, the equalization circuits, sense amplifiers, the subword line drivers, and the global ground voltage lines, and between the global lines and the local lines. And a core isolation control circuit for controlling electrical connection of the semiconductor memory device. 2. The core separation activating circuit according to claim 1, wherein the core separation control circuit operates in accordance with a signal allowing input of an address and generates a separation signal according to a connection state of a fuse responding to address information related to the defect. And means for interrupting electrical connection between the global lines and the local lines in response to a signal.