JPH07230265A - Device and method for driving liquid crystal and device for displaying it - Google Patents

Abstract

PURPOSE:To realize a liquid crystal driving device improving supply method of operation power source and incorporating a display data storage means with a lower power consumption and a larger capacity. CONSTITUTION:A signal electrode drive circuit (X driver) consists of a low voltage amplitude operation part 101 operating by receiving a first source voltage group and a high voltage amplitude operation part 102 operating by receiving a second source voltage group, and is constituted so that a frame memory 109 storing the display data is arranged on the high voltage amplitude operation part 102, and the operation power source is supplied from the second source voltage group. Further, the power source of the frame memory 109 may be supplied through a constant voltage circuit making the second source voltage a constant voltage, and may be supplied switching the first, the second source voltages according to the condition of the second source voltage by a power source monitor means monitoring the second source voltage group. This is particularly effective constitution in a plural lines simultaneous selection drive method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a RAM-embedded signal electrode driver used in a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, in a simple matrix type liquid crystal display device, display data is sent from a MPU (microprocessor unit) side to a signal electrode drive circuit (X driver) in an LCD module (liquid crystal panel, LCD panel). As a transfer method, a method using a RAM built-in X driver is known. In this method, the display data is sequentially transferred to the X driver by the shift clock, and the display data is once written in the built-in RAM. The display operation is performed by simultaneously reading the display data for one scanning line from the built-in RAM. According to this method, the display data is stored in the built-in RAM of the X driver. Therefore, when there is no display change, the display refresh can be performed by reading the display data from the built-in RAM without newly transferring the display data to the X driver.
As a result, when there is no display change, it is not necessary to transfer the display data by the shift clock, and low power consumption operation is possible.

FIG. 14 shows an example of the configuration of a conventional RAM built-in X driver. This X driver includes a row address counter decoder 904, a timing circuit 906, a data input control circuit 908, a chip enable control circuit 910, a bidirectional shift register 912, a data register 914, a frame memory (built-in RAM) 916, a latch circuit 918, a level shifter. 920, voltage selector 9
Including 22. The row address counter decoder 904 is
It has a function of sequentially selecting one line of the frame memory 916. Initialization of the selected address is performed based on the YD signal, and the selected address is incremented when the data writing to the frame memory 916 is completed after the falling edge of the LP signal. The timing circuit 906 is
It has functions such as controlling the row address counter decoder 904 based on the shift clock XSCL. The data input control circuit 908 controls the display data D ₀ from the MPU.
Up to D _n are fetched and the fetched data is transferred to the data register 914. The chip enable control circuit 910 performs automatic power saving for each chip when a plurality of chips are used, based on the enable signals CEI and CE0. The bidirectional shift register 912 outputs a control signal for writing the display data D _{0 to} D _n to the data register 914, to the data register 914. The order of the display data written in the data register 914 is inverted by the SHL signal. Data register 914
Is a register that controls writing of display data to the frame memory 916.
Data writing to 6 is performed at the falling edge of the LP signal.

The latch circuit 918 reads the display data of the row address selected by the row address counter decoder 904 from the frame memory 916 at the falling edge of the LP signal and outputs it to the level shifter 920. The level shifter 920 is a circuit for converting the voltage level of the signal from the logic system power supply level (V _DD , V _SS ) to the liquid crystal drive system power supply level (V _{0 to} V ₅ ). The voltage selector 922 has a function of selecting a liquid crystal drive voltage for driving the signal electrodes X _{1 to} X _m from V _{0 to} V ₅ . Which of V _{0 to} V ₅ is selected is determined by the display data and the FR signal which is a signal for alternating the liquid crystal drive.

In the above conventional example, as shown in FIG. 14, a row address counter decoder 904, a timing circuit 906, a data input control circuit 908, a chip enable control circuit 910, and a bidirectional shift register 9 are provided.
12, data register 914, frame memory (built-in R
AM) 916 and the latch circuit 918 are arranged in the low voltage amplitude operating portion 901. On the other hand, the level shifter 920,
The voltage selector 922 is arranged in the high voltage amplitude operating portion 902. In the low voltage amplitude operation portion 901, the voltage difference between the power supply voltage on the high potential side and the power supply voltage on the low potential side is small,
In the high voltage amplitude operation portion 902, the voltage difference between the power supply voltage on the high potential side and the power supply voltage on the low potential side is large.

[0006]

In the above-mentioned conventional example, the RAM (frame memory 916) incorporated in the X driver is also increasing in capacity along with the increase in size of the LCD panel, which directly leads to an increase in the chip area. . Built-in RAM to prevent the increase of chip area
In addition, it is conceivable to adopt a high registration type RAM instead of the full CMOS type RAM. Full CMO
The S type RAM cell includes a P-channel transistor and an N-channel transistor, whereas the high registration type RAM cell includes a high resistance element and an N-channel transistor. And high register type RAM
In this case, since the P-channel transistor does not exist in the RAM cell, it is not necessary to separate the P-channel transistor and the N-channel transistor from each other, so that the area can be greatly reduced. Therefore, in order to reduce the chip area and reduce the cost of the device, it is desirable to use a high-registration type RAM as the built-in RAM.

On the other hand, since the liquid crystal driving device is used for a liquid crystal display device in a portable electronic device or the like, low power consumption is desired, and therefore, the power supply voltage used tends to be low. is there. Therefore, even in the X driver,
The reduction of the power supply voltage of the low voltage amplitude operation portion 901 is being realized. In order to completely reduce the voltage, it is necessary to reduce the power supply voltage of the built-in RAM (frame memory 916) arranged in the low voltage amplitude operation portion 901 of the X driver.

As described above, in order to reduce the chip area, it is necessary to use a high-registration type RAM as the built-in RAM, while lowering the power supply voltage of the low-voltage amplitude operating portion 901 to reduce the device size. There is a problem that the power supply voltage of the built-in RAM must be lowered in order to reduce the power consumption.

However, in the high-registration type RAM cell, when the operating power supply voltage becomes lower than 3.0 V, defective write operation or defective read operation occurs,
If the voltage is lower than 1.5 V, there is a problem that retention failure occurs, which makes it impossible to retain data itself, and garbled data occurs. This problem will be described in detail below with reference to FIG.

FIG. 15 shows an example of the structure of a high registration type (high resistance load type) RAM cell. This RAM
The cell is an N-channel transistor 80 for driving.
1, 802 (T1, T2) and high resistance 805, 806
(R1, R2) are included. These T1, T2, R1,
R2 constitutes a data holding part. Also, this RA
The M cell also includes N channel transistors 803 and 804 (T3, T4) for the transmission gate. T
3 and T4 are turned on when the word line WL807 is "H", and transfer the potentials of the bit line BL808 and the bit line bar BL809 to the data holding portion composed of T1, T2, R1 and R2.

Next, the basic operation of this RAM cell will be described. When writing data, the transmission gates T3 and T4 are turned on, and BL and bar BL
The potential (inverted signal of BL) is transmitted to the data holding portion. If BL = “H” and bar BL = “L”, the potentials of M1 and M2 are “H” and “H”, respectively.
When the potential of M1 becomes "H", the transistor T2 is turned on and the potential of M2 becomes stable at "L".
Since the potential of M2 is "L", the transistor T1 is turned off, and the potential of M1 stabilizes at "H". After that, even if the transmission gates T3 and T4 are turned off, the potential of M1 is pulled up to the H level by the high resistance R1,
Since the potential of 2 is fixed to the L level by the transistor T2, the potentials of M1 and M2 are held. As a result, the data write operation is realized. Further, at the time of reading, transmission gates T3 and T4 are turned on, and the potentials of M1 and M2 are transmitted to BL and bar BL. Then, the data read operation is realized by detecting this potential with a sense amplifier or the like.

Next, the write operation failure will be described. At the time of writing, a write signal is transmitted via the transmission gates T3 and T4. At this time, there occurs a situation in which the voltage of the write signal is lowered by the threshold voltage V _th of the N-channel transistor of the transmission gate. If BL = “H”,
Considering the case of writing the bar BL = “L”, the potential of M1 becomes lower than the H level by the threshold voltage V _{th of} T3. At this time, if the potential of M1 is at a level at which the transistor T2 can be turned on, no problem will occur. However, as the operating power supply voltage drops, the potential of M1 also drops, and when the operating power supply voltage becomes equal to or lower than a predetermined voltage, T2 cannot be turned on due to the potential of M1. As a result, "L" is added to M2 by the BL side.
Even when writing, the potential of M2 is not stably set to "L", which causes a write operation failure.

Next, the read operation failure will be described. At the time of reading, transmission gates T3 and T4 are turned on after precharging BL and bar BL to "H" before reading. Here, it is assumed that M1 = "H" and M2 = "L". Then, the potential of M1 decreases by _{Vth of} T3, and
The potential of M2 is slightly increased by the bar BL. As a result, T2 that was in the ON state slightly shifts to the OFF state, and T1 that was in the OFF state slightly shifts to the ON state. When the operating power supply voltage drops, T2
Shifts further to the off state and T1 shifts to the larger on state, which causes a phenomenon that the on / off state is reversed, resulting in a read operation failure. When the operating power supply voltage is lowered as described above, the impedance balance between the loads R1 and R2 and the transistors T1 and T2 is disturbed, and the fluctuation of _Vth of the transistor greatly affects the stable operation. Therefore, if the operating power supply voltage is lowered, it becomes difficult to secure a wide operating margin.

As described above, in the conventional example, the problem of miniaturization of the chip area by adopting the high-registration type RAM and the low power consumption of the device by lowering the voltage of the low voltage amplitude operation portion 901 are achieved. There was a problem that it could not be compatible with the task of becoming a product.

This problem also occurs in a method called a multiple line simultaneous selection drive method. For a method of simultaneously selecting a plurality of lines, see Japanese Patent Application No. 5-51.
5531, Japanese Patent Application No. 5-152533.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to improve the method of supplying power to the display data storage means incorporated therein to improve the power consumption. It is intended to ensure normal operation of the display data storage means while adopting a display data storage means that can be scaled up, and to further reduce the voltage of the low voltage amplitude operation portion.

Another object of the present invention is to incorporate a liquid crystal driving device adopting a multiple line simultaneous selection driving method by utilizing the fact that the liquid crystal driving power supply voltage is lowered in the driving method. It is to improve the method of supplying power to the display data storage means.

Another object of the present invention is to stabilize the power supply voltage supplied to the display data storage means when improving the method of supplying power to the display data storage means incorporated therein. .

Another object of the present invention is to monitor an abnormal situation of the supplied power supply voltage and improve the power supply method to the built-in display data storage means in the case where the abnormal situation occurs. Another object is to effectively prevent the display data stored in the display data storage means from being destroyed.

[0020]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a low voltage amplitude operation section which has at least a control logic section and is operated by being supplied with a first power supply voltage group, and a liquid crystal. A high voltage amplitude operating part which is operated by being supplied with a second power supply voltage group used for driving liquid crystal elements arranged in a matrix on a panel, the second liquid crystal driving device comprising: The voltage difference between at least one pair of high-potential-side power source voltage and low-potential-side power source voltage included in the power-source voltage group is the difference between the high-potential-side power source voltage and the low-potential-side power source voltage included in the first power-source voltage group. Display data storage means for storing display data for displaying an image on the liquid crystal panel, the display data storage means being set to be larger than the voltage difference;
Power supply voltage group, or a third power supply voltage group obtained by converting the second power supply voltage group by the power supply conversion means, as means for supplying the display data storage means with operating power. Characterize.

According to the present invention, the display data storage means is arranged in the high voltage amplitude operating portion, and its operating power supply is supplied from the second or third power supply voltage group. Therefore, even if it is a display data storage means that causes a write / read operation failure, etc. when it is arranged in the low voltage amplitude operation portion, it can be ensured in normal operation by arranging it in the high voltage amplitude operation portion. You can On the other hand, regarding the logic control section that is placed in the low voltage amplitude operation section and operates at high speed,
It is possible to reduce the voltage regardless of the operating voltage of the display data storage means.

In the present invention, the display data storage means includes a plurality of RAM cells that can be written and read at any time, and the RAM cells include at least one pair of transistors for holding data and the pair of transistors. And a high resistance element for supplying an operating current to the transistor.

According to the present invention, the display data storage means is composed of a high registration type RAM cell. And
Even if a high registration type RAM cell is adopted,
Since these RAM cells are arranged in the high voltage amplitude operation portion, the occurrence of write / read operation failure is prevented. When the high-registration type RAM cell is adopted, the chip area can be significantly reduced as compared with the case where the conventional full CMOS type RAM cell is adopted.

Further, according to the present invention, the liquid crystal panel includes a plurality of scanning electrodes and a plurality of signal electrodes intersecting with the scanning electrodes, and means for latching display data read from the display data storage means, and the latched display data. Level shift means for performing voltage level conversion, and voltage selection means for selecting a liquid crystal drive voltage from the second power supply voltage group based on the voltage level converted display data and outputting the liquid crystal drive voltage to the signal electrode. And the latch means, the level shift means, and the voltage select means are arranged in the high voltage amplitude operation portion.

According to the present invention, it is possible to apply the principle of the present invention to a liquid crystal driving device that employs the voltage averaging method. As a result, it is possible to normally operate the display data storage means that causes a write / read operation failure when placed in the low voltage amplitude operation part, and further lower the voltage of the low voltage amplitude operation part. Becomes When the principle of the present invention is applied to the voltage averaging method, it is desirable to supply the display data storage means or the like with a voltage obtained by stepping down the second power supply voltage. It is desirable to perform conversion for boosting the stepped-down voltage to the level of the second power supply voltage.

Further, according to the present invention, the liquid crystal panel includes a plurality of scanning electrodes and a plurality of signal electrodes intersecting the scanning electrodes, and the display data read from the display data storage means and the plurality of scanning electrodes are simultaneously selected. Of the driving voltage to the signal electrode from the voltage state of the driving signal, means for latching the driving voltage information output from the driving signal determining means, and the driving voltage information based on the latched driving voltage information. A liquid crystal driving voltage from a second power supply voltage group, and a voltage selecting means for outputting the liquid crystal driving voltage to the signal electrode, wherein the driving signal determining means, the latching means, and the voltage selecting means include the high voltage. It is characterized in that it is arranged in the amplitude operation part.

According to the present invention, it is possible to apply the principle of the present invention to a liquid crystal driving device that employs a multiple line simultaneous selection driving method. Then, according to the multiple line simultaneous selection driving method, the second power supply voltage can be made lower than that in the voltage averaging method. Therefore, it is possible to supply an appropriate power supply voltage to the display data storage means without lowering the second power supply voltage. Further, it is not necessary to manufacture the display data storage means, the drive signal determination means, the latch means, and the voltage selection means in a high withstand voltage process.

In the present invention, the power supply conversion means includes constant voltage generation means for obtaining the third power supply voltage group of constant voltage from the second power supply voltage group, and the display data storage means includes: It is characterized in that the third power supply voltage group, which has been converted into a constant voltage by the constant voltage generation means, is supplied to operate.

According to the present invention, a constant power supply voltage can be supplied to the display data storage means. As a result, it is possible to prevent fluctuations in the voltage level due to the switch operation of the voltage selection means, for example, from affecting the stable operation of the display data storage means.

Further, the present invention includes a power supply monitoring means for monitoring the voltage state of the second power supply voltage group or the third power supply voltage group, and the power supply monitoring means supplies the display data storage means. It is characterized by including means for switching the power supply voltage from the voltage of the second power supply voltage group or the voltage of the third power supply voltage group to the voltage of the first power supply voltage group.

According to the present invention, for example, when the second power source is turned off, this off state is detected by the power source monitoring means, and the power source voltage supplied to the display data storage means is the first power source. Switched to voltage. As a result, although the data writing / reading operation to / from the display data storage means is disabled, the data can be normally held.

Further, the present invention is characterized in that the power supply monitoring means includes means for externally monitoring the state of the second power supply voltage group.

According to the present invention, an external device such as an MPU can monitor the state of the second power supply voltage group.

According to the present invention, the power supply monitoring means is provided with a voltage difference between a pair of high-potential-side power supply voltage and low-potential-side power supply voltage in the second power supply voltage group or the third power supply voltage group. Means for dividing the divided voltage to generate a divided voltage, and means for comparing the divided voltage with a reference voltage generated from the first power supply voltage group,
On / off operation is performed based on the comparison result from the comparison means, and the power supply voltage to be supplied to the display data storage means is changed from the voltage of the second power supply voltage group or the third power supply voltage group to the first power supply. And a switching means for switching to a voltage of the voltage group.

According to the present invention, since the reference voltage is generated from the first power supply voltage group, it has a constant value regardless of the state of the second power supply. On the other hand, the divided voltage from the divided voltage generating means changes, for example, when the second power supply is turned off. Therefore, the comparison means can monitor the state of the second power supply by comparing the reference voltage with the divided voltage.
Then, the power supply voltage supplied to the display data storage means can be switched to the first power supply voltage by turning on / off the switching means according to the output result of the comparison means.

The liquid crystal display device of the present invention is characterized by including at least the above liquid crystal drive device and a liquid crystal panel in which liquid crystal elements are arranged in a matrix.

According to the present invention, since the chip area of the liquid crystal driving device can be reduced and the power consumption can be suppressed low, the cost and power consumption of the liquid crystal display device including the liquid crystal driving device can be suppressed low. Becomes

[0038]

Embodiments of the present invention will now be described with reference to the drawings.

(First Embodiment) 1. Configuration and Operation FIG. 1 is a block diagram showing the overall configuration of a signal electrode drive circuit (X driver) according to the first embodiment of the present invention. The X driver shown in FIG. 1 is divided into a low voltage amplitude operating part 101 which operates by a first power supply voltage group and a high voltage amplitude operating part 102 which operates by a second power supply voltage group. Then, a voltage difference between at least one pair of high-potential-side power supply voltage and low-potential-side power supply voltage included in the second power supply voltage group, for example, a voltage difference between V ₂ and V _C is included in the first power supply voltage group. High-potential-side power supply voltage V _DD and low-potential-side power supply voltage V _SS
It is set larger than the voltage difference between and.

Now, the X driver shown in FIG. 1 has a chip enable control circuit 103 and a timing circuit 10.
4, data input control circuit 105, input register 106,
Write register 107, level shifter 108, frame memory (built-in RAM) 109, row address register 1
10, a drive signal determination circuit (MLS decoder) 111, a latch circuit 112, and a voltage selector 113. here,
The chip enable control circuit 103 performs automatic power saving for each chip when using a plurality of chips.
This is performed based on the enable signals CEI and CEO. The timing circuit 104 uses the shift clock XSC.
It forms a required timing signal based on L, YD signals, LP signals and the like. Data input control circuit 10
Reference numeral 5 is for fetching the display data D _{0 to} D _n transferred from the MPU to the X driver upon generation of the enable signal E, and outputting the fetched data to the input register 106. The input register 106 sequentially takes in display data at the falling edge of the shift clock XSCL and stores display data for one scanning line. The write register 107 collectively latches the display data for one scanning line from the input register 106 with a latch pulse, and outputs the display data for two scanning lines, for example, when the display data for two scanning lines is latched. The data is written in the memory cell in the frame memory 109 via the.

The level shifter 108 has a function of converting the level of a signal when the signal from the low voltage amplitude operating portion 101 is transmitted to the high voltage amplitude operating portion 102. The frame memory 109 includes memory cells arranged in a matrix and its peripheral circuits, and accumulates display data input from the write register 107. The row address register 110 is initialized by the signal scanning start signal YD and a field identification signal FIS which will be described later, and every time the write control signal WR or the read control signal RD is applied from the timing circuit 104, a line (word line) of the frame memory 109 is applied. ) Are sequentially selected. As a result, the display data for every two lines is output from the frame memory 109 to the drive signal determination circuit 111. The drive signal determination circuit (MLS decoder) 111 determines drive voltage information of the signal electrode from a combination of the FIS signal, the AC signal FR, and the display data (for two lines) from the frame memory 109. The latch circuit 112 collectively latches the drive voltage information from the drive signal determination circuit 111 at the falling edge of the LP signal. The voltage selector 113 selects a liquid crystal drive voltage from the second power supply voltage groups V ₂ , V _C , and −V ₂ based on the drive voltage information from the latch circuit 112, and selects the liquid crystal drive voltage from each of the signal electrodes X ₁ to X ₁ . It is applied to X _m .

The timing circuit 104 shown in FIG.
The latch pulse LP 'and the shift clock XSCL' output from are generated from the control signals LP and XSCL supplied to the X driver, respectively, but these signals are only when the display on the LCD panel is changed. Since it is an output signal, LP, XS
It is attached with'to distinguish it from CL.

Next, the method of supplying the power supply voltage in this embodiment will be described. In this embodiment, the first power supply voltage group is supplied to the low voltage amplitude operating portion 101 by the terminals V _DD and V _SS , and the terminals V ₂ and V _C are supplied to the high voltage amplitude operating portion 102. , -V ₂ supplies the second power supply voltage group. The relationship between the potentials of these power supplies is as shown in FIG. 2 with V _DD and V ₂ being a common potential. That is, V _DD = V ₂ = 0 V, V _SS = -2.7 V, V _C =-
4.0V, and has a -V ₂ = -8.0V. The supply of the power supply voltage to each block inside the X driver will be described again with reference to FIG. Low voltage amplitude operating part 101
Row address register 110, timing circuit 10
4, data input control circuit 105, write register 10
7, the power supply terminals V _DD and V _SS of each block of the input register 106 and the chip enable control circuit 103 are connected to the terminals V _DD and V _{SS to} which the first power supply voltage group is supplied. As a result, the V _DD terminal of each block has 0 V, V _SS
The terminal is supplied with -2.7V. As a result, each of these blocks operates at a power supply voltage with a voltage difference of 2.7V. Further, the power supply terminal V _2, V _C, -V ₂ voltage selector 113 of the high voltage amplitude operation section 102 has terminals V ₂ to the second power supply voltage group is supplied, V _C, -V ₂ is connected It Thus, the V ₂ terminal 0V, -4 to V _C terminal.
0V, the -V ₂ terminal -8.0V is supplied. Then, by selecting these voltages by the voltage selector 113, the outputs X _{1 to} X _m of the X driver are formed. The latch circuit 112, the drive signal determination circuit 111, the frame memory 109, and the level shifter 1 in the high voltage amplitude operation portion 102
The power supply terminals V _DD and V _SS of each block of 08 are connected to the terminals V ₂ and V _{C to} which the second power supply voltage group is supplied. As a result, 0 V is supplied to the V _DD terminal and -4.0 V is supplied to the V _SS terminal. As a result, each of these blocks has a voltage difference of 4.
It operates with a power supply voltage of 0V.

As described above, according to the X driver of this embodiment, the frame memory 109 is supplied with the power supply voltage having the voltage difference of 4.0 V by the _second power supply voltages V ₂ and V _C. It As a result, even if the frame memory 109 is composed of a high-registration type (high resistance load type) RAM (see FIG. 15), stable operation of the RAM is ensured. And
By configuring the frame memory 109 with a high registration type RAM, the chip area can be reduced. On the other hand, it is not necessary to dispose the frame memory 109 in the low voltage amplitude operation part 101 including the logic control part that operates at high speed. Therefore, the low voltage amplitude operating portion 101
A first power supply voltage group to be supplied to V _DD = 0V,
It is possible to reduce the voltage difference such that V _SS = −2.7V. As a result, the power supply voltage of the portion that operates with the high-speed clock (for example, m times as high as the high voltage amplitude operating portion) can be lowered, and thus the power consumption can be significantly reduced. Further, if such a reduction in voltage becomes possible, it becomes possible to manufacture the transistor that constitutes the low-voltage amplitude operation portion 101 by a fine process, and the chip area can be further reduced.

In the present embodiment, the frame memory 10
9 not only improve the method of supplying the power supply voltage to 9,
The arrangement position of the level shifter 108 is also improved. FIG. 3 shows an example of the configuration of the level shifter 108 that performs level conversion of a signal when the signal is transmitted from the low voltage amplitude operating portion 101 to the high voltage amplitude operating portion 102. The level shifter 108 includes an inverter 301 that inverts an input signal I, N-channel transistors 302 and 303 that are turned on / off by the input signal I, and P-channel transistors 304 and 305 that are turned on / off according to the potential state of the drain regions of these transistors. Contains. The power supplies V _DD and V _SS are supplied from the second power supply voltage group. Next, the operation of the level shifter 108 will be described. First, when the input signal I is "L", the voltage levels of the gate electrodes of the transistors 302 and 303 are "L" and "H", respectively. This turns off the transistor 302 and turns on the transistor 303.
Therefore, the voltage level of the gate electrode of the transistor 304 becomes "L", and the transistor 304 is turned on. On the other hand, the voltage level of the gate electrode of the transistor 305 is "
The output O and the bar O (inverted signal of O) become "L" and "H", respectively, and the input I is level-converted and transmitted to the output O. When the input I is “H”, the transistors 302 and 303, the transistor 30
The on / off relations of 4 and 305 are reversed.

Next, the level shifter 10 in this embodiment.
The insertion position of 8 will be described. High voltage amplitude operation part 1
The latch circuit 112 and the drive signal determination circuit 111 arranged in 02 can be arranged in the low voltage amplitude operation portion 101 as shown in FIG. 4 and operated by the first power supply voltage group. However, when these two circuits are configured to operate at a low voltage amplitude, as shown in FIG.
Although it is not necessary to convert the levels of the signals LP, FR and FIS, there is a drawback that a plurality of level shifters are required as follows. That is, in the case of FIG. 4, the level shifter 120 for level up is used for signal transmission from the write register 107 to the frame memory 109, and the level shifter 120 is level down for signal transmission from the frame memory 109 to the drive signal determination circuit 111. The level shifter 122 of (1) requires the level shifter 124 for level up for signal transmission from the latch circuit 112 to the voltage selector 113. Since the signals passing through the level shifters 120, 122, and 124 are required for the number of outputs (m) of the driver, the area occupied by the level shifters is greatly increased, and the chip area of the driver is increased. Therefore, in this embodiment, the level shifter 108 is arranged as shown in FIG. 1, the level conversion is performed only once, and the latch circuit 112 and the drive signal determination circuit 111 are operated at a high voltage. The high voltage amplitude operation part 102 does not have a part that operates with the high speed clock XSCL like the control logic part in the low voltage amplitude operation part 101. Therefore, even with such a configuration, this does not significantly affect the increase in power consumption of the entire X driver.

2. Multiple Lines Simultaneous Selection Driving Method The X driver of the present embodiment uses multiple lines simultaneous selection (Multip
le Lines Selection) The configuration is suitable for the driving method. The multiple line simultaneous selection drive method can realize the same on / off ratio as the conventional method of selecting and driving one line at a time, and can further suppress the drive voltage on the X driver side. For example, when the threshold V _{th of the} liquid crystal element is 2.1 V and the duty ratio is 1/240, the maximum drive voltage amplitude of the X driver is about 20 V in the conventional drive method. In the multiple line simultaneous selection drive method, 8.0 V (between V ₂ and -V ₂ ) is sufficient as shown in this embodiment. Therefore, it is not necessary to make the voltage selector 113 and the level shifter 124, which are high breakdown voltage parts, monolithic.
As a result, it becomes possible to use a process capable of manufacturing a highly integrated RAM, and a large capacity RAM can be built in the X driver. Further, in order to perform the multiple line simultaneous selection driving method, the power supply voltage of (the number of simultaneously selected lines) +1 is required to supply power to the voltage selector 113. In this embodiment, three power supply voltages V _2, V _c because it simultaneously selected number of lines and two lines, -V ₂ is required. Since the voltage difference between these power supply voltages is as low as 8.0 V at the maximum, it can be used as an operating power supply for the RAM without stepping down these power supply voltages. In this embodiment, a voltage difference of 4.0 V between V ₂ and V _C is used as the operating power supply for the RAM.

Next, a method of simultaneously selecting a plurality of lines will be described. The driving method based on the voltage averaging method is shown in FIG.
As shown in (D), the scan electrodes Y ₁ , Y _{2 to} Y _n are sequentially selected line by line to apply a scan voltage, and depending on whether each pixel on the selected scan electrode is on or off. The signal electrode waveforms corresponding to the signal electrode waveforms are set to the respective signal electrodes X ₁ , X _{2 to} X _m.
Apply to. However, this method has problems that the driving voltage is relatively high, the contrast is poor, and flicker is large when frame gradation is performed. Therefore, as a method for solving the above problem, a multiple line simultaneous selection driving method has been proposed.

FIGS. 6A to 6D show examples of applied voltage waveforms when the multiple line simultaneous selection driving method is used. FIGS. 6A to 6D show a case where three scanning electrodes are sequentially selected at a time. For example, when performing pixel display as shown in FIG. 7A, first, three scan electrodes Y ₁ , Y ₂ and Y ₃ are simultaneously selected and these scan electrodes Y ₁ , Y ₂ and Y are selected. ₃ in applying a scanning voltage as shown in FIG. 6 (a). Next, the scan electrodes Y ₄ , Y ₅ , and Y ₆ are selected, and the scan voltage shown in FIG. 6B is applied to those scan electrodes Y ₄ , Y ₅ , and Y ₆ . Then, such simultaneous selection is sequentially performed for all the scan electrodes Y ₁ , Y _{2 to} Y _n . In the next frame, the potential is reversed to drive the liquid crystal in an alternating current. In the multiple line simultaneous selection driving method, the selection period is evenly distributed in one frame in time while maintaining the normal orthogonality of the selection of the scanning electrodes, and at the same time, the scanning electrodes are selected in a specific number of sets (blocks). . Here, “regular” means that all the scanning voltages have the same effective voltage value (amplitude value) in each frame period. The term "orthogonal" means that the voltage amplitude applied to a certain scan electrode becomes 0 in frame cycle units when the voltage amplitudes applied to other arbitrary scan electrodes are summed up every one selection period. To do. In the simple matrix type LCD, this orthonormality is
This is a major premise for on / off control of each pixel independently. For example, in FIGS. 6A to 6D, when the V ₁ level at the time of selection is “1”, the −V ₁ level is “−1”, and the determinant for one frame is F = f _ij , The orthogonality between the first row (Y ₁ ) and the second row (Y ₂ ) is Σ _{(j = 1} to ₄₎ f _1j × f _2j = 1 + (− 1) + (− 1) + 1 =
It is verified as 0.

On the other hand, the voltage waveform on the signal side is determined by selecting one voltage level from (h + 1) discrete voltage levels according to the display data when, for example, h lines are simultaneously selected. To be In the voltage averaging method, FIG.
As shown in (D) to (D), the signal electrode (row) waveform has a one-to-one correspondence with the selection waveform of one row. On the other hand, h
In the case of the simultaneous selection, it is necessary to output an equivalent on / off voltage level for the row selection waveforms of h sets. This equivalent ON / OFF voltage level is obtained by setting the ON display data to “1” and the OFF display data to “0”, and the data pattern on the signal electrode side and the column pattern of the determinant F = f _ij (scan electrode selection pattern). ) And the number of disagreements with C. For example, considering a case where the column pattern is (1, 1, 1), the signal electrode side data pattern and the X driver output voltage are as shown in FIG. 7B. Therefore, if the column pattern is determined, the output voltage of the X driver is determined by directly decoding the output voltage of the X driver from the number of mismatches or the signal electrode data pattern. That is, the drive signal determination circuit 111 obtains drive voltage information based on the signal electrode data patterns for three rows from the frame memory 109, the FR signal, and the FIS signal, and outputs the X driver based on this drive voltage information. Voltage is required. A specific signal electrode voltage waveform is as shown in FIG. Figure 7
The display of the intersection pixels of the signal electrode X ₁ and the scan electrodes Y ₁ , Y ₂ , and Y ₃ in (A) is 1 (on), 1 (on), 0 in order.
At (OFF), the voltage values of the scan electrodes in the first Δt corresponding thereto are 1 (V ₁ ), 1 (V ₁ ), 0 (−V ₁ ) in that order. Therefore, since the number of mismatches is 0, the output voltage in the first Δt of the signal electrode X ₁ is −V ₃ from FIG. 7B. Thereafter, the output voltage waveform of the signal electrode is similarly determined.

The present applicant describes in Japanese Patent Application No. 5-515531 a uniform distribution type multiple line simultaneous selection drive method which is an improvement of the multiple line simultaneous selection drive method. In this uniform dispersion type multiple line simultaneous selection drive method, a plurality of scan electrodes are sequentially selected at the same time, and a voltage is applied by dividing the selection period into a plurality of times within one frame. That is, once in one frame (collectively h
Instead of selecting (a period of Δt), the voltage is applied by dividing the selected period into a plurality of times (dispersed) in one frame. As a result, the voltage is applied to the pixel a plurality of times during one frame, so that the brightness can be maintained and the contrast can be increased. In this case, the voltage may be applied by dividing each of the four column patterns into four times,
For example, the voltage may be applied to each two times twice.

In the multiple line simultaneous selection method described above, three scanning electrodes are simultaneously selected, so that the second power supply voltage group has four levels of V ₃ , V ₂ , -V ₂ and -V _3. Become. When V _DD = V ₃ = 0V, the power supply terminals V _DD and V _SS of the frame memory 109 and the like have V ₃ and V _{2 respectively.}
Alternatively, either V ₃ , -V ₂ or V ₃ , -V ₃ pair is supplied. On the other hand, when V _SS = −V ₃ = 0V, the power supply terminals V _DD and V _SS of the frame memory 109 and the like have −V ₂ , −V ₃ or V ₂ , −V ₃ or V ₃ , −.
Either pair of V ₃ is supplied. In any case, at least one of the voltage differences between these pairs (for example, the voltage difference between V ₃ and −V ₃ ) is more than the voltage difference between V _DD and V _SS supplied to the low voltage amplitude operating portion 101. Since the size of the frame memory 109 is large, the normal operation of the frame memory 109 is guaranteed. The above is the same when the number of simultaneously selected lines is four or more and the second power supply voltage group is five or more levels.

(Second Embodiment) In the first embodiment shown in FIG. 1, the latch circuit 1 of the high voltage amplitude operating portion 102 is used.
12, drive signal determination circuit 111, frame memory 10
9. The second power supply voltage groups V ₂ and V _C were directly supplied to the level shifter 108. However, when V ₂ and V _C are directly supplied as described above, the fluctuation of the voltage level due to the switching of the voltage selector 113 affects the stable operation of these circuits, particularly the frame memory 109. In the second embodiment, this point is taken into consideration, and the second power supply voltage group is supplied not through these circuits directly but through a constant voltage circuit. FIG. 8 shows a block diagram of the overall configuration of the X driver according to the second embodiment. In FIG. 8, those having the same reference numerals as the constituent blocks shown in FIG. 1 are the same as those described in the first embodiment. Here, a constant voltage circuit 401 is newly added. This constant voltage circuit 401, the second power supply voltage group V _2, V _C, -V
₂ is input and a constant voltage V _DD2 = 0V, V _SS2
= -4.0 V is generated and supplied to the latch circuit 112, the drive signal determination circuit 111, the frame memory 109, and the level shifter 108. This guarantees stable operation of these circuits.

FIG. 9 shows an example of the configuration of the constant voltage circuit 401. This constant voltage circuit 401 includes P-channel transistors 501, 502 (P1, P2), N-channel transistors 503, 504, 505 (N1, N2, N3), resistors 506, 507 (R, R) having the same resistance value, It includes an operational amplifier 508 (OP). Next, the operation will be described. P
In the reference voltage generating section composed of 1, P2, N1 and N2, _{Vth of} P1 and P2 are equal, and P1 and P2 are equal.
2, N1 and N2 have the same transistor capability. With this configuration, a reference voltage of (V _th2 −V _th1 ) is generated at the point A. Here, V _th1 and V _th2 are threshold voltages of N1 and N2, respectively. Now, suppose V _th1 = 2.
5V, when the V _th2 = 0.5V, the voltage of the point A is always constant irrespective of the variation of V _c, a -2.0 V. The point A is connected to the inverting input terminal of the operational amplifier 508. At this time, when the transistor N3 is turned on and a current flows through the resistor R, the voltage at the point C is fixed to −2.0 V by the imaginary short circuit function of the operational amplifier 508. The currents flowing through the resistors 506 and 507 are equal,
The resistance value of 07 is also the same. Therefore, the resistors 506, 50
The voltage drop at point 7 is equal, and the voltage at point B is -4.
It becomes 0V. This voltage is always constant constant voltage regardless of variations of -V _2. Then, this constant voltage is supplied to the frame memory 109 and the like as V _SS2 . Regarding V _DD2 , V ₂ = 0V which is the reference voltage is supplied as it is. As described above, stable operation of the frame memory 109 and the like is guaranteed.

(Third Embodiment) In the liquid crystal display system, the liquid crystal driving power supply may be turned off in order to reduce power consumption. For example, in a mode called display off, all liquid crystal power supply voltages are fixed to the same voltage. When the liquid crystal driving power supply is turned off, in the X driver of the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 8, the second power supply supplied to the high voltage amplitude operating portion 102 is turned off. It will be. Then, the display data stored in the frame memory 109 is cleared and may be lost.

The third embodiment takes this point into consideration. The voltage state (off state) of the second power supply voltage group is monitored, and when the second power supply is turned off, the first power supply is turned on. Is supplied to the frame memory to hold display data. FIG. 10 shows a block diagram of the overall configuration of the X driver according to the third embodiment. In FIG. 10, the components having the same numbers as the constituent blocks shown in FIGS. 1 and 8 are the same as those described in the first and second embodiments. Here, a power supply monitoring circuit 601 is newly added as compared with the second embodiment. The power supply monitoring circuit 601 includes a high voltage amplitude operation part 1
02, frame memory 109, drive signal determination circuit 1
11, V _DD2 and V _SS2 supplied to the latch circuit 112
Monitor the voltage difference between. Then, the external MPU or the like is notified via the terminal MONI whether the second power source is in the ON state or the OFF state. Therefore, the external MPU or the like can judge whether or not the display data can be transferred by monitoring the MONI terminal when sending the display data to the X driver. That is, when the second power supply is turned off, data cannot be written in the frame memory 109. Therefore, the external M
To prevent the PU or the like from writing useless data in the frame memory 109, or in order not to make a mistaken judgment that the data has been actually written, the ON / OFF state of the power supply is controlled by an external device using the MONI terminal. Notify the MPU etc.

Further, the power supply monitoring circuit 601 normally operates the second power supply voltage group V _DD2 when the second power supply is in the ON state.
V _SS2 is supplied to the frame memory 109, and when the second power supply is turned off, the first power supply voltage groups V _DD and V _SS are supplied to the frame memory 109. As a result, the display data in the frame memory 109 is held. This is because in the high-registration type RAM, the first power supply voltage (voltage difference 2.7
In V), the writing operation and the reading operation cannot be performed, but the data holding operation is possible.

FIG. 11 shows an example of the configuration of the power supply monitoring circuit 401. The power supply monitoring circuit 401 includes P-channel transistors 701 and 702 (P1 and P2) and N-channel transistors 703, 704, and 708 (N1,
N2, N3), and a resistance 705 having a resistance value ratio of 5: 3,
706 (5R, 3R), comparator 707 (COM
P) is included. Next, the operation of the power supply monitoring circuit 401 will be described using the voltage waveform diagram shown in FIG. P1, P
The portion constituted by 2, N1 and N2 is the reference voltage generating portion, and the operation is as already described in the explanation of the constant voltage circuit.
This reference voltage generator generates V _A = −2.0 V, and this V _A is input to the inverting input terminal of the comparator 707. On the other hand, V is applied to the non-inverting input terminal of the comparator 707.
_B is input. Here, since V ₂ = V _DD = 0V,
When the second power source is in the ON state, a voltage obtained by dividing the voltage difference of 4.0 V between V _DD and V _SS2 by the resistors 5R and 3R is V _B =-
It becomes 2.5V. Therefore, as shown in FIG. 12, V _A >
The output MONI of the comparator 707 is -2.7 from V _B.
The voltage becomes V and the transistor N3 is turned off. And N3
The terminal V _OUT connected to is connected to V _SS2 ,
-4.0V is supplied to _SS2 . Therefore, when N3 is off, -4.0 V is output to V _OUT . As a result, the power supply terminals V _DD and V _SS of the frame memory 109
0V and -4.0V are input to the frame memory 10
9 normal read / write operations are guaranteed.

On the other hand, when the second power source is in the off state, the following occurs. That is, the constant voltage circuit 401 shown in FIG.
As can be understood by looking at the configuration of V _SS2 ,
6, 507 and V _DD (identical to V ₂ ).
Therefore, the output V _OUT of the power supply monitoring circuit 601 is also the resistor 50.
Connected to V _DD via 6, 507. However, since V _B = 0V is input to the non-inverting input of the comparator 707, the output MONI of the comparator 707 becomes 0V and the transistor N3 turns on. As a result, V _OUT is connected to V _SS = -2.7 V, and as shown in FIG.
-2.7V is output to _OUT . As a result, 0V is applied to the power supply terminals V _DD and V _SS of the frame memory 109, -2.
7V is input. Therefore, the frame memory 109 is
Although writing / reading operations cannot be performed, data holding operations are possible and display data can be backed up.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the gist of the present invention.

For example, in the above-mentioned first to third embodiments, the explanation has been given by taking the X driver adopting the multiple line simultaneous selection driving method as an example, but the present invention is not limited to this, and the voltage averaging method is used. It can also be applied to the X driver. FIG. 13 shows an example of the configuration in this case. The following points are different from FIG. 14. First, in the high voltage amplitude operating portion 902,
In addition to the level shifter 921 and the voltage selector 922, a frame memory 916, a latch circuit 918, a level shifter 9
30 is arranged, and a row address counter decoder 90
4, the signal from the data register 914 is the level shifter 9
The level is converted by 30 and input to the frame memory 916. Further, a constant voltage circuit 932 is provided, and a second high-voltage power supply voltage group R is formed by a highly integrated process.
It is stepped down to voltages V _DD3 and V _SS3 at which the AM can operate and supplied to the frame memory 916 and the like. Also, the latch circuit 9
18 and the voltage selector 922 between the latch circuit 91.
A level shifter 921 for boosting the output signal of No. 8 to the level of the second power supply voltage group V0 to V5 is provided. In this case, the voltage difference between the power supply voltages V _DD3 and V _SS3 supplied to the frame memory 916 is smaller than the voltage difference between V ₀ and V ₅ , for example, and V _DD supplied to the low voltage amplitude operating portion 901 is: It is set to be larger than the voltage difference between V _SS . By setting in this way, the frame memory 916
Can be constituted by a high-registration type RAM cell, and it is not necessary to manufacture the frame memory 916 and the latch circuit 918 by a high withstand voltage process. As a result, the chip area can be reduced and the power consumption of the device can be reduced. However, the configuration of the present invention using the voltage averaging method is not limited to the configuration shown in FIG. Furthermore,
The present invention can be applied not only to a simple matrix type liquid crystal display device but also to other types of liquid crystal display devices.

Further, in this embodiment, a high registration type RA is used.
Although the example using M is shown, the present invention is not limited to this. For example, a TFT (thin film transistor) that operates at a lower voltage than a high registration type RAM
A type of RAM may be used. In this case, the TFT
It suffices that the lower limit value of the power supply voltage difference that guarantees the normal operation of the RAM configured in (3) exceeds the voltage difference of the first power supply voltage group supplied to the low voltage amplitude operating portion. Further, in addition to this, the present invention provides an S memory as a memory constituting the frame memory.
A memory such as RAM, DRAM, or E ² PROM can also be adopted. Further, a configuration in which a depletion type transistor is used instead of the high resistance element is also conceivable.

[0063]

According to the present invention, it is possible to normally operate the display data storage means which is defective in reading and writing in the low voltage amplitude operation, and to lower the operating voltage of the low voltage amplitude operating portion. As a result, the display data storage means can be downsized and the power consumption can be reduced. As a result, it is possible to reduce the cost of the device and to provide the optimal liquid crystal drive device for the liquid crystal display device adopted in the portable electronic device.

Further, according to the present invention, the conventional full CMO is used.
The chip area can be significantly reduced as compared with the case where the S type RAM cell is adopted.

Further, according to the present invention, in the liquid crystal driving device adopting the voltage averaging method, the display data storage means can be downsized and the power consumption can be reduced.

Further, according to the present invention, in the liquid crystal drive device adopting the plural line simultaneous selection drive method, the display data storage means can be downsized and the power consumption can be reduced. Further, since it is not necessary to manufacture the display data storage means, the drive signal determination means, the latch means, and the voltage selection means in a high breakdown voltage process, the chip area can be further reduced.

Further, according to the present invention, the stable operation of the display data storage means can be guaranteed, and the display data can be prevented from being lost or being erroneously converted into erroneous data.

Further, according to the present invention, it becomes possible to hold the data normally even when the second power source is turned off, for example, by turning off the display.
The device can have a function of backing up display data.

Further, according to the present invention, an external MPU
It is possible to prevent a situation in which such a device writes useless data in the display data storage means or erroneously determines that data has been written even though no data is actually written.

Further, according to the present invention, the state of the second power source is monitored, and the first power source voltage is surely supplied to the display data storage means when the second power source or the like is turned off. Is possible.

Further, according to the present invention, the cost and power consumption of the liquid crystal display device can be kept low, and the liquid crystal display device suitable for portable electronic equipment can be provided.

[0072]

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a signal electrode drive circuit (X driver) according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a potential relationship of a second power supply voltage group.

FIG. 3 is a diagram showing an example of the configuration of a level shifter.

FIG. 4 is a block diagram showing an example of a configuration of a signal electrode drive circuit when a drive signal determination circuit and a latch circuit are arranged in a low voltage amplitude operation portion in the first embodiment.

5A to 5D are waveform diagrams of voltages applied to scan electrodes, signal electrodes, and liquid crystal elements when a voltage averaging method is used.

FIGS. 6A to 6D are waveform diagrams of voltages applied to scan electrodes, signal electrodes, and liquid crystal elements in the case of using a multiple line simultaneous selection driving method.

7A is a diagram showing an example of an on / off state of a pixel, and FIG. 7B is a diagram showing the relationship between the number of mismatches, the signal electrode data pattern, the number of data patterns, and the X driver output voltage. It is a figure showing.

FIG. 8 is a block diagram showing an overall configuration of a signal electrode drive circuit according to a second embodiment of the present invention.

FIG. 9 is a diagram showing an example of a configuration of a constant voltage circuit.

FIG. 10 is a block diagram showing an overall configuration of a signal electrode drive circuit according to a third embodiment of the present invention.

FIG. 11 is a diagram showing an example of a configuration of a power supply monitoring circuit.

FIG. 12 is a waveform diagram for explaining the operation of the power supply monitoring circuit.

FIG. 13 is a block diagram showing an example of a configuration of the present invention when a voltage averaging method is used.

FIG. 14 is a block diagram showing an overall configuration of a conventional signal electrode drive circuit.

FIG. 15 is a diagram showing an example of a configuration of a high registration type (high resistance load type) RAM.

[Explanation of symbols]

 101 Low Voltage Amplitude Operating Part 102 High Voltage Amplitude Operating Part 103 Chip Enable Control Circuit 104 Timing Circuit 105 Data Input Control Circuit 106 Input Register 107 Write Register 108 Level Shifter 109 Frame Memory 110 Row Address Register 111 Drive Signal Determining Circuit 112 Latch Circuit 113 Voltage Selector 301 Inverter 302 N-channel transistor 303 N-channel transistor 304 P-channel transistor 305 P-channel transistor 401 Constant voltage circuit 501 P-channel transistor 502 P-channel transistor 503 N-channel transistor 504 N-channel transistor 505 N-channel transistor 506 Resistor 507 Resistor 508 Operational amplifier 601Power supply monitoring circuit 701 P-channel transistor 702 P-channel transistor 703 N-channel transistor 704 N-channel transistor 705 Resistor 706 Resistor 707 Comparator 708 N-channel transistor 801 N-channel transistor 802 N-channel transistor 803 N-channel transistor 804 N-channel transistor 805 Resistor 806 Resistor 807 Word line 808 Bit line 809 Bit line bar 901 Low voltage amplitude operation part 902 High voltage amplitude operation part 904 Row address counter decoder 906 Timing circuit 908 Data input control circuit 910 Chip enable control circuit 912 Bidirectional shift register 914 Data register 916 Frame memory 9 8 latch circuit 921 level shifter 922 voltage selector 930 level shifter 932 voltage regulator

Claims (10)

[Claims] 1. A low-voltage-amplitude operating part which has at least a control logic part and which is operated by being supplied with a first power supply voltage group, and which is used for driving liquid crystal elements arranged in a matrix on a liquid crystal panel. A liquid crystal driving device including a high voltage amplitude operating portion which is supplied with a second power supply voltage group and operates, wherein at least one pair of high-potential-side power supply voltage and low potential included in the second power supply voltage group. The voltage difference with the side power supply voltage is set to be larger than the voltage difference between the high-potential-side power supply voltage and the low-potential-side power supply voltage included in the first power supply voltage group, and is for displaying an image on the liquid crystal panel. The display data storage means for storing display data, the second power supply voltage group, or the third power supply voltage group obtained by converting the second power supply voltage group by the power supply conversion means is used as the display data. Memorizer And a means for supplying it as an operating power source for the stage. 2. The display data storage means according to claim 1, wherein the display data storage means includes a plurality of RAM cells that can be written and read at any time, and the RAM cells include at least one pair of transistors for holding data, and the one pair of transistors. A liquid crystal driving device comprising: a high resistance element connected to each of the transistors to supply an operating current to the transistors. 3. The liquid crystal panel according to claim 1, wherein the liquid crystal panel includes a plurality of scanning electrodes and a plurality of signal electrodes intersecting the scanning electrodes, and means for latching display data read from the display data storage means. A level shift means for converting the voltage level of the latched display data, and a liquid crystal drive voltage from the second power supply voltage group based on the voltage level converted display data, and the liquid crystal drive voltage is set to the signal electrode. And a voltage selecting means for outputting to the liquid crystal driving device, wherein the latching means, the level shifting means, and the voltage selecting means are arranged in the high voltage amplitude operating portion. 4. The liquid crystal panel according to claim 1, wherein the liquid crystal panel includes a plurality of scanning electrodes and a plurality of signal electrodes intersecting with the scanning electrodes, and a plurality of display data read from the display data storage means are simultaneously displayed. Drive signal determination means for determining information on the drive voltage to the signal electrode from the voltage state of the selected scan electrode, means for latching drive voltage information output from the drive signal determination means, and latched drive Voltage selection means for selecting a liquid crystal drive voltage from the second power supply voltage group based on voltage information and outputting the liquid crystal drive voltage to the signal electrode, the drive signal determination means, the latch means, the voltage A liquid crystal drive device, wherein a selecting means is arranged in the high voltage amplitude operating portion. 5. The power supply conversion means according to claim 1, further comprising a constant voltage generation means for obtaining the third power supply voltage group of constant voltage from the second power supply voltage group,
A liquid crystal drive device, wherein the display data storage means is operated by being supplied with a third power supply voltage group which is made constant by the constant voltage generation means. 6. The power supply monitoring unit according to claim 1, further comprising a power supply monitoring unit that monitors a voltage state of the second power supply voltage group or the third power supply voltage group. A liquid crystal drive device comprising means for switching the power supply voltage supplied to the data storage means from the voltage of the second power supply voltage group or the voltage of the third power supply voltage group to the voltage of the first power supply voltage group. 7. The liquid crystal drive device according to claim 6, wherein the power supply monitoring means includes means for externally monitoring the state of the second power supply voltage group. 8. The power supply monitoring means according to claim 6, wherein the power supply monitoring means includes a pair of high-potential-side power supply voltage and low-potential-side power supply voltage in the second power supply voltage group or the third power supply voltage group. Means for dividing the voltage difference from the power supply voltage to generate a divided voltage; means for comparing the divided voltage with a reference voltage generated from the first power supply voltage group; and turning on based on the comparison result from the comparing means. A switching means that is turned off and switches the power supply voltage supplied to the display data storage means from the voltage of the second power supply voltage group or the voltage of the third power supply voltage group to the voltage of the first power supply voltage group. A liquid crystal drive device characterized by the above. 9. A liquid crystal display device comprising at least the liquid crystal drive device according to claim 1 and a liquid crystal panel in which liquid crystal elements are arranged in a matrix. 10. A low voltage amplitude operation part having at least a control logic part and operated by being supplied with a first power supply voltage group, and a low voltage amplitude operation part used for driving liquid crystal elements arranged in a matrix on a liquid crystal panel. A liquid crystal driving method used in a liquid crystal driving device, comprising: a high voltage amplitude operating portion which is supplied with a second power supply voltage group to operate, wherein at least one pair of high voltage power supplies included in the second power supply voltage group. The voltage difference between the potential side power supply voltage and the low potential side power supply voltage is set to be larger than the voltage difference between the high potential side power supply voltage and the low potential side power supply voltage included in the first power supply voltage group, and the liquid crystal panel Display data for displaying an image in the display data storage means, and the second power supply voltage group, or a third power supply voltage group obtained by converting the second power supply voltage group, Display data description Liquid crystal driving method and supplying the operating power means.