JPH0722863A - Current limiting circuit - Google Patents

Current limiting circuit

Info

Publication number
JPH0722863A
JPH0722863A JP18666893A JP18666893A JPH0722863A JP H0722863 A JPH0722863 A JP H0722863A JP 18666893 A JP18666893 A JP 18666893A JP 18666893 A JP18666893 A JP 18666893A JP H0722863 A JPH0722863 A JP H0722863A
Authority
JP
Japan
Prior art keywords
trs
transistors
current
output
resistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18666893A
Other languages
Japanese (ja)
Inventor
Tsugio Takagi
次男 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Columbia Techno Kk
Original Assignee
Columbia Techno Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Columbia Techno Kk filed Critical Columbia Techno Kk
Priority to JP18666893A priority Critical patent/JPH0722863A/en
Publication of JPH0722863A publication Critical patent/JPH0722863A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the distortion like a spike generated by the condition of a load connected to an amifier by cascoding voltage level shift elements and limiting VBE of an output transistor TR to a certain value. CONSTITUTION:Collector currents of TRs TR7 and TR8 are outputted by currents of resistors R1 and R2 between emitters and bases of TRs TR5 and TR6 constituting the amplifier where TRs TR5 and TR7 and TRs TR6 and TR8 are cascoded from both ends of resistors R1 and R2. Currents of resistor R1 and R2 are detected by TRs TR3 to TR6 and are current-converted by TRs TR7 and TR8 to turn on TRs TR9 and TR10 through resistors R5 and R6, and VBEs of output TRs TR1 and TR2 are limited by diodes D1 and D2 and TRs TR9 and TR10 to limit the emitter currents of output TRs TR1 and TR2 to a certain value.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、増幅器の電流制限回路
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier current limiting circuit.

【0002】[0002]

【従来の技術】従来電力増幅器等に於ける増幅器の終段
素子の電流制限は、図3に示すように通常終段素子のエ
ミッタ抵抗R1,R2の両端電圧を検出し、検出用のトラ
ンジスタTR3,TR4をONさせ出力トランジスタTR
1,TR2のベースと出力端をダイオードD1,D2を介し
それぞれ短絡することにより、終段素子のトランジスタ
TR1,TR2の出力電流を制限するようになされてい
た。
2. Description of the Related Art As shown in FIG. 3, the current limit of the final-stage element of an amplifier in a conventional power amplifier or the like is normally detected by detecting the voltage across the emitter resistors R1 and R2 of the final-stage element and detecting the transistor TR3. , TR4 is turned on and output transistor TR
The bases of 1 and TR2 and the output terminals are short-circuited via the diodes D1 and D2, respectively, to limit the output currents of the transistors TR1 and TR2 of the final stage element.

【0003】[0003]

【発明が解決しようとする課題】電力増幅器の終段素子
がB級増幅動作時等にはエミッタ抵抗R1,R2に流れる
電流が出力トランジスタTR1,TR2,ON−OFFす
る際に大幅に変化するため、抵抗器のインダクタンスと
プリント基板等のインダクタンス等により逆起電力が発
生し、抵抗R1,R2の両端にスパイク状の電圧が発生す
る。このひずみは出力トランジスタTR1,TR2のスイ
ッチングひずみ及びクロスオーバひずみ等と同様のひず
みであり増幅器のひずみ等劣化の一要因となって隠され
ていた。
The current flowing through the emitter resistors R1 and R2 greatly changes when the output transistors TR1 and TR2 are turned on and off when the final stage element of the power amplifier is in the class B amplification operation. The counter electromotive force is generated by the inductance of the resistor and the inductance of the printed circuit board, etc., and a spike-like voltage is generated across the resistors R1 and R2. This distortion is the same as the switching distortion and crossover distortion of the output transistors TR1 and TR2, and is hidden as a factor of deterioration of the amplifier distortion.

【0004】[0004]

【課題を解決するための手段】そのため本発明は、電力
増幅器の電力増幅素子の電流を制限する回路に、電力増
幅素子と縦列接続された電圧レベルシフト素子を有し、
電圧レベルシフト素子はカスコード接続され、電圧レベ
ルシフト回路素子に流れる電流を検出し、出力トランジ
スタのベース電流を制限することにより電力増幅素子の
VBE又はVGSを一定値に制限することにより電力増幅素
子の電流を制限する電流制限回路である。
Therefore, according to the present invention, a circuit for limiting a current of a power amplification element of a power amplifier has a voltage level shift element connected in series with the power amplification element,
The voltage level shift element is cascode-connected, the current flowing through the voltage level shift circuit element is detected, and the base current of the output transistor is limited to limit VBE or VGS of the power amplification element to a constant value. It is a current limiting circuit that limits the current.

【0005】[0005]

【実施例】本発明の一実施例を図面により説明する。図
1は本発明の一実施例を示す回路図である。極性の異な
る出力トランジスタTR1,TR2のそれぞれのエミッタ
が負荷RLに接続される。
An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. The emitters of the output transistors TR1 and TR2 having different polarities are connected to the load RL.

【0006】出力トランジスタTR1,TR2のコレクタ
にそれぞれ縦列接続されるレベルシフト素子の回路が接
続され、出力トランジスタTR1,TR2のベースに信号
入力がコンデンサC1及びバイアス用定電流源A1,A2
をそれぞれ介して電源+Vcc1,−Vcc1に接続される。
Circuits of level shift elements connected in series are connected to the collectors of the output transistors TR1 and TR2, respectively, and the signal inputs to the bases of the output transistors TR1 and TR2 are a capacitor C1 and bias constant current sources A1 and A2.
Are respectively connected to the power sources + Vcc1 and -Vcc1.

【0007】レベルシフト素子の回路は出力トランジス
タTR1,TR2のコレクタにそれぞれ抵抗R1,R2を介
しトランジスタTR3,TR4のエミッタに接続される。
トランジスタTR3,TR4のベースはそれぞれバイアス
用定電流源A3,A4を介して電源+Vcc3,−Vcc3に接
続され、コレクタは電源+Vcc2,−Vcc2に接続され、
トランジスタTR3,TR4はON状態にバイアスされて
いる。
In the circuit of the level shift element, the collectors of the output transistors TR1 and TR2 are connected to the emitters of the transistors TR3 and TR4 via resistors R1 and R2, respectively.
The bases of the transistors TR3 and TR4 are connected to the power supplies + Vcc3 and -Vcc3 via the biasing constant current sources A3 and A4, respectively, and the collectors are connected to the power supplies + Vcc2 and -Vcc2,
The transistors TR3 and TR4 are biased in the ON state.

【0008】抵抗R1,R2のそれぞれ両端からトランジ
スタTR5,TR7とTR6,TR8のカスコード接続され
た増幅器を構成するTR5,TR6のエミッタベース間に
接続されて抵抗R1,R2に流れる電流により、トランジ
スタTR7,TR8のコレクタ電流を出力する。
Transistors TR7 and TR2 are connected between the emitters and bases of TR5 and TR6, which form a cascode-connected amplifier of transistors TR5 and TR7 and TR6 and TR8, from both ends of the resistors R1 and R2. , TR8 collector current is output.

【0009】トランジスタTR7,TR8のエミッタはそ
れぞれ電源+Vcc2,−Vcc2に接続され、トランジスタ
TR5,TR6 のコレクタにそれぞれトランジスタTR
7,TR8のベースが接続されると共に抵抗R3,R4をそ
れぞれ介して電源+Vcc2,−Vcc2に接続されている。
The emitters of the transistors TR7 and TR8 are connected to the power supplies + Vcc2 and -Vcc2, respectively, and the collectors of the transistors TR5 and TR6 are connected to the transistor TR, respectively.
The bases of 7 and TR8 are connected and also connected to the power sources + Vcc2 and -Vcc2 via resistors R3 and R4, respectively.

【0010】トランジスタTR7,TR8のエミッタはそ
れぞれ電源+Vcc2,−Vcc2に接続され、コレクタはそ
れぞれ抵抗R5,R6を介してトランジスタTR9,TR1
0 のベースに接続され、トランジスタTR9,TR10 の
コレクタはそれそれダイオードD1,D2を介して出力ト
ランジスタTR1,TR2のベースに接続される。トラン
ジスタTR9,TR10 のエミッタは共に出力トランジス
タTR1,TR2のエミッタに接続される。
The emitters of the transistors TR7 and TR8 are connected to the power sources + Vcc2 and -Vcc2, respectively, and the collectors are connected to the transistors TR9 and TR1 via the resistors R5 and R6, respectively.
Connected to the base of 0, the collectors of the transistors TR9 and TR10 are respectively connected to the bases of the output transistors TR1 and TR2 via the diodes D1 and D2. The emitters of the transistors TR9 and TR10 are both connected to the emitters of the output transistors TR1 and TR2.

【0011】従って、レベルシフト素子として組まれた
抵抗R1,R2に流れる電流をトランジスタ検出用トラン
ジスタTR5,TR6で検出し、トランジスタTR7,T
R8で電流変換した後抵抗R5,R6をそれぞれ介してト
ランジスタTR9,TR10 をONさせ、出力トランジス
タTR1,TR2のVBEをダイオードD1,D2及びトラン
ジスタTR9,TR10 で制限し、出力トランジスタTR
1,TR2のエミッタ電流を一定に制限する。
Therefore, the currents flowing through the resistors R1 and R2 incorporated as level shift elements are detected by the transistor detection transistors TR5 and TR6, and the transistors TR7 and T7 are detected.
After converting the current by R8, the transistors TR9 and TR10 are turned on via the resistors R5 and R6, respectively, and the VBE of the output transistors TR1 and TR2 is limited by the diodes D1 and D2 and the transistors TR9 and TR10.
1, Limit the emitter current of TR2 to a constant value.

【0012】図2は本発明の他の一実施例を示す回路図
である。カスコード接続の一部が図1とは異なるがほぼ
同じ動作をするので説明は略す。
FIG. 2 is a circuit diagram showing another embodiment of the present invention. A part of the cascode connection is different from that of FIG.

【0013】従来の図3に示す回路に用いたエミッタ抵
抗を介すことなく、出力トランジスタのエミッタと負荷
とが直接結合されるため、増幅器の内部抵抗が静的に
も、動的にも低くでき、図示せずも帰還が(有っても、
無くても)関係無く安定な出力信号を得ることができ
る。
Since the emitter of the output transistor and the load are directly coupled without using the emitter resistance used in the conventional circuit shown in FIG. 3, the internal resistance of the amplifier is low both statically and dynamically. Yes, you can get feedback (not shown,
A stable output signal can be obtained regardless of (without).

【0014】従って、増幅器の出力回線の配線条件によ
り生ずる逆起電力によるスパイク状のひずみ発生が無
く、低ひずみ高性能な増幅器を提供することができる。
Therefore, it is possible to provide a high-performance amplifier with low distortion, without generation of spike-like distortion due to back electromotive force caused by wiring conditions of the output line of the amplifier.

【0015】[0015]

【発明の効果】本発明によると電圧レベルシフト素子を
カスコード接続にし、出力トランジスタのVBEを一定に
なるように制限したので増幅器に接続される負荷条件に
よって生ずるスパイク状のひずみを防止することがで
き、動作も安定している電流制限回路を得ることができ
る。
According to the present invention, since the voltage level shift element is cascode-connected and the VBE of the output transistor is limited to be constant, spike-like distortion caused by the load condition connected to the amplifier can be prevented. It is possible to obtain a current limiting circuit whose operation is stable.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す回路図。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】本発明の他の一実施例を示す回路図。FIG. 2 is a circuit diagram showing another embodiment of the present invention.

【図3】従来の回路を示す図。FIG. 3 is a diagram showing a conventional circuit.

【符号の説明】[Explanation of symbols]

TR1〜10 トランジスタ D1,2 ダイオード R1〜R6 抵抗 TR1 ~ 10 Transistor D1,2 Diode R1 ~ R6 Resistance

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成5年7月28日[Submission date] July 28, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0006[Correction target item name] 0006

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0006】出力トランジスタTR1,TR2のコレク
タにそれぞれ縦列接続されるレベルシフト素子の回路が
接続され、出力トランジスタTR1,TR2のベースに
信号入力がベースバイアス電源BT1及びバイアス用定
電流源A1,A2をそれぞれ介して電源+Vcc1,−
Vcc1に接続される。
Circuits of level shift elements connected in series are connected to the collectors of the output transistors TR1 and TR2, respectively, and a signal input to the bases of the output transistors TR1 and TR2 includes a base bias power source BT1 and bias constant current sources A1 and A2. Power supply + Vcc1, -via each
Connected to Vcc1.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0011[Correction target item name] 0011

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0011】従って、レベルシフト素子として組まれた
抵抗R1,R2に流れる電流を出力端からレベルシフト
用電源BT3,BT2を介しトランジスタTR3,TR
4及び検出用のトランジスタTR5,TR6で検出し制
御して、トランジスタTR7,TR8で電流変換した後
抵抗R5,R6をそれぞれ介してトランジスタTR9,
TR10をONさせ、出力トランジスタTR1,TR2
のVBEをダイオードD1,D2及びトランジスタTR
9,TR10で制限し、出力トランジスタTR1,TR
2のエミッタ電流を一定に制限する。
Therefore, the current flowing through the resistors R1 and R2, which are incorporated as level shift elements, is level-shifted from the output end.
Power supply BT3, BT2 through transistors TR3, TR
4 and detection transistors TR5 and TR6 detect and control
And your, transistor TR7, TR8 via respective resistors R5, R6 after current conversion at the transistor TR9,
Turn on TR10 to output transistors TR1, TR2
VBE of diode D1, D2 and transistor TR
9 and TR10 limit output transistor TR1, TR
Limit the emitter current of 2 to a constant value.

【手続補正3】[Procedure 3]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】全図[Correction target item name] All drawings

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図1】 [Figure 1]

【図2】 [Fig. 2]

【図3】 [Figure 3]

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電力増幅器の電力増幅素子の電流を制限
する回路に於いて、電力増幅素子と縦列接続された電圧
レベルシフト素子を有し、上記電圧レベルシフト素子は
カスコード接続され、上記電圧レベルシフト回路素子に
流れる電流を検出し、出力トランジスタのベース電流を
制限することにより上記電力増幅素子のVBE又はVGSを
一定値に制限することにより上記電力増幅素子の電流を
制限することを特徴とする電流制限回路。
1. A circuit for limiting a current of a power amplification element of a power amplifier, comprising a voltage level shift element cascade-connected to the power amplification element, said voltage level shift element being cascode-connected, said voltage level A current flowing through the shift circuit element is detected, and the base current of the output transistor is limited to limit VBE or VGS of the power amplification element to a constant value, thereby limiting the current of the power amplification element. Current limiting circuit.
JP18666893A 1993-06-30 1993-06-30 Current limiting circuit Pending JPH0722863A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18666893A JPH0722863A (en) 1993-06-30 1993-06-30 Current limiting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18666893A JPH0722863A (en) 1993-06-30 1993-06-30 Current limiting circuit

Publications (1)

Publication Number Publication Date
JPH0722863A true JPH0722863A (en) 1995-01-24

Family

ID=16192576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18666893A Pending JPH0722863A (en) 1993-06-30 1993-06-30 Current limiting circuit

Country Status (1)

Country Link
JP (1) JPH0722863A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106330171A (en) * 2016-08-26 2017-01-11 成都启臣微电子股份有限公司 Positive and negative voltage dynamic bias level shifting circuit based on negative voltage detection and band-gap reference

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106330171A (en) * 2016-08-26 2017-01-11 成都启臣微电子股份有限公司 Positive and negative voltage dynamic bias level shifting circuit based on negative voltage detection and band-gap reference
CN106330171B (en) * 2016-08-26 2019-05-24 成都启臣微电子股份有限公司 Positive/negative-pressure dynamic bias level displacement circuit based on detection of negative pressure and band-gap reference

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