JPH07226525A - Semiconductor laminated structure, semiconductor device and manufacture of those - Google Patents

Abstract

PURPOSE:To provide a semiconductor laminated structure wherein a compound semiconductor layer, which has a grating constant different from that of a semiconductor substrate and is superior in quality, is provided on this semiconductor substrate. CONSTITUTION:A semiconductor laminated structure consists of a P-type hiavily doped GaAs buffer layer 2, an Al layer 3, an AlAs layer 4 and a P-type GaAs layer 5, which are provided on a P-type Si substrate 1. Here, the grating constant of the substrate 1 is different from that of the layer 2, but the rise of a dislocation in the layer 2 can be inhibited by the layer 3. The layer 4 is formed of a compound semiconductor layer containing Al of the layer 3 as its constituent element and the layer 5 is formed of one having the same crystal structure as that of the layer 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laminated structure composed of a plurality of semiconductors having different lattice constants, a manufacturing method thereof, a semiconductor device having such a semiconductor laminated structure, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a layered structure in which a GaAs layer is formed on a Si substrate, lattice mismatch dislocations occur because the lattice constants of the two differ by 7%, and the performance of a semiconductor device formed on the layered structure is improved. Various methods have been conventionally proposed for reducing this dislocation in order to cause deterioration. this house,
Two-step growth method and thermal cycle annealing are effective methods for reducing dislocations. The two-step growth method is a method in which an amorphous film is formed at a low temperature in the initial stage of growth and an epitaxial film is formed thereon at a high temperature. The thermal cycle annealing is a method in which the growth is temporarily stopped during the formation of the laminated structure and the step of changing the sample temperature from a high temperature (700 ° C. to 900 ° C.) to a low temperature (300 ° C.) is repeated several times. By these methods, the dislocation density can be reduced from 10 ⁸ cm ^-3 to 10 ⁶ cm ^-3 . However, in manufacturing a semiconductor device performance comparable to the GaAs substrate, it is necessary to reduce the dislocation density to ^-3 10 ⁴ cm.

Therefore, further, InGaAs / GaA
A method has been adopted in which an s-isostrained superlattice is inserted in a laminated structure and a large number of interfaces prevent rise of dislocations. Japan Journal of Applied Physics, 30
(1991) L668 to L671 (Jpn.
J. Appl. Phys. 30 (1991) pp. L6
68-L671), thermal cycle annealing, InGaAs / GaAs strained superlattice method are adopted, and further, the migration enhancement is performed at low temperature by forming one crystal layer at a time interval.
A dislocation density of 10 ⁵ cm ^-3 or less has been realized by the epitaxy method.

[0004]

Since the conventional thermal cycle annealing uses a high temperature of 900 ° C., in a semiconductor device having a pn junction and a heterogeneous semiconductor junction, dopant atoms or semiconductor constituent atoms are diffused to cause a junction. There was a problem that the steepness of could not be maintained. Further, in the migration enhancement epitaxy method, since the entire laminated structure is formed at a low temperature, impurities are easily taken in and a film with good crystallinity is difficult to obtain. There is a problem that it is unsuitable to use when doing.

A first object of the present invention is to provide on a semiconductor substrate,
Another object of the present invention is to provide a semiconductor laminated structure provided with a compound semiconductor layer having a different lattice constant and excellent quality. A second object of the present invention is to provide a semiconductor device having such a semiconductor laminated structure. A third object of the present invention is to provide a method for manufacturing such a semiconductor laminated structure. A fourth object of the present invention is to provide a method of manufacturing such a semiconductor device.

[0006]

In order to achieve the first object, the semiconductor laminated structure of the present invention has a first compound semiconductor layer arranged on a semiconductor substrate, and a first compound semiconductor layer laminated on this layer. And a second compound semiconductor layer having the element of the metal layer as one of the constituent elements, the metal layer being composed of at least one of the constituent elements of the desired compound semiconductor, and this layer. A third compound semiconductor layer laminated on the semiconductor substrate, and the semiconductor substrate and the first compound semiconductor are
The second compound semiconductor and the third compound semiconductor have different lattice constants, and have the same crystal structure.

The metal layer is made of, for example, a compound semiconductor of III-
In the case of a group V compound semiconductor, Al that is a constituent element thereof
Any layer such as In or In may be used. When this layer is Al,
AlAs or the like may be used as the second compound semiconductor. The layer of the second compound semiconductor preferably has a thickness of substantially one atomic layer.

In order to achieve the second object,
A semiconductor device of the present invention comprises any one of the above semiconductor laminated structures and a semiconductor element arranged on the semiconductor laminated structure. The semiconductor element may be formed not only on the laminated structure but also on the semiconductor substrate below the metal layer.

Further, in order to achieve the third object,
According to the method for manufacturing a semiconductor laminated structure of the present invention, a first compound semiconductor layer having a lattice constant different from that of the semiconductor substrate is formed on a semiconductor substrate, and a desired compound semiconductor layer is formed on the layer. A metal layer made of at least one of the constituent elements is formed, and the surface layer of the metal layer is changed to a second compound semiconductor at a temperature equal to or lower than the melting point of the metal forming the metal layer. On top of the second layer
The third compound semiconductor layer having the same crystal structure as that of the compound semiconductor is formed.

The metal layer is as described above. The substrate temperature when forming the metal layer is preferably a temperature not higher than the melting point of the metal. Further, for example, when this layer is Al and the layer is irradiated with As, the surface layer changes to AlAs. This AlAs becomes the second compound semiconductor. When As is irradiated at a temperature lower than the melting point of Al, substantially one atomic layer of the surface layer of the metal layer is AlA.
can be changed to s.

In order to achieve the above-mentioned fourth object,
A method for manufacturing a semiconductor device of the present invention comprises forming a compound semiconductor junction of the same kind or different kinds on a semiconductor laminated structure manufactured by any one of the methods for manufacturing a semiconductor laminated structure described above, and forming at least the junction. It is designed to be a part of a semiconductor device.

In this method of manufacturing a semiconductor device, for example, a photoelectric conversion element is previously formed on a semiconductor substrate,
By forming a laminated structure of a layer of the first compound semiconductor or more thereon and further forming a photoelectric conversion element thereon, a semiconductor device in which elements are provided above and below the metal layer can be manufactured. .

[0013]

For convenience of explanation, the semiconductor substrate is made of Si, the first and third compound semiconductors are GaAs, and the metal is A.
The operation of the present invention will be described assuming that it is 1 or In. Si
By disposing the GaAs layer and the Al or In metal layer on the substrate, the electric interaction due to the electrostatic field of the metal, and the interface formed by the heteroatom of GaAs and Al or In The increase in the frictional force at s1 slows the movement of the dislocations. Therefore, Si and GaA
It is possible to prevent upward movement of dislocations that occur at the s interface and propagate in the laminated structure.

Further, the surface of the Al or In layer having a melting point not higher than that of Al or In is irradiated with As to expose AlAs or InAs.
, The Al or In layer is a solid phase,
Reacts only with surface atoms without melting into the metal layer,
The surface layer can be changed to AlAs or InAs. Therefore, thinly strained AlAs and InAs can be formed, and new lattice mismatch dislocations do not occur.

Further, the surface region of the metal layer is covered with AlAs or I
In the case of an nAs layer, AlAs or InAs has the same crystal structure as GaAs, and therefore GaAs formed on it.
Can be epitaxially grown.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. <Embodiment 1> FIG. 1 is a sectional view of a semiconductor device having a photoelectric conversion element according to an embodiment of the present invention. This photoelectric conversion element includes a p-type Si substrate 1, a high-concentration p-type GaAs buffer layer 2, an Al layer 3, an AlAs layer 4, and a high-concentration p-type GaAs layer 2.
′, P-type GaAs layer 5, high-concentration n-type GaAs layer 6 and n
P-type GaAs having a laminated structure of the AlGaAs layer 7
A photoelectric conversion part having a pn structure is formed in the layer 5 and the high-concentration n-type GaAs layer 6. Further, the p-type electrode 10 is formed on the p-type Si substrate 1, and the high-concentration n-type GaA is formed on the surface of the n-type AlGaAs layer 7.
An s layer 8 and an n-type electrode 9 are formed. The manufacturing method of this semiconductor device will be described below.

The p-type Si substrate 1 has a p-type and a resistivity of 0.
A substrate having 5 Ωcm, a thickness of 0.4 μm, a (001) plane orientation, and a 2 ° off tilt in the <110> direction is used. After the substrate is washed with organic material and washed with water, a thin oxide film is formed on the surface by chemical etching and immediately introduced into a molecular beam crystal growth apparatus. The oxide film formed on the p-type Si substrate 1 is 900 ° C. in an As atmosphere in a crystal growth apparatus.
It is decomposed and removed by heating for 10 minutes. After that, the substrate temperature is lowered to 400 ° C., a part of the high-concentration p-type GaAs buffer layer 2 is formed to a thickness of 0.1 μm, and the substrate temperature is set to 6 μm.
The temperature is raised to 00 ° C. and the high-concentration p-type GaAs buffer layer 2 is set to 2 μm.
m.

Here, the As cell temperature is lowered to room temperature, the substrate temperature is lowered to 400 ° C., and the Al layer 3 is made up of 5 atomic layers.
1 nm is formed. After that, the temperature of the As cell is raised and As is irradiated by a shutter operation, so that the Al of the surface layer of the Al layer 3 is irradiated.
To AlAs layer 4. Since the melting point of Al is 659 ° C., Al is a solid phase on a substrate at 400 ° C. For this reason,
By As irradiation, As does not go into the Al layer, and only the surface layer Al can be changed to AlAs.

After that, the high concentration p-type GaAs layer 2'is
m. The substrate temperature at this time is 400 immediately after the growth.
C., and after growing about 0.1 μm, up to 600 ° C.,
Gradually raise. The GaAs formed so far is B
It is a high-concentration p-type with an e concentration of 1 × 10 ¹⁹ cm ⁻³ . After this,
At a substrate temperature of 600 ° C., a p-type GaAs layer (Be concentration; 8 ×
10 ¹⁶ cm ⁻³ ) 5 to 2.5 μm, higher concentration n-type Ga
0.5 μm of As layer (Si concentration; 3 × 10 ¹⁸ cm ⁻³ ) 6
m, sequentially stacked.

When the sample having the laminated structure produced by the above method was etched in KOH at 350 ° C. for 4 minutes and the sample surface was observed with a microscope, it was 7 × 10 ⁴ to 1 × 10 ⁵ c.
An etch pit of m ^-3 is observed. This value is
It is of the same order as the value observed with the aAs substrate.

In order to manufacture a photoelectric conversion element, a high concentration n
N-type AlG as a window layer on the n-type GaAs layer 6
The aAs layer (Si concentration; 3 × 10 ¹⁸ cm ⁻³ ) 7 is set to 300
Å A high-concentration n-type GaAs layer (Si concentration; 5 × 10 ¹⁸ cm ⁻³ ) 8 of 1000 Å is laminated as an electrode connecting portion. Then, the high-concentration n-type GaAs layer 8 is etched leaving only the n-type electrode portion to form the n-type electrode 9 and the p-type electrode 10.

The produced photoelectric conversion element is a GaAs produced on a GaAs substrate with a general dislocation density of 10 ⁴ cm ^-3.
The efficiency of the photoelectric conversion element is 70 to 80%, and the manufacturing cost is reduced by almost one digit.

In this embodiment, the p-type Si substrate 1 is used.
N-type, high-concentration p-type GaAs buffer layer 2, high-concentration p
-Type GaAs layers 2 ′ are respectively made into high-concentration n-type and p-type GaA
The s layer 5 is n-type, the high-concentration n-type GaAs layer 6 is high-concentration p-type, the n-type AlGaAs layer 7 is p-type, and high-concentration n-type GaA.
Even if the s layer 8 is a high-concentration p-type, the n-type electrode 9 is a p-type, and the p-type electrode 10 is an n-type, the same effect is obtained.

<Embodiment 2> FIG. 2 is a sectional view of a semiconductor device having a photoelectric conversion element according to another embodiment of the present invention. This photoelectric conversion element includes a p-type Si substrate 11 and a high-concentration p-type Ga substrate.
The As buffer layer 12, the In layer 13, the InAs layer 14, the high-concentration p-type GaAs layer 12 ′, the p-type GaAs layer 15, the high-concentration n-type GaAs layer 16, and the n-type AlGaAs layer 17 are laminated to form a p-type GaAs. Layer 15, high concentration n-type Ga
A photoelectric conversion part having a pn structure is formed in the As layer 16.
Further, the p-type electrode 20 is formed on the p-type Si substrate 11 by the n-type Al.
A high concentration n-type GaAs layer 18 and an n-type electrode 19 are formed on the surface of the GaAs layer 17. The manufacturing method of this semiconductor device will be described below.

The p-type Si substrate 1 is manufactured in the same manner as in the above embodiment.
A high-concentration p-type GaAs buffer layer 12 having a thickness of 2 μm is formed on the substrate 1. After that, while lowering the As cell temperature to room temperature,
The substrate temperature is lowered to 100 ° C., the In layer 13 is made up of 5 atomic layers,
1.2 nm is formed. After that, the As cell temperature is raised and As is irradiated by a shutter operation to change the In of the surface layer of the In layer 13 to the InAs layer 14. In has a melting point of 156
Since the temperature is ° C, In is a solid phase at the time of As irradiation.

After that, the high-concentration p-type GaAs layer 12 'is formed into 1
μm is formed. The substrate temperature at this time is 10 immediately after the growth.
After the temperature is set to 0 ° C. and the growth is performed for about 0.1 μm, the temperature is gradually increased to 600 ° C. GaA formed so far
s is a high-concentration p-type with a Be concentration of 1 × 10 ¹⁹ cm ⁻³ .
Then, at a substrate temperature of 600 ° C., the p-type GaAs layer (Be concentration; 8 × 10 ¹⁶ cm ⁻³ ) 15 is 2.5 μm, and the high concentration n-type GaAs layer (Si concentration; 3 × 10 ¹⁸ cm ⁻³ ) 16 is formed. 0.
5 μm, stacked in order.

The etch pit density of the sample having the laminated structure produced by the above method is 5 × 10 ⁴ to 1 × 10 ⁵ cm ^-3 . Since In, which is heavier than Al in Example 1, is used, the ability to prevent dislocation movement is increased.

In order to manufacture a photoelectric conversion element, a high concentration n
On the n-type GaAs layer 16 and n-type Al as a window layer
The GaAs layer (3 × 10 ¹⁸ cm ⁻³ ) 17 is 300 liters, and the high-concentration n-type GaAs layer (5 × 10 ¹⁸ c) is used as an electrode connecting portion.
m ^-3 ) 18 is laminated by 1000Å. Then, the high-concentration n-type GaAs layer 18 is etched leaving only the n-type electrode portion to form the n-type electrode 19 and the p-type electrode 20. The performance of the photoelectric conversion element is equivalent to that of the above-mentioned embodiment.

Also in this embodiment, the p-type Si substrate 11 is n-type, the high-concentration p-type GaAs buffer layer 12 and the high-concentration p-type GaAs layer 12 'are high-concentration n-type, and p-type Ga is used.
The As layer 15 is n-type, the high-concentration n-type GaAs layer 16 is p-type, the n-type AlGaAs layer 17 is p-type, and the high-concentration n-type Ga is
The As layer 18 is a high-concentration p-type, the n-type electrode 19 is a p-type, and the p-type is
Even if the mold electrode 20 is an n-type, the same effect can be obtained.

[0030]

As in the above embodiments, the movement of dislocations is slowed down by inserting a metal layer such as Al or In in the middle of the laminated structure. Therefore, it is possible to prevent upward movement of dislocations that occur at the interface between Si and GaAs and propagate in the laminated structure.

AlAs and In formed on the metal layer
Since As has the same crystal structure as GaAs and is very thinly strained, the GaAs layer formed thereon grows epitaxially and new dislocations due to lattice mismatch do not occur.

Therefore, Ga formed on the upper part of the laminated structure
The dislocation density in As is almost the same as that of a commercial GaAs substrate.
0 ⁵ cm ^-3 can be reduced to below the semiconductor element produced exhibits a performance similar to that produced on a GaAs substrate. Moreover, if inexpensive Si is used as the substrate,
It can be about 10.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device having a photoelectric conversion element according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device having a photoelectric conversion element according to a second embodiment of the present invention.

[Explanation of symbols]

1, 11 ... p-type Si substrate, 2, 12 ... high-concentration p-type GaA
s buffer layer, 2 ', 12' ... high-concentration p-type GaAs layer,
3 ... Al layer, 4 ... AlAs layer, 5, 15 ... P-type GaAs
Layers, 6, 16 ... High-concentration n-type GaAs layer, 7, 17 ... n-type AlGaAs layer, 8, 18 ... High-concentration n-type GaAs layer,
9, 19 ... N-type electrode, 10, 20 ... P-type electrode, 13 ... I
n layer, 14 ... InAs layer.

Claims (12)

[Claims] 1. A semiconductor substrate, a layer of a first compound semiconductor arranged on the semiconductor substrate, and at least one of constituent elements of a desired compound semiconductor laminated on the layer of the first compound semiconductor. A metal layer, laminated on the metal layer,
A second compound semiconductor layer having an element of the metal layer as one of the constituent elements and a third compound semiconductor layer laminated on the second compound semiconductor layer;
The compound semiconductor of (1) has a different lattice constant, and the second compound semiconductor and the third compound semiconductor have the same crystal structure. 2. The semiconductor laminated structure according to claim 1, wherein
The semiconductor laminated structure, wherein the second compound semiconductor layer has a thickness of substantially one atomic layer. 3. The semiconductor laminated structure according to claim 1 or 2, wherein each of the first, second and third compound semiconductors is a III-V group compound semiconductor. 4. The semiconductor laminated structure according to claim 1, 2 or 3, wherein the semiconductor substrate is Si. 5. The semiconductor laminated structure according to claim 4,
The first and third compound semiconductors are GaAs,
The second compound semiconductor is AlAs, and the metal layer is made of Al. 6. The semiconductor laminated structure according to claim 4,
The first and third compound semiconductors are GaAs,
The semiconductor laminated structure, wherein the second compound semiconductor is InAs and the metal layer is made of In. 7. A semiconductor device comprising the semiconductor laminated structure according to claim 1 and a semiconductor element arranged on the semiconductor laminated structure. 8. A first step of forming a layer of a first compound semiconductor having a lattice constant different from that of the semiconductor substrate on a semiconductor substrate, the desired compound being formed on the layer of the first compound semiconductor. Second step of forming a metal layer composed of at least one of the constituent elements of the semiconductor, third step of changing the surface layer of the metal layer into a second compound semiconductor at a temperature equal to or lower than the melting point of the metal forming the metal layer And a fourth step of forming, on the second compound semiconductor layer, a third compound semiconductor layer having the same crystal structure as that of the second compound semiconductor. Method. 9. The method for manufacturing a semiconductor laminated structure according to claim 8, wherein the thickness of the surface layer of the metal layer changed to the second compound semiconductor is substantially the thickness of one atomic layer. A method for manufacturing a semiconductor laminated structure, comprising: 10. The method for manufacturing a semiconductor laminated structure according to claim 8 or 9, wherein the third step comprises:
A method for manufacturing a semiconductor laminated structure, which is carried out by irradiating an element different from the metal of the constituent elements of the second compound semiconductor. 11. The method for manufacturing a semiconductor laminated structure according to claim 8, 9, or 10, wherein each of the first, second, and third compound semiconductors is a III-V group compound semiconductor. Method for manufacturing semiconductor laminated structure. 12. A compound semiconductor junction is formed on the semiconductor laminated structure produced by the method for producing a semiconductor laminated structure according to claim 8, and the junction is formed in at least one of semiconductor elements. A method of manufacturing a semiconductor device, comprising: