JPH07226035A - Method and device for decoding data - Google Patents

Abstract

PURPOSE:To increase an effect of decoding the data while suppressing the increase of a circuit scale to the minimum in the decoding of the data obtained through a system where interference between codes exists. CONSTITUTION:By using a (d, k) code defining a minimal length of continuation of the same symbols (d) and a maximum length of the continuation of the same symbols (k), and by using the (d, k) code defining an interference between codes width N in a recording/reproducing system or a transmission system where code interference to an adjacent code section is allowed, to be 2<N<2(d+1)+1, Viterbi decoding is performed for the code. This device is provided with an equalizer part 1 waveform shaping a supplied input signal, an A/D converter 3 converting an output signal from the equalizer part into a digital signal, a phase locked loop part 2 generating a reproducing clock based on the output signal from the equalizer part, a Viteribi decoding part 4 Viterbi-decoding to the (d, k) code defining the interference between codes width N to be 2<N<2(d+1)+1 to the output signal from the A/D converter and a demodulation part 5 demodulating the output signal from the Viterbi decoding part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decoding method for decoding data obtained through a system having intersymbol interference such as a partial response method, and a data decoding apparatus using this data decoding method.

[0002]

2. Description of the Related Art Recent progress in high-density recording technology in digital recording is remarkable. This high-density recording is made possible not only by improving the performance of the recording medium and recording head, but also by adding various improvements to each signal processing method performed by the apparatus.

Among various signal processing methods, the partial response method is used as a signal detection method. The partial response method is a method in which a correlation code having a digital value is transmitted so that the influence of a code error caused by transmission line noise or the like will not be exerted later. In this partial response system, a circuit that performs a conversion process that provides correlation between codes that subtracts inter-code interference with subsequent data in advance is called a so-called precoder.

A Viterbi decoding method is used as a signal decoding method. This Viterbi decoding method is one of the maximum likelihood decoding methods that searches for the path with the shortest Hamming distance by reducing the decoding error, and simplifies the search for a probable value by decoding the path that has no possibility. Is.

As described above, the Viterbi decoding method utilizing the correlation between codes is well known. It is known that when the Viterbi decoding method is applied to a system having inter-code interference such as the partial response method described above, the error rate at the time of decoding can be significantly improved. FIG. 11 shows a basic system configuration of a recording / reproducing system using the partial response method and the Viterbi decoding method.

The recording side or the transmitting side has a modulator 10 for modulating the information supplied from the information source and an N for the NRZI conversion.
The RZI unit 11 and the recording amplifier 12 are used to record information on the recording medium M. The playback side or the receiving side
A reproduction amplifier 20 for amplifying a reproduction signal from the recording medium M
And an equalizer section 21 for equalizing the waveform, and an equalizer section 2
Phase locked loop (hereinafter referred to as PLL) circuit section 22 for extracting a reproduction clock from the output signal of No. 1 and A / D converter 23 for A / D converting the output signal of the equalizer section 21.
And a Viterbi decoding unit 24 that performs Viterbi decoding according to the reproduction clock, and a demodulation unit 25 that demodulates the output signal from the Viterbi decoding unit 24 into the original information according to the reproduction clock.

In a system such as the partial response system which allows intersymbol interference, input of new information to the encoder causes a transition to the next state. Such a state transition relationship is described by a state transition diagram. For example, FIG. 12 is a state transition diagram of a system in which inter-code interference is 4 bits and shows a Viterbi decoding algorithm in the Viterbi decoding unit 24 of FIG. By setting the intersymbol interference to 4 bits, the system takes the states S0 to Sf and 16 shown below.

S0: 0000 S1: 0001 S2: 0011 S3: 0010 S4: 0101 S5: 0100 S6: 0111 S7: 0110 S8: 1111 S9: 1110 Sa: 1100 Sb: 1101 Sc: 1010 Sd: 1011 Se: 1000 Sf: 1001 These states indicate bits after the NRZI conversion processing.

In the state of the system having the intersymbol interference width N = 4 shown in FIG. 12, each state has two paths. The state transition is represented by an arrow, and the transition condition from the previous state to the transition destination state is described on the tip side of the arrow. This described transition condition is represented by X / Y. Here, X is the modulation output data supplied from the modulator 10 of FIG. 11 to the NRZI converter 11. Y is an output that should be reproduced correctly from the recording medium M of FIG. 11 via the equalizer unit 21, and the subscript indicates the number of the transition state.

In the state transition of this Viterbi decoding, generally, the supplied data takes only binary values of "0" and "1" at the maximum, and therefore there are two states in the new state to be transitioned from other states. State transitions will only occur via the path. In the Viterbi decoding, of the two paths that enter a certain state, only the state having a higher likelihood that represents more certainty is left at each time based on the reproduction clock. In the Viterbi decoding unit 24, the sequence of the surviving paths due to the selection according to the likelihood becomes the same value after an appropriate time and is unified, and the decoded data X corresponding to the modulation output data is demodulated. 25 is output.

The Viterbi decoding unit 24, as shown in FIG. 13, for example, a so-called branch metric calculation circuit unit 24a for performing a branch distance calculation based on the digital data supplied via the A / D converter 23, and a branch. A survivor path selection circuit section 24b that selects a survivor path from the calculation result of the metric calculation circuit section 24a, and a normalization circuit section 2 that obtains a minimum value and normalizes it to prevent overflow.
4c, a state metric memory circuit section 24d for storing a state metric, and a path memory section 24e in which a 1-bit shift register and then a 1-bit shift register and a 1-bit multiplexer are arranged in n stages.

A specific circuit configuration of the above-mentioned Viterbi decoding unit 24 will be described with reference to the main circuit of FIGS. The branch metric calculation circuit section 24a is a section indicated by reference symbol A in the figure. Output data from the A / D converter 23 shown in FIG. 8 is supplied to one end side of the 16 branch metric calculation circuits. The values y _{0 to} y _{f of} the 16 reproduction outputs Y shown in the state transition diagram of FIG. 12 are supplied to the other ends of the 16 branch metric calculation circuits. For convenience of illustration, the output of the A / D converter 23 is displayed so as to be supplied to the other end of the branch metric calculation circuit via the input terminals 30 and 31.

Here, the metric represents the degree of certainty of a path from a certain time to each state.

These branch metric calculation circuits are
The difference between the output data from the D / D converter 23 and the reproduction output Y is squared, and the likelihood at the transition from the previous state to a certain state is output as an output signal to the surviving path selection circuit section. To do.

The survivor path selection circuit section 24b is designated by the symbol B.
It is composed of a survivor path selection circuit indicated by and a state metric calculation circuit indicated by reference sign C. The survivor path selection circuit is supplied with the metric of the past survivor path output from the state metric storage circuit described later. As shown in the state transition of FIG. 12, each state is 2
Since the transition is made from two states, arrows corresponding to two paths are input and two arrows are output. Further, the modulation output data X is displayed on the tip side of the arrow indicating the transition to this state.
And the reproduction output data y with a subscript indicating the state are displayed. Specifically, for example, in order to select the surviving path in the state transition of the state S0, the metric of the state S0 and the state Se output from the state metric storage circuit described later is output to the surviving path selection circuit corresponding to the reproduction output y _0. It will be supplied.

Here, the above-mentioned path represents a series of transitions from state to state.

The survivor path selection circuit makes a selection for the metric of these two states. The survivor path selection circuit outputs the selection result to the path memory unit 24e represented by the components indicated by the symbols F and G described later, and also outputs the metric of the selected state to the state metric calculation circuit. The state metric calculation circuit calculates the metric of a new surviving path from the branch metric and the state metric, which is the certainty of the surviving path in the past. Each survivor path selection circuit supplies a new survivor path metric to one end side of each normalization circuit indicated by the symbol D in the normalization circuit unit 24c. The state metric obtained by this survivor path selection circuit indicates the accumulation of past certainty. This state metric is meaningful in terms of relative size.

However, due to the above definition of the state metric, if the value of the state metric continues to accumulate as time goes by, the value of the state metric becomes too large and the state metric becomes meaningless. A normalization circuit section 24c is provided in order to add meaning to the relative size of the state metric while accumulating the state metric.

The normalization circuit section 24c is composed of 16 normalization circuits and a minimum value detection circuit Min. The minimum value detection circuit Min shown in FIG. 16 inputs the data in each of the states S0 to Sf and detects the minimum value. The minimum value detection circuit Min supplies the detected minimum value to the other end side of each normalization circuit of the normalization circuit section via the terminals 32 and 33. The normalization circuit normalizes the state metric value by subtracting the state metric value and the minimum value. The value of the state metric thus normalized is supplied to the state metric storage circuit section 24d indicated by the symbol E as the probability of the surviving path.

The state metric storage circuit section 24d is
The states S0 to S0 in which the display corresponding to the subscript of the reproduction output y is made from each of the 16 state metric memory circuits
The state metric of Sf is output. That is,
For example, when the input is the reproduction output y ₄ , the state metric storage circuit outputs the state metric of the state S4. The state metric of the state S4 output from the state metric storage circuit is supplied to the other end of the surviving path selection circuit of the reproduction output y _c shown in FIG. 15 and the reproduction output y _d shown in FIG. 16, respectively.

As described above, the path memory unit 24e is composed of a 1-bit register and a 1-bit multiplexer, which are represented by the symbols F and G, and which are, for example, flip-flop circuits. The first 1 in the path memory unit 24e
The bit register includes a state metric storage circuit unit 2
Modulation output data X for supplying the output state of 4d is supplied. The 1-bit register outputs the input modulated output data X. Numbers b _{00 to} b _0f are given to the outputs of the flip-flops in the same row as the 1-bit register.

After this 1-bit register, a path memory is constructed which includes a 1-bit multiplexer and a 1-bit register as a set. This path memory has n stages. The 2-input 1-bit multiplexer of the first-stage path memory supplies the respective state metrics to the terminals having the numbers corresponding to the numbers b _{00 to} b _0f output from the first 1-bit register. . The 1-bit multiplexer selects one of the numbers input according to the output signal from the survivor path selection circuit and supplies it to the memory of the 1-bit register. Furthermore, outputs the a series of processes from n-1 stage repeated n-th stage 1-bit register 16 number b _n0 ~b _nf. The data shown by these 16 numbers b _{n0 to} b _nf all have the same value.
The Viterbi decoding unit 24 selects any one of the 16 and outputs it as decoded data.

With this configuration, the determined survivor path and the decoded data, that is, the state transition modulation output data X shown in FIG. 12, have a one-to-one correspondence. In this way, when the path is selected and the output data is unified so that all the output data have the same value by the selection, it is understood that the decoding is completed as the decoded data. The data decoding corresponding to such modulated output data X requires a certain amount of time to select the data according to the path selection, and thus the path memory unit 24e described above is required.

[0024] A concrete study example of applying the partial response method and the Viterbi decoding method having such a configuration to high density recording is reported in IEICE Technical Report MR91-34 pp.19-24. ing. In this report, a high-density recording method applied to a high-definition digital video tape recorder which records a high-definition moving image and records / reproduces for a long time within a predetermined length is examined. .

In this report, in order to verify the optimum high density recording, 4-state Viterbi decoding for 1,7 codes is used as a recording code, and the error rate characteristic is obtained by computer simulation. Here, the 1,7 code is an encoding method for converting 2 bits of data bits into 3 bits of channel bits. The 1,7 code has a feature of a run-length limited code in which 1 or more and 7 or less "0" always enter between "1" and "1". However, NRZI is used for recording channel data because the DC components of the 1 and 7 codes are not free. Correlation of partial response (1,1) and 1,7
The result of utilizing the correlation of the codes shows that the 4-state Viterbi decoding has the best performance in both the three-value detection and the two-value detection, and is strong and stable against, for example, equalizer adjustment deviation and temporal change.

In general, in order to perform such high density recording, it is known that the reproduction band of the signal required by the device can be narrowed by increasing the intersymbol interference width.

[0027]

By the way, although the inter-code interference width is set to 4 bits in the above-mentioned example, if the inter-code interference width is further increased to enable high density recording, the Viterbi decoding algorithm is used. The number of states taken will increase exponentially. Therefore, the circuit configuration of Viterbi decoding with the increased number of states becomes a large-scale configuration.

In order to reduce the circuit scale of Viterbi decoding,
Recently, a method of adding a constraint to the constraint length d has been proposed.
A report on the Viterbi decoding method using such a d-constraint has been published in The Television Society of Japan, Vol. 44, No. 10 (1990) pp. 1369-1375.
It is in. In this report, PR (1,1), which is one of the partial response methods as a high-density recording code in magneto-optical recording, which is attracting attention as a rewritable large-capacity optical memory.
We are studying the combination of the scheme and the Viterbi decoding method, and the title of the paper is "New variable-length block code and d
Application of Viterbi decoding method using constraints to magneto-optical recording ”. In this paper, we developed a (3,19; 4,9; 3) code that can reduce waveform interference in magneto-optical recording, and use PR (1,1) method as a signal detection method and d constraint as a decoding method. A Viterbi decoding method that takes into account has been proposed. In this paper as well, compared with the case where the conventional peak detection method is adopted by obtaining the error rate characteristic by simulation,
It has been revealed that the N ratio is improved by about 2.9 dB.

For the constraint of such constraint length d, d = 1,
There are three cases, that is, two and three, and a method in which PR (1,1) by the partial response method and the Viterbi decoding method are combined has been reported. The intersymbol interference width N at this time is 2
Is.

However, even if Viterbi decoding is performed by paying attention only to the constraint of the constraint length d, if the inter-code interference width is ignored,
The data decoding effect deteriorates. If the inter-code interference width is increased to increase the recording density, the circuit scale of Viterbi decoding becomes large.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a data decoding method capable of suppressing the increase in the circuit scale and improving the data decoding effect. To aim.

Another object of the present invention is to provide a data decoding device which embodies the above data decoding method.

[0033]

In order to solve the above-mentioned problems, the data decoding method according to the present invention sets the minimum length of the series of identical symbols to d, and sets the maximum length of the series of identical symbols to k. In the data decoding method of performing data decoding using the (d, k) code, the inter-code interference width N in the recording / reproducing system or the transmission system in which the code interference to the adjacent code section is allowed is 2 <N <2. Let (d + 1) +1 (d, k)
A feature is that a code is used and Viterbi decoding is performed on the code.

Here, the intersymbol interference width N is 2 (d
+1) is preferable. Also, the minimum length d is 4
It is preferable to restrict

The data decoding device according to the present invention is a data decoding device that modulates information from an information source and decodes data that has been subjected to correlation processing between codes for subtracting inter-code interference generated in the modulated data in advance. In order to solve the above-mentioned problems in an apparatus, an equalizer unit that shapes the waveform of an input signal that is supplied, an A / D converter that converts the output signal from the equalizer unit into a digital signal, and an output signal from the equalizer unit The inter-code interference width N is set to 2 <N <2 (d + 1) +1 with respect to the output signal from the phase-locked loop unit for generating the recovered clock and the A / D converter (d, k).
It is characterized by having a Viterbi decoding unit for performing Viterbi decoding on a code and a demodulation unit for demodulating an output signal from the Viterbi decoding unit.

Here, the Viterbi decoding unit sets the circuit scale to be equal to or less than the ratio of the number of states generated by the intersymbol interference width N and the number of states due to the constraint of the minimum length d.

[0037]

In the data decoding method according to the present invention, (d, k)
In the data decoding of the code, the Viterbi decoding is performed with the inter-code interference width of 2 <N <2 (d + 1) +1 in the recording / reproducing system or the transmission system in which the code interference to the adjacent code section is allowed, and the constraint length By using the correlation due to the constraint of the constraint length d in consideration of the intersymbol interference width N bits together with a certain d,
When the intersymbol interference width N is N <d + 2, the number of states S when performing Viterbi decoding is S = 2 (d + 1) (1), and the intersymbol interference width N is d + 1 <N <2 (d +
When 1) +1, the number of states S when performing Viterbi decoding is

[0038]

[Equation 1]

Therefore, the number of states is suppressed as compared with the N number of 2 which is the original number of states.

Here, by setting the intersymbol interference width N to be 2 (d + 1), there is no distortion at the conversion point, that is, the zero-cross point, so that the recovered clock component can be easily extracted. Further, the value of the constraint length d is set to 4 to increase the recording density as compared with the conventional data decoding.

Further, in the data decoding device according to the present invention,
The equalizer section waveform-shapes the reproduced signal obtained from the recording medium, and the A / D converter converts the output signal from the equalizer section into a digital signal. The phase locked loop unit generates a reproduction clock based on the output signal output from the equalizer unit, and the reproduction clock is supplied to the Viterbi decoding unit and the demodulation unit. In the Viterbi decoding unit, the inter-code interference width N is 2 <N <2 (d + 1) + with respect to the output signal from the A / D converter.
Viterbi decoding is performed with a (d, k) code of 1. The demodulation section demodulates the decoded data output by the Viterbi decoding section to reproduce information. This minimizes the increase in circuit configuration.

Here, the Viterbi decoding unit simplifies the circuit configuration by setting the circuit scale to be equal to or less than the ratio of the number of states generated by the intersymbol interference width N and the number of states due to the constraint of the minimum length d. .

[0043]

Embodiments of the data decoding method and the data decoding apparatus according to the present invention will be described below with reference to the drawings. In the data decoding method of the present invention, a variable length block code is used and is generally expressed as a (d, k) code. This data decoding method is one of the maximum likelihood decoding methods for decoding data using the (d, k) code, and is applied to the so-called Viterbi decoding method that searches for a probable value by discarding a path that is not possible. An example will be described.

The constraint lengths d and k used in the variable-length block code (d, k) are constraints added to a run that is, for example, a series of "0" of the same symbol. d
In this case, the run length of the same symbol “0” indicates the minimum length, and k indicates the maximum length of the run length of the same symbol “0”. The Viterbi decoding method is used in combination with the partial response method that allows code interference to adjacent code intervals. The partial response method is a method in which recording processing is performed or transmission is performed after performing a conversion process that gives correlation between codes such that an inter-code interference amount with subsequent data is subtracted in advance.
Therefore, the recording / reproducing system or the transmission system is affected by the intersymbol interference.

Further, in order to satisfy the recent technical requirements for high-density recording and the like, it is necessary to increase the intersymbol interference width. However, if the inter-symbol interference width is increased, the number of states dramatically increases, and the circuit scale increases. In order to reduce the circuit scale, a constraint is placed on the constraint length d, but if only the constraint length d is noted, the decoding effect deteriorates. In order to solve such a problem, in the present invention, the intersymbol interference width N bits is larger than 2, and the intersymbol interference width N bits is 2.
The range is smaller than (d + 1) +1, that is, the condition regarding the intersymbol interference width of 2 <N <2 (d + 1) +1 (3) is imposed. Viterbi decoding is performed on the (d, k) code using this condition. The reason for the upper limit of the condition regarding the intersymbol interference width N will be described later.

Here, the constraint length d is set to 4. First, the intersymbol interference width N = 5 bits. d = 4 and N = 5
From the condition that the number of states S is S = 2 (d + 1) (4), it can be seen that the number of states is 10. The state transitions that satisfy this condition are shown in FIG. Specifically, the states under these conditions are S0: 0000, S1: 00001, S2: 00011, S3: 00111, S4: 01111, S5: 11111, S6: 11110, S7: 11100, S8: 11000, S9: 10000, and 10 states from S0 to S9. Become. At this time, as for the state transition, as shown in FIG. 1, only one path enters the states other than the states S0 and S5. If no ordinary restrictions are set, 32 states occur. Restraint length d = 4
By limiting the width of the intersymbol interference width N, the number of states can be reduced from 32 to 10. This significant reduction in the number of states will minimize the scale of the circuit to which this method applies.

A data decoding device satisfying the above conditions will be described with reference to FIGS. For example, as shown in FIG. 2, this data decoding device includes an equalizer unit 1 for waveform equalizing a reproduced signal, and a phase locked loop circuit unit (hereinafter, PLL circuit) for generating a reproduced clock based on an output signal of the equalizer unit 1. 2) and equalizer section 1
A / D converter 3 for converting the output signal of the digital signal into a digital signal
And a Viterbi decoding unit 4 that decodes data based on the output signal of the A / D converter 3, and a demodulation unit 5 that demodulates a signal from the decoded data of the Viterbi decoding unit 4. The Viterbi demodulation unit 4 of this data decoding device is configured with a circuit that embodies the above-described data decoding method.

The equalizer section 1 is composed of, for example, a transversal filter which is a kind of digital filter which has a transfer characteristic of a transmission system. The reproduction signal waveform-equalized by the equalizer 1 is supplied to the PLL circuit 2 and the A / D converter 3, respectively. The PLL circuit 2 generates a reproduction clock serving as a reference clock of the data decoding device from the supplied reproduction signal. This reproduction clock is supplied as an operation clock in the operation of the Viterbi decoding unit 4 and the demodulation unit 5.

The A / D converter 3 A / D converts the supplied reproduction signal and outputs it to the Viterbi decoding unit 4. The Viterbi decoding unit 4 sets the constraint of the constraint length d = 4 and the intersymbol interference width N bits to be larger than 2, and the intersymbol interference width N bits to be 2 (d
Condition (2 <N <2 (d
It is composed of a circuit that satisfies +1) +1). Specifically, regarding the circuit configuration in the case where the constraint length d = 4 and the intersymbol interference width N = 5, and the constraint length d = 4 and the intersymbol interference width N = 10, FIGS. This will be described with reference to FIGS. 6 and 7. The Viterbi decoding unit 4 outputs the same value for all decoded data by selecting a probable path while selecting a surviving path. In this way, the Viterbi decoding unit 4 decodes the most probable decoded data into the demodulation unit 5
Supply to. The demodulation unit 5 outputs a demodulation signal or demodulation information from the decoded data.

Constraint of constraint length d = 4 and intersymbol interference width N = 5
Under the condition of, the Viterbi decoding unit 4 adopts the circuit configuration shown in FIGS. 3 and 4. Here, the symbol A in the figure is a branch metric calculation circuit. An output signal from the A / D converter 3 is supplied to one end of each branch metric calculation circuit. Here, in the drawing, the output signal from the A / D converter 3 is supplied to one end side of each branch metric calculation circuit of the reproduction outputs y _{7 to} y ₉ via the terminal 6.

The survivor path selection circuit shown by the reference symbol B and the state metric calculation circuit shown by the reference symbol C constitute a survivor path selection unit. The state metric output by the survivor path selection unit is output to the normalization unit. The normalization unit is composed of the minimum value detection circuit Min shown in FIG. 4 and the normalization circuit indicated by the symbol D. Here, the output of the minimum value detection circuit Min is also supplied to the respective normalization circuits of the reproduction outputs y _{0 to} y ₆ via the terminal 7.

This normalization unit suppresses the increase in the value due to the accumulation of the past certainty, and uses the minimum value of the metric to make the value of the metric of the relative size meaningful. The normalization unit encodes the value of this relative metric with the code E.
To the state metric memory circuit indicated by. The state metric memory circuit supplies the state metric value in the same state as the number indicating the state of the reproduction output to the wired survivor path selection circuit and one end side of the state metric calculation circuit.

The Viterbi decoding unit 4 is provided with a path memory unit. The path memory unit is composed of a 1-bit register indicated by reference sign F and a 1-bit multiplexer indicated by reference sign G. Data corresponding to the modulated output data X is input to the first 1-bit register. In the 1-bit multiplexer, which of two paths is selected is selected by the output from the surviving path selection circuit.

As shown in the state transition of FIG. 1, the Viterbi decoding unit 4 has only one path, so the state S
It becomes unnecessary to provide the survivor selection circuit and the 1-bit multiplexer of the path memory unit except 0 and the state S5.
As a result, the circuit configuration is minimized by setting the ratio of the number of states 10 with the restriction and the limitation of the intersymbol interference width to the number of states 32 in the normal case without the above-mentioned limitation of 10/32 or less. Therefore, the circuit scale can be suppressed.

Here, the upper limit value of the intersymbol interference width N will be briefly described. The upper limit value of the intersymbol interference width is 2 (d + 1). The upper limit of this intersymbol interference width N is N
When ≦ 2 (d + 1), there is a condition that the conversion point, which is a zero cross point, becomes distortion-free. As a condition that the conversion point becomes distortion-free, a condition that it always passes through the same point is necessary. Actually, the intersymbol interference width N = 4 and N = at the constraint length d = 1
Consider the case of 5. For example, the inter-code interference width N = 4 and the interference coefficient are (1, 2, 2, 1), and the code strings are “000111”, “000110”, and “10011”.
Considering "1" and "100110", the values on the reproduced waveform are "-4, 0, +4," -4, 0, +2 "," -2,
0, +4 "," -2, 0, +2 ". As shown by the value of the reproduced waveform, the midpoints of the three points always cross the same position, that is," 0 ".

However, the intersymbol interference width is N> 2 (d
When it becomes +1), distortion is added to the conversion point. For example, when the code interference width N = 5 with the constraint length d = 1, the interference coefficients are set to (1, 2, 3, 2, 1), and when the same code string as described above is considered, the reproduced waveforms are respectively “−”. 3, +3 ","-
The values are 3, + 1 "," -1, +3 ", and" -1, + 1 ".
In this case, the respective zero cross points are not at the same position and are scattered. In this example, the position of the zero cross from the minus direction to the plus direction is examined, but the position of the zero cross from the opposite plus direction to the minus direction also varies.

Thus, depending on the condition of the intersymbol interference width,
For example, the condition of passing the zero-cross point of the eye pattern is not satisfied and the position of the zero-cross varies. Therefore, it is difficult to extract the clock component by the PLL circuit used in the data decoding device, and the waveform of the reproduced clock or the like is distorted. As a result, the system of the data decoding device becomes unstable, which is not desirable.

Therefore, for example, the upper limit of the intersymbol interference width N when the constraint length d = 4 is N = 10 depending on the condition of 2 (d + 1).

Next, a case where the constraint length d = 4 and the intersymbol interference width N = 10 in this data decoding method will be described. By the condition that d = 4 and N = 10, the number of states S
Is

[0060]

[Equation 2]

Equation (5), expressed as, must be applied. By substituting each numerical value into the equation (5), the number of states S becomes 4
0 is obtained. The state of 40 is as shown below.

[0062]

[Table 1]

As for the state transition in this case, as shown in FIG. 5, for example, the number of states is suppressed to 40 instead of the number of 1024 required in the normal intersymbol interference width N = 10. In addition, the number of states in which two paths may be input is only 12 out of 40 states, 6 states S0 to S5 and 6 states S10 to S15. Since only one path is input in the other states, the path is determined without selecting the surviving path.

Considering the configuration of the Viterbi decoding unit 4 of the data decoding device based on the state transition shown in FIG. 5, the circuit is as follows.
This can be schematically represented by the simplified circuit configurations of FIGS. 6 and 7.

Here, reference numeral (J) shown in FIGS. 6 and 7
Indicates a circuit configuration having a surviving path selection circuit and a 1-bit multiplexer in the path memory unit in the circuit related to the reproduction output y ₀ as shown in FIG. 3, and the symbol (K) is shown in FIG. 3, for example. Play output y
It indicates that the circuit for _one is optionally not circuit configuration and a 1-bit multiplexer in survivor path selection circuit and the path memory unit.

The input signal from the A / D converter 3 shown in FIG. 2 is supplied to one end side of each branch metric calculation circuit indicated by the symbol A. The reproduction outputs y _{0 to} y ₉ , y _{20 to} y ₂₉ , y are provided at the other ends of the branch metric calculation circuits, respectively.
Data is supplied from the states of ₁₀ to y ₁₉ , y ₃₀ to ₃₉ and 40. Of these 40 states, two paths are included, that is, six states S0 to S5 and state S10.
Since the survivor path selection is required only for the six paths up to S15, the survivor path selection circuit indicated by the symbol B is provided. Since only one path is supplied to the states other than this, it is not necessary to perform path selection, and the surviving path selection circuit can be omitted.

Further, in the path memory unit constituted by providing n stages of 1-bit shift registers and 1-bit multiplexers, which are respectively denoted by the symbols F and G, the paths other than the above 12 states are determined. Therefore, the 1-bit multiplexer can be omitted. Therefore, 28 × n 1-bit multiplexers can be omitted, and the circuit configuration can be greatly simplified.

With this configuration, only 12 states are selected in the path memory unit, "0" and "1" are selected, and they are integrated into one in n stages, and the output from the last 1-bit register is obtained. All have the same value. The Viterbi decoding unit 4 selects any one of the outputs b _{n0 to} b _n39 and outputs it as decoded data. If no ordinary constraint is set, 1024 states will occur. By limiting the width of the constraint length d = 4 and the intersymbol interference width N, the number of states is from 1024 to 4
Since the number of states can be reduced to 0 and the number of paths is unified, the number of states is 40 when the constraint and the limitation of the intersymbol interference width are set, and the number of states in the normal case where the above-mentioned limitation is not set is 10
It is possible to minimize the scale of the circuit by setting the ratio to 24 to be 40/1024 or less.

In addition, the constraint length d = 1 and the intersymbol interference width N =
The case of No. 4 will be described with reference to FIGS. The constraint of d = 1 is a constraint that one or more "0" s are always consecutive after the symbol "1". Also in this case, the number of states S is 10 using the equation (5).

Due to this restriction, the states that can be adopted are specifically: S0: 0000 S1: 0001 S2: 0011 S3: 0111 S4: 0110 S5: 1111 S6: 1110 S7: 1100 S8: 1000 S9: 10100. It becomes the state of. Moreover, the state S shown in FIG.
Only one path is included in the four states of 3, S4, S8, and S9. Therefore, in these four states, the survivor selection path circuit for path selection becomes unnecessary.

Further, since the algorithm represented by the state transition shown in FIG. 8 does not have a path due to the constraint of d = 0, for example, the modulated output data “101000” is converted into “a” by the algorithm represented by the state transition shown in FIG. 1100
There is a possibility of avoiding the case of erroneously decoding as "00" and correctly decoding.

The configuration of the Viterbi decoding circuit adapted to the state transition shown in FIG. 8 is shown in FIGS. 9 and 10. In this Viterbi decoding circuit, the number of states is reduced from 16 to 6 and the circuit configuration is simplified. A / D converter 3 on the drawing display
The output signal from the terminal connects FIG. 8 and FIG. 9 via the terminal 8. The output from the minimum value detection circuit Min also connects FIG. 8 and FIG. 9 via the terminal 9.

This Viterbi decoding circuit, as described above,
Reproduction output y because only one path can be entered in one state
_In the circuit for inputting ₃ , y ₄ , y ₈ and y ₉ , the code B
It is possible to omit the survivor path selection circuit and the n 1-bit multiplexers indicated by the reference symbol G in the path memory section. With this configuration, it is possible to reduce the circuit scale by about 40% as compared with the circuit configuration not subject to the constraint length d.

With the above arrangement, the number of states can be significantly suppressed even if the intersymbol interference width N is increased, the required reproduction band can be narrowed, and the recording density can be increased. Further, if the correlation due to the constraint of the constraint length d is also used, the data decoding effect can be further enhanced.
The constraint length d is preferably set to 4, for example. The upper limit of the intersymbol interference width N due to this setting is 2 (d
From the condition of +1), N = 10 is preferable.

By using this method, the survivor path selection circuit and the 1-bit multiplexer of the circuit configuration of the Viterbi decoding unit in the data decoding apparatus can be omitted, and the circuit configuration can be greatly simplified, and the cost can be reduced. be able to.

[0076]

In the data decoding method according to the present invention, in the data decoding of the (d, k) code of the variable length block code, the recording / reproducing system or the transmission system in which the code interference to the adjacent code section is allowed. The intersymbol interference width N is set to 2 <N <2 (d +
1) +1 is performed by Viterbi decoding, and the correlation due to the constraint length d is used in consideration of the constraint length d and the intersymbol interference width N. Can be significantly suppressed, the required reproduction band can be narrowed, and the recording density can be increased.

If the correlation due to the constraint of the constraint length d is also used, the data decoding effect can be further enhanced. The constraint length d is preferably set to 4, for example. The upper limit of the intersymbol interference width N due to this setting is 2 (d
From the condition of +1), N = 10 is preferable.

By using this method, the survivor path selection circuit and the 1-bit multiplexer of the circuit configuration of the Viterbi decoding unit in the data decoding apparatus can be omitted and the circuit configuration can be greatly simplified, and the cost can be reduced. be able to.

[Brief description of drawings]

1 is a data decoding method according to the present invention, d = 4,
It is a figure which shows the state transition in intersymbol interference width N = 5.

FIG. 2 is a schematic block diagram of a data decoding device using the above data decoding method.

FIG. 3 is a main part circuit diagram showing a specific circuit configuration of a Viterbi decoding unit of the data decoding device.

FIG. 4 is a main part circuit diagram showing a specific circuit configuration of a Viterbi decoding unit of the data decoding device.

FIG. 5 is a diagram showing state transitions when d = 4 and an upper limit N = 10 of the intersymbol interference width in the above data decoding method.

FIG. 6 is a schematic diagram of a main circuit showing a simplified circuit configuration of d = 4 and intersymbol interference width N = 10 in the data decoding method.

FIG. 7 is a schematic diagram of a main circuit showing a simplified circuit configuration of d = 4 and intersymbol interference width N = 10 in the data decoding method.

FIG. 8 shows d for Viterbi decoding of the system with the intersymbol interference width N = 4.
It is a figure which shows the state transition at the time of adding the constraint of = 1.

FIG. 9 is a main-portion circuit diagram showing a schematic circuit configuration for specifically realizing the state transition.

FIG. 10 is a main-portion circuit diagram showing a schematic circuit configuration for specifically realizing the state transition.

FIG. 11 is a block diagram showing a schematic system configuration for recording a signal from an information source on a recording medium and reproducing the data from this recording medium by Viterbi decoding.

FIG. 12 is a diagram showing state transition of an inter-code interference 4-bit system for data decoding by the Viterbi decoding.

FIG. 13 is a block diagram showing a schematic circuit configuration for performing the Viterbi decoding.

FIG. 14 is a main part circuit diagram showing a schematic circuit configuration for specifically realizing the state transition of the system with the intersymbol interference width N = 4.

FIG. 15 is a main part circuit diagram showing a schematic circuit configuration for specifically realizing the state transition of the system with the intersymbol interference width N = 4.

FIG. 16 is a main-portion circuit diagram showing a schematic circuit configuration for specifically realizing the state transition of the system with the intersymbol interference width N = 4.

[Explanation of symbols]

 1 Equalizer part 2 PLL circuit part 3 A / D converter 4 Viterbi decoding part 5 Demodulation part 6, 7 terminals A Branch metric calculation circuit B Survival path selection circuit C State metric calculation circuit D Normalization circuit E State metric storage circuit F 1 Bit register G 1-bit multiplexer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H03H 17/00 B 8842-5J C4 H03M 13/12 8730-5J H04L 25/03 C 9199-5K H04N 5/92 7/24

Claims (5)

[Claims] 1. A minimum length of a series of the same symbols is d.
In a data decoding method for decoding data using a (d, k) code in which the maximum length of the same symbol sequence is k, a recording / reproducing system or transmission in which code interference to adjacent code sections is allowed. The intersymbol interference width N in the system is 2 <N <2 (d +
1) A data decoding method characterized in that a (d, k) code of +1 is used and Viterbi decoding is performed on the code. 2. The data decoding method according to claim 1, wherein the intersymbol interference width N is set to 2 (d + 1). 3. The data decoding method according to claim 1, wherein the minimum length d is 4. 4. A data decoding device for modulating data from an information source and decoding data which has been subjected to correlation processing between codes by subtracting inter-code interference generated in the modulated data in advance. Waveform equalizing means for waveform shaping the signal, signal converting means for converting the output signal from the waveform equalizing means into a digital signal, and clock reproducing means for generating a reproduced clock based on the output signal from the waveform equalizing means. Then, the intersymbol interference width N is set in the range of 2 <N <2 (d + 1) +1 for the output signal from the data conversion means (d,
k) A data decoding device having a Viterbi decoding means for performing Viterbi decoding on a code and a demodulation means for demodulating an output signal from the Viterbi decoding means. 5. The Viterbi decoding means sets the circuit scale to be equal to or less than the ratio of the number of states generated by the intersymbol interference width N and the number of states due to the constraint of the minimum length d. Data decoding device.