JPH07226034A - Method for recording information - Google Patents

Abstract

PURPOSE:To shorten length of synchronizing signal and to enhance capacity efficiency of recording medium by making a regenerating synchronizing signal inserted into a recording data line whose increment of channel bit (CB) length after inserting a resynchronizing signal non-integer times the length of a CB equivalent to one byte to the CB length before inserting. CONSTITUTION:A code rule of a (1, 7) code newly proposed as standard of a 130mm rewritable optical disk is used for a modulation system of the recording data. A data bit string before (1, 7) encoding is provided with a resynchronizing part 3 (resynchronizing signal pattern) between a data part 1 and a data part 2. One byte of the (1, 7) code is converted into 12CH bits. The 10 bits data are inserted into the resynch part 3 as the temporary data like (a). When the temporary data are encoded according to the code rule, the data become a 15CH bits pattern. When the pattern (c) after converting is NRZI-converted, the patterns become figures (d) or (e). That is, the increment of the CB length after inserting the resynchronizing signal is made non-integer times the length of the CB of one byte to the CB length before inserting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording method for encoding recording data and recording it on an information recording medium, and more particularly to a method for generating a resynchronization signal pattern inserted in a recording data string.

[0002]

2. Description of the Related Art FIG. 11 is a diagram showing a code rule of a (2,7) code used for 90 mm and 130 mm rewritable optical disks. The resynchronization signal pattern (hereinafter referred to as the RESYNC pattern) used for this (2,7) code is a pattern of 1 byte-16 channel bits of "0010000000100100". This pattern is RES
It has the following four features that are effective as a YNC pattern. (1) A pattern shorter than T _min (3 channel bits) in the (2, 7) coding rule is not used. (2) A pattern that does not appear in the (2, 7) coding rule of FIG. 11 (a pattern of 8 channel bit intervals and immediately following 3 channel bit intervals) is used. (3) This RESYNC pattern is, for example, a 1-byte information word of “7A” in hexadecimal notation and “01111010” in binary notation inserted into an information word string (2,7) and encoded as the 7th of them. It can be obtained by forcibly converting “1” of the th channel bit into “0”. Furthermore,
Decoding this pattern does not affect the decoding of the information words before and after the RESYNC pattern. (4) This RESYNC pattern corresponds to just one byte of information.

Next, FIG. 12 shows a coding rule of a (1,7) code used for a 300 mm write-once type optical disc. In this (1,7) code, the RESYNC pattern is 1
The 1-byte information word "C5" in hexadecimal notation (1,
7) The converted pattern is used. This pattern becomes "x01000001000" when converted to channel bits. x is a bit obtained by inverting the channel bit of the immediately preceding data. The RESYNC pattern of the (1,7) code satisfies the conditions (1), (3), and (4) of the four features described above, but does not satisfy the condition (2).

If the condition (2) is not satisfied, the same pattern as the RESYNC pattern may exist in the data signal sequence, so it is necessary to prevent it from being erroneously detected during reproduction. . Therefore, in order to prevent erroneous detection of other patterns in this way, a narrow RESY
The detection window for the NC pattern must be set up and those that do not fit in that window must be removed. But,
Since the detection window of the RESYNC pattern at the time of such reproduction is created with reference to other synchronization signal detection signals such as the sector mark detection signal or the SYNC detection signal, the recording position on the recording medium shifts back and forth, or the speed variation of the medium. Is large, the correctly detected RESYNC
This causes a problem that the pattern detection signal is out of the detection window. Therefore, in the specifications of the 300 mm write-once optical disc described above, variations in the recording position on the recording medium and fluctuations in the speed of the medium are strictly regulated.

Next, FIG. 13 shows the coding rule of the (1,7) code proposed as a new standard of a new 130 mm rewritable optical disk, and FIG. 14 shows the RESYNC pattern at that time. In the (1,7) coding rule of FIG. 13, 2 bits of the information word are converted into 3 bits. In this conversion, the information word (Input bit) is the preceding 1 channel bit (Preceding Channel bit), and Information word (F
ollowing bit) Determined from 2 channel bits. Also, as shown in FIG. 14, the 2 bytes-24 channel bits of the RESYNC area are 3 channel bits including the channel bit x determined by the information word immediately before that, R channel.
3 including 18 channel bits of the ESYNC pattern and channel bit y determined by the information word immediately following
Made of channel bits.

Further, as shown in FIG. 14, in the RESYNC pattern, RESYNC1 and R whose last bits are 0 and 1 are used.
There is ESYNC2, which suppresses the DC level of the recording signal, and either one is selected and used as described later in detail. The 8-channel bit interval in the RESYNC pattern and the 7-channel bit immediately following it are patterns that do not appear in the (1,7) code of FIG.

In the above RESYNC pattern, code connection channel bits of 3 channel bits are provided before and after the RESYNC pattern. Therefore, when the signals before and after the RESYNC pattern are decoded, the decoding of the information words before and after the RESYNC pattern is not affected. Absent. In this RESYNC pattern, for example, the 2-byte information word "36,5D" in hexadecimal notation is converted into the (1,7) code in FIG. 13, and the 10th channel bit thereof is forcibly set to "0". Further, the 21st channel bit can be obtained by comparing and determining the DSV (Digital Sum Value) of the signals before and after it. However, DS
V indicates an accumulated value within a predetermined section when "1" of the NRZI converted signal is counted as +1 and "0" is counted as -1. Further, this RESYNC pattern satisfies the other items (1) to (3) except that the length of the item (4) is increased from 1 byte to 2 bytes among the above-mentioned four conditions. And satisfies the following fifth condition. (5) It has a function of suppressing the DC level fluctuation of the recording signal.

Here, RESYNC1 and RES in FIG.
The selection algorithm of YNC2 will be described. This is based on the latest standard proposal for a 130 mm rewritable optical disc. The RESYNC pattern is selected according to the following procedure. (a) First, the channel bit data described in PPM is converted into PWM data. The PWM data is obtained by switching the sign at the "1" portion in PPM. For example, if the PPM data is ... 0010100010010 ... And the PWM data is ... 0011000011100. For calculation of DSV, "0" of PWM data is -1, PW
“1” of M data is regarded as +1 and the sum is obtained. FIG. 15 is a diagram showing an example of the calculation. In FIG. 15, PPM data, PWM data, and a disc-shaped mark corresponding to them are shown. DSVm at this time is + 5-4 + 8 when calculating “0” of PWM data as −1 and “1” as +1. -5 ... (b) The RESYNC area has the following 2 of RS and INV.
It can be divided into two parts.

Described as PPM data, RS = 0x010
Described as 000000100000010 PPM data, INV = 000y (INV1) or 100y (INV2) (c) The user data field (the area actually recorded by the user in the recording field) is connected as follows. FIG. 16 shows the format of this user data field. However, m is from 1 to 29.

VFO3‖SYNC‖B0‖RS1‖IN
V1 (orINV2) ‖B1‖RS2‖… ‖INV1
(OrINV2) ‖Bm‖RSm + 1‖… ‖INV1
(OrINV2) || B30 (d) The value of DSV (Z) is the final DSV value of the data string prior to the data string Z, and the data string represented by PPM following that state is PWM. It is the total sum with the DSV value when converted (see FIG. 16). (e) The selection of INV1 and INV2 is performed as follows (see FIG. 16).

P0 ‖ DSV (VFO3 ‖ SYNC ‖ B0 ‖ RS1) Pm = Pm-1 + DSV (INV1 ‖Bm‖RSm +
1) orPm = Pm-1 + DSV (INV2 | Bm | RSm
+1) INV is calculated from these equations so that the value of | Pm | becomes small.
1 or INV2 is selected.

P30 = P29 + DSV (INV1 | B30) or P30 = P29 + DSV (INV2 | B30) Also, INV1 or INV2 is selected from these equations so that the value of | P30 | becomes small. Repeat this procedure from m = 1 to 30 to get RESYNC1 and RES
If | Pm | is equal to YNC2, RESYNC1 is selected.

[0013]

FIG. 17 is a diagram showing an example of a sector format in which the number of user bytes is 512 bytes. Here, the total capacity of one sector is 801 bytes, of which 670 bytes are a data field in which information can be recorded. The above-mentioned RESYNC pattern is inserted in the data field, for example, every 15 bytes of data or every 20 bytes of data. When inserting every 15 bytes of data, a RESYNC pattern is inserted at about 40 places in one sector, and when inserting every 20 bytes of data, a RESYNC pattern is inserted at about 30 places in one sector. Here, if the RESYNC pattern length is 2 bytes, 30-40 bytes per sector is 2 bytes of RE.
The SYNC pattern requires extra. this is,
3.7-5.0% when the entire sector is 801 bytes
The capacity efficiency is reduced. Therefore, from the viewpoint of disk capacity efficiency, the length of the RESYNC pattern is preferably 1 byte rather than 2 bytes.

However, in the (1,7) coding rule of FIG. 13, when the RESYNC pattern is 1 byte,
It is difficult to satisfy the above conditions (1) to (4), and it takes 2 bytes to satisfy these conditions. Therefore, considering the RESYNC pattern as 1 byte, the shortest pattern that satisfies the conditions of (1) and (2) is the 10-channel bit pattern of "1000000001". However, this pattern is 1 byte-1
If the coding rule of FIG. 13 is used, when the data is put into two channel bits, it cannot be stored in twelve channel bits due to restrictions at the front and rear ends. If a hexadecimal expression "C7" is inserted to encode a pattern "010000000010" and this is encoded by (1,7) according to FIG. 13, "01000000001" will be generated by the information word next to RESYNC.
0 is generated, or the pattern becomes “010000000101.” Furthermore, if the pattern “010000000010” is forcibly inserted, the RES will be restored at the time of decoding.
The information word next to the YNC pattern changes to another data. Thus, in the (1,7) coding rule of FIG.
If the length of the SYNC pattern is set to 1 byte, problems such as the data changing to other data at the time of decoding may occur. Therefore, the length of the RESYNC pattern needs to be 2 bytes. Capacity was needed.

The present invention has been made in view of the above conventional problems, and an object thereof is to shorten the length of the resynchronization signal while satisfying all the conditions required for the resynchronization signal. Another object of the present invention is to provide an information recording method for improving the capacity efficiency.

[0016]

An object of the present invention is to record an information recording medium in which a resynchronization signal is regularly inserted in a recording data string and the recording data is modulated into a predetermined recording code and recorded in an information recording medium. In the method, the resynchronization signal has a length which is not an integral multiple of the channel bit length corresponding to 1 byte with respect to the channel bit length before insertion of the resynchronization signal. This is achieved by a characteristic information recording method.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram for explaining an embodiment of the information recording method of the present invention. In the following description, it is assumed that the (1,7) coding rule in FIG. 13 is used as the recording data modulation method. FIG. 1A shows a bit string of data before (1,7) encoding, and its data part 1
The resync unit 3 (resynchronization signal pattern) is provided between the data unit 2 and the data unit 2. One byte (8 bits) of the (1,7) code is converted into 12 channel bits. This (1,
7) Prior to encoding, the resync unit 3 is configured as shown in FIG.
As shown in (a), 10-bit data "1100011100" is inserted as resync temporary data. Conventionally, the length of the resync unit 3 is 1 byte or 2 bytes, but here, the length of the resync unit 3 is 1.25 bytes (10 bits).

This is (1,7) according to the code rule of FIG.
When encoded, as shown in FIG. 1 (b), "010001000010"
This is a pattern of 15 channel bits of 00x ". However, x has a different value depending on the data section 2 following it. Next, the" 1 "of the 6th channel bit of the pattern of the resync section 3 of FIG. It is forcibly replaced with “0.” This is to make nine identical codes continuous so as to form a pattern that does not appear in the (1,7) coding rule, and thus, the above-mentioned item (2) is used. A resync pattern is created so as to satisfy the condition of 1. Moreover, "0" of the 13th bit is replaced with "Z", where "Z" is D.
It is a bit for suppressing the C level fluctuation, and is set to the smaller DC level fluctuation by comparing the DSV of the NRZI signal before “Z” with the DSV of the NRZI signal of the block following “Z”. The detailed algorithm is as described above.

FIG. 1C is a diagram showing the pattern of the resync unit 3 after the conversion as described above.
When converted, the pattern becomes as shown in FIG. 1D or 1E. However, it is assumed here that the last bit of the data part 1 is “0”, and if the data part 1
If the last bit of "1" is "1",
In the pattern (e), "1" and "0" are opposite patterns. In this way, the resync pattern is regularly inserted, for example, in every 15 bytes or 20 bytes of data, and after being modulated into a predetermined recording code, it is recorded in the recording medium.

Here, the resync pattern described with reference to FIG. 1 includes a portion in which nine identical codes are continuous, that is, a mark or space having a period of 9t, which is a pattern that does not appear in the (1,7) coding rule. is there. That is, this resync pattern satisfies the condition (2) described above. Also,
A pattern shorter than T _min (2 channel bits) of the (1,7) coding rule is not used, and the above condition (1) is satisfied. Furthermore, when the channel bits of the resync pattern of FIG. 1 are decoded according to FIG. 13, the data of the data part 1 and the data part 2 do not change to different data as will be described later in detail. Satisfy the condition of. Of course, since it also has the function of suppressing the DC level fluctuation of the recording signal, the above condition (5) is also satisfied.

As described above, the resync pattern shown in FIG.
The pattern has the shortest length to satisfy the conditions (1), (2), (3), and (5), and it is difficult to satisfy the above conditions with a resync pattern shorter than this.
Therefore, the resync pattern used in this embodiment is not 1 byte in the above item (4), but is shorter than 2 bytes, and the minimum length required while satisfying all the conditions other than the item (4). (1.25 bytes).

Next, a specific example of an information recording apparatus for recording information using the above resync pattern will be described with reference to FIGS. 2 is a block diagram showing an example of the information recording apparatus, and FIG. 3 is a time chart showing its operation. First, 10 in the figure is a buffer memory for temporarily storing the recording data S1 sent from an external host computer (not shown). Normally, the print data S1 is sent as parallel data, and is parallel / serial converted by the buffer memory 10 to be output as serial data S2. FIG. 3A shows recording data S1 input to the buffer memory 10, and FIG. 3B shows serial data S2 which is parallel / serial converted in the buffer memory 10.

The bit counter 11 counts the clock of a constant frequency sent from the outside, and the count value is sent to the resync switching signal generating circuit 12. The resync switching signal generation circuit 12 generates a resync switching signal S4 as shown in FIG. 3D based on the count value of the clock and outputs it to the buffer memory 10 and the selector 13. As shown in FIG. 3D, the resync switching signal S4 is generated so as to have a low level for the length of the data block and a high level for the length of the resync pattern. Here, 1.
Since a 25-byte resync pattern is inserted, the 120-clock period corresponding to 15 bytes of the data block is at the low level, and the 10-clock period corresponding to 1.5 bytes of the resync pattern is at the high level.

In the buffer memory 10, the serial data S2 is output to the selector 13 as shown in FIG. 3B while the resync switching signal S4 is at the low level. On the other hand, the resync temporary data generation circuit 14 generates resync temporary data S3 as shown in FIG. Here, as the resync tentative data S3, 10-bit resync tentative data "1100011100" is generated as described in FIG. 1, and this is serially output to the selector 13. In the selector 13, the serial data S2 from the buffer memory 10 is selected while the resync switching signal S4 is at the low level, and the resync temporary data S3 is selected while the resync switching signal S4 is at the high level. Thus, in the selector 13, resync temporary data is inserted into the data string for each predetermined byte of data as shown in FIG. 3E, and is output to the encoder 15 as serial data S5 including the resync pattern.

In the encoder 15, the serial data S5 is (1,7) encoded, and the resync sixth bit operating circuit 1
6 is output. When the resync temporary data S3 is (1,7) encoded, it has a pattern of 15 channel bits as shown in FIG. In the resync sixth bit operation circuit 16, the sixth bit of the (1,7) -coded resync pattern is forcibly changed from "1" to "0" as described in FIG. The serial data is output to the buffer memory 17 and the NRZI conversion circuit 18, respectively. In the NRZI conversion circuit 18, the input data is N
NR converted to RZI and shown in FIGS. 1 (d) and 1 (e)
Converted to ZI signal. In the DSV measurement determination circuit 19,
The 13th bit (Z) of the resync pattern of FIG. 1B is set to "0" and "1" by the above-mentioned algorithm.
It is determined which of the two is to be used. That is, it is determined whether the smaller DC variation of the recording signal is “0” or “1”, and the DSV measurement determination signal S6 (FIG. 3 (f)) indicating the determination result is the resync thirteenth. Bit setting circuit 2
Sent to 0.

Here, when the DSV is measured and determined, the DSV of the block in the period up to the next Z must be determined with respect to the "Z" of the resync pattern.
In order to insert the flag Z into the determination result of the DSV measurement determination signal S6, that is, the 13th bit of the resync pattern, it is necessary to delay the encoded data by the interval of the flag Z. Therefore, the encoded data is temporarily stored in the buffer memory 17, during which the DSV measurement determination circuit 19 operates the flag Z of the 13th bit as described above.
It is determined whether "0" or "1" is set.
Therefore, the encoded data S7 from the buffer memory 17 is output with a delay of one block of data as shown in FIG. 3 (g), and by shifting the timing in this way, the resync thirteenth bit setting circuit 20 outputs the DSV measurement determination signal S6. Based on the above, the flag Z of the 13th bit of the resync pattern is set.

The output data of the resync thirteenth bit setting circuit 20 is converted into an NRZI signal by the NRZI converting circuit 21 and then sent to the buffer memory 22. On the other hand, the recording timing signal generation circuit 23 generates a trigger signal for indicating an accurate recording start position on the recording medium 25,
It is output to the buffer memory 22. This trigger signal is created based on the sector mark detection signal, and the recording signal S8 of the buffer memory 22 shown in FIG. 3 (h) is output to the recording means 24 at the output timing of the trigger signal. And
The recording signal S8 is recorded on the recording medium 25 by the recording means 24.

Next, a specific example of the information reproducing apparatus for reproducing the information recorded on the recording medium by using the resync pattern shown in FIG. 1 will be described with reference to FIGS. 4 and 5. FIG. 4 is a block diagram showing an example of the information reproducing apparatus, and FIG. 5 is a time chart showing its operation. First, on the information recording medium 25, the resync pattern described with reference to FIG. 1 is regularly inserted and recorded for each predetermined byte of data. The data including the resync pattern of the recording medium 25 is reproduced by the reproducing means 30.
The reproduced signal obtained by the reproduction is binarized by the binarization circuit 31. The binarized signal obtained by the binarization circuit 31 is sent to the data separator 32, and is separated into a synchronization clock and data S9 synchronized with it. FIG. 5A shows the data S9 thus obtained by the data separator 22.

On the other hand, the binarized signal of the binarization circuit 31 is sent to the sector mark detection circuit 33, and the sector mark detection circuit 33 detects the sector mark of the recording medium 25 from the binarized signal. That is, the information track of the recording medium 25 is divided into a plurality of sectors, and a sector mark is added to the beginning of each sector.
In 3, the sector mark of each sector is detected and is output to the sync detection circuit 34 as a sector mark detection signal. In the sync detection circuit 34, the sector mark detection signal and the data S9 of the data separator 32 are referred to in FIG.
A sync detection signal S10 as shown in (b) is generated,
It is output to the delay 35. The delay 35 is shown in FIG.
As shown in (c), the sync detection signal S10 is delayed by a certain time to output a signal S11, which is output to the decoder 37, the resync window generation circuit 39, and the resync interpolation circuit 40 via the OR circuit 36, respectively. It FIG. 5D shows the output signal S1 of the OR circuit 36.
It is 2.

In the OR circuit 36, the signal S1 of the delay 35
The signal S12 is output by taking the logical sum of 1 and the output signal of the selector 44 described later. The signal S11 from the delay 35 is sent to the decoder 37 via the OR circuit 36 as a signal indicating the beginning of the data. In this case, the data S9 sent from the data separator 32 to the decoder 37
Is delayed by a delay 41 for a certain period of time in order to cancel the delay of the resync detection signal 12 with respect to the data S9 of the data separator 32. Similarly,
A delay 35 cancels the delay of the resync detection signal S18 from the selector 44 with respect to the sync detection signal S10 of the sync detection circuit 34. Thus decoder 3
In FIG. 7, when the signal S12 is output from the OR circuit 12, the signal S12 is set as the start time point and the (1,7)
Decryption is started.

On the other hand, the data S9 of the data separator 32
Is sent to the resync detection circuit 38, and the resync detection circuit 3
8, the data S9 is pattern-matched to detect the resync pattern. When the resync pattern is detected, the resync detection signal S13 is output as shown in FIG. 5 (e). Here, when the recorded information on the recording medium 25 is reproduced, it is assumed that the resync 2 and the data 3 portions of the data S9 of the data separator 32 have signal defects due to medium defects as shown in FIG. 5A. . As a result, in the resync detection circuit 38, as shown in FIG.
No resync pattern is detected, and the pseudo resync detection signal W is output although the data 3 is not the original resync pattern. The resync detection signal S13 is delayed by the delay 42 for a certain period of time, as shown in FIG.
As shown in, the signal S16 is output to the selector 44. The delay 42 is for waiting for the determination of the resync presence / absence determination circuit 43.

In the resync interpolation circuit 40, the position where the next resync detection signal should be is predicted with reference to the output signal S12 of the OR circuit 36, and as shown in FIG. A pulse signal S15 similar to the delayed signal S16) is generated, and this is output to the selector 44 as a resync interpolation signal. In the resync detection window generation circuit 39, the output signal S12 of the OR circuit 36 is used as a reference in FIG.
As shown in (f), the window pulse signal S14 for detecting the next resync pattern is generated and output to the resync presence / absence determination circuit 43. Resync presence / absence determination circuit 4
Reference numeral 3 denotes a circuit for determining whether or not the resync detection signal S13 of FIG. 5 (e) exists in the window (high level period) of the window pulse signal S14 of FIG. 5 (f).
If the resync detection signal S13 exists in the window, a high level signal S17 indicating the existence of the resync detection signal is output to the selector 44 as shown in FIG. Is output to. In this way, the resync presence / absence determination circuit 43 determines the presence / absence of a resync detection signal in the window, and the selector 4
In 4, the output signal of the delay 42 or the output signal of the resync interpolation circuit 40 is selected based on the determination result.

Here, since there is no medium defect in the resync 1 of FIG. 5A and the resync pattern is normally detected as shown in FIG. 5E, the resync detection signal is shown in FIG.
It exists in the window of the resync detection window generation circuit 39 of (f). Therefore, at this time, the resync presence / absence determination circuit 43 determines that the resync detection signal is present in the window, and the resync determination signal S17 of a pulse having a predetermined width is output to the selector 44 as shown in FIG. When the selector 44 normally detects the resync pattern in this manner, the signal S16 (FIG. 5 (h)) on the delay 42 side, that is, the resync detection circuit 38 detects the pattern by pattern matching as shown in FIG. 5 (j). The selected resync detection signal is selected and output to the decoder 37 via the OR circuit 36.

Next, since the resync 2 of FIG. 5A has a medium defect and the resync detection circuit 38 cannot detect the resync pattern as shown in FIG. 5E, the resync detection is performed as shown in FIG. 5F. There is no resync detection signal in the window. In this case, the resync existence determination circuit 43
Then, it is determined that there is no resync detection signal in the window, and a low-level determination signal is output as shown in FIG. When the selector 44 cannot detect the resync pattern in this way, the interpolation signal S15 generated by the resync interpolation circuit 40 of FIG. 5G is selected and output to the decoder 37. Furthermore, the data 3 in FIG.
Due to the defect of the resync detecting circuit 38 as shown in FIG.
When the pseudo resync detection signal W is output from the above, the pseudo resync detection signal W does not exist in the resync detection window, and therefore the resync presence / absence determination circuit 43 determines that there is no resync detection signal, and FIG. ), The determination signal remains low level.

Therefore, when the pseudo resync detection signal is generated due to the defect in the data portion in this way, the resync presence / absence determination circuit 43 determines that there is no resync detection signal, and thus the selector 44 is used as shown in FIG. 5 (j). The pseudo resync detection signal is not selected and is not output to the decoder 37. In this way, the selector 44 selects either the resync detection signal S16 of the delay 42 or the interpolation signal S15 of the resync interpolation circuit 40 based on the determination result of the resync presence / absence determination circuit 43, and sends it to the decoder 37 via the OR circuit 36. Then, in the decoder 37, every time the resync detection signal is sent from the selector 44 through the OR circuit 36, the data block is decoded with the resync detection signal as a start point, and as shown in FIGS. Reproduction data S19 and a synchronization clock S synchronized with it
20 is generated.

As described above, in this embodiment, as a necessary condition for the resync pattern, a pattern shorter than T _min in the (1) (1, 7) coding rule is not used. (2) The code rule uses a pattern that does not appear. (3) It does not hinder the decoding of the information words before and after the resync pattern when it is decoded. (5) It has a function of suppressing the DC level fluctuation of the recording signal. The resync pattern of the condition (4) above is not 1 byte long, but can be shorter than 2 bytes. That is, while satisfying the resync pattern requirement, (1, 7)
The length of the resync pattern can be made shorter than 2 bytes by making it a length that is not an integral multiple of 1 byte, which was not considered in the past, though it is not 1 byte that was difficult to realize with the coding rule. This can increase the capacity efficiency of the recording medium.

That is, in the past, in the information recording / reproducing apparatus, it was considered that the structure would be complicated unless the data was handled in byte units, and it was actually difficult to design the apparatus. However, in this embodiment, even if the resync pattern has a length of 1.25 bytes, there is no problem in function or design of the device, and recording / reproducing of information is performed. Proved that is possible.

Next, the effect of improving the capacity efficiency of a specific recording medium will be described. Conventionally, two bytes are required for one resync pattern, but only 1.25 bytes are needed in this embodiment, so there is a reduction effect of 0.75 bytes for one resync pattern. Therefore, assuming that the capacity of the entire sector is, for example, 800 bytes and the number of resync patterns is 39 in one sector, the capacity can be reduced by 30 bytes in one sector, resulting in an improvement in capacity efficiency of about 3.75%. To improve the capacity efficiency, the capacity of the recording medium may be increased by 3.75% as it is by changing the sector arrangement of the recording medium and increasing the number of sectors.
By increasing the recording pit length on the recording medium without changing the sector arrangement, it is possible to increase the reliability of recording and reproduction while maintaining the capacity of the recording medium.

Here, in the embodiment, it was explained that even if the resync pattern of FIG. 1 is decoded according to FIG. 13 as described above, the data part 1 and the data part 2 do not change to different data. Will be described in detail. FIG. 6 is a diagram showing the inverse transformation of the (1,7) coding rule shown in FIG. In the resync pattern of FIG. 1B, the code 6 channel bits after the data part 1 is converted from “0” to “1”. However, according to the inverse conversion rule of FIG. It is used up to 2 channel bits behind the data part 1. Therefore, when decoding, the data part 1
Does not change to different data. Also, FIG.
In FIG. 6B, the code 3 channel bits before the data part 2 is manipulated, but according to FIG. 6, the data part 2 is used for decoding only 2 channel bits before the data part 2. The data section 2 does not change to different data at the time of decoding. As described above, in the embodiment, the data part 1 and the data part 2 do not change to different data at the time of decoding, and the condition of the above-mentioned item (3) is satisfied.

Next, another embodiment of the present invention will be described. First, in the embodiment of FIG. 1, (1),
An example of a resync pattern having the shortest length of 1.25 bytes is shown as the resync pattern satisfying the conditions of (2), (3), and (5), but this is not necessarily the shortest. For example, the length may be 1.5 bytes. FIG. 7 shows the case of using the (1,7) code shown in FIG.
It is the figure which showed the example of the 5-byte resync pattern. Here, examples of 12 resync patterns shown in FIGS. 7A to 7L are shown. For example, in FIG. 7A, “0x” is shown.
An example of a pattern of "010000000010Z00x" is shown. Each of these resync patterns is regularly inserted as resync tentative data in the recording data string, and then (1, 7) encoded to generate 18 as in FIG. This is a pattern when converted into a channel bit pattern, and the predetermined bit "1" is replaced with "0" and the predetermined bit is replaced with "Z". , The capacity efficiency of the recording medium is reduced as much as the length of the recording medium is longer than that of 1.25 bytes, but there is an advantage that the occurrence rate of erroneous detection of the resync pattern can be reduced.

FIG. 8 is a diagram showing another example of the resync pattern when the (1, 7) code of FIG. 12 is used. Here, as the resync temporary data of the resync unit 3 to be input to the decoder, 1.25-byte temporary data "1100101110" is used as shown in FIG. 8A. When this is encoded according to the (1,7) coding rule of FIG.
It becomes a pattern of 15 channel bits like (b),
The 10th bit "1" of this pattern is set to "0"
When the 4-channel bit "1" is converted into "Z", the resync pattern shown in FIG. 8C is obtained. Then, the resync pattern of FIG. 8C is converted into an NRZI signal, and if the leading bit is “0”, the pattern of FIG. 8D or 8E is obtained. Also in this embodiment, the resync pattern is not the one byte of the condition of the item (4), but has the shortest length (1.25) that satisfies all the conditions other than the item (4).

In the above embodiments, the case where the (1,7) code is used has been described, but the present invention uses other RLLs.
It can also be used for codes. FIG. 9 is a diagram showing an embodiment in the case where the (2,7) code in FIG. 11 is used. When the (2, 7) code in FIG. 11 is used, the resync pattern of just 1 byte of the 16-channel clock "0010000000100100" is usually used as described above. On the other hand, in the present embodiment, as shown in FIG. 9C, 14 channel bits “00100000000100”, 0.
An 875-byte resync pattern can be used. This resync pattern is "0110010" in FIG. 9 (a).
7-bit resync temporary data of (2, 7) is encoded and converted into a 14-channel bit pattern "00100000100100" as shown in FIG. 9B, and the 9th bit "1" is "0". Can be obtained by converting to. Furthermore, when the resync pattern shown in FIG. 9C is converted into an NRZI signal, the pattern shown in FIG. 9D is obtained.
As described above, in this embodiment, the resync pattern satisfies the above-described conditions (1), (2), and (3), and one resync pattern shortens the length by 0.125 bytes. The capacity of the recording medium can be increased.

Next, an embodiment which satisfies the conditions (1), (2), (3), and (5) when the (2, 7) code in FIG. 11 is used will be described with reference to FIG. To do. FIG. 10A shows resync tentative data, and 9-bit tentative data of "011011011" is used. When this is (2,7) encoded according to FIG. 11, “0010” is obtained as shown in FIG.
A pattern of 18 channel bits of 00001000001000 "is obtained. When the 9th bit" 1 "of this pattern is converted to" 0 "and the 12th bit" 0 "is converted to" Z ", respectively, the pattern of FIG. Like “00100000000Z00100
This is an 18-channel bit resync pattern of "0". Also, the resync pattern of FIG.
When converted into a signal, a pattern as shown in FIG. 10D or 10E is obtained. Here, in 1 byte-16 channel bits, the above (1), (2), (3), (5)
Although the above conditions cannot be satisfied at the same time, in the present embodiment, one byte-18 channel bits are satisfied, so all of these conditions are satisfied.

In the above embodiments, an example in which the present invention is applied to an information recording / reproducing apparatus has been described, but since the present invention is basically a signal transmission technique, it can be applied to an information communication apparatus or the like. Is possible. Further, in the above embodiment, the (1,7) code, (2,
7) Although the code is taken as an example, the present invention can be used for other RLL codes or other recording codes such as 8-9, 8-10 conversion block codes.

[0045]

As described above, according to the present invention, the increment of the channel bit length after the insertion of the resynchronization signal to be inserted into the recording data string is 1 byte with respect to the channel bit length before the insertion of the resynchronization signal. The length of the resynchronization signal can be set to 2 bytes or less by setting the length to a value that is not an integral multiple of the corresponding channel bit, and the capacity of the recording medium can be achieved while satisfying the conditions required for the resynchronization signal. There is an effect that efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an information recording method of the present invention.

FIG. 2 is a block diagram showing a specific example of an information recording device used in the information recording method of the present invention.

FIG. 3 is a time chart showing the operation of the information recording device of FIG.

FIG. 4 is a block diagram showing a specific example of an information reproducing apparatus for reproducing information recorded by the information recording method of the present invention.

5 is a time chart showing the operation of the information reproducing apparatus of FIG.

FIG. 6 is a diagram showing inverse conversion of the (1,7) coding rule of FIG.

FIG. 7 is a diagram showing an example of a resync pattern when the length of the resync pattern is 1.5 bytes.

8 is a diagram showing an example of a resync pattern when the (1,7) code in FIG. 12 is used.

9 is a diagram showing an example of a resync pattern when the (1,7) code in FIG. 11 is used.

FIG. 10 is a diagram showing another example of the resync pattern when the (1,7) code in FIG. 11 is used.

FIG. 11 is a diagram showing a code rule of a (2,7) code used for 90 mm and 130 mm rewritable optical disks.

FIG. 12 is a diagram showing a code rule of a (1,7) code used for a 300 mm write-once optical disc.

FIG. 13 is a diagram showing a code rule of a (1,7) code proposed as a standard standard for a new 130 mm rewritable optical disc.

14 is a diagram showing a resync pattern corresponding to the (1,7) code in FIG.

FIG. 15 is a diagram for explaining calculation of DSV.

FIG. 16 is a diagram showing a format of a user data field of an optical disc.

FIG. 17 is a diagram showing an example of a sector format of an optical disc.

[Explanation of symbols]

 1, 2 Data part 3 Resync part 10, 17, 22 Buffer memory 12 Resync switching signal generation circuit 13 Selector 14 Resync temporary data generation circuit 15 Encoder 16 Resync 6th bit operation circuit 18, 21 NRZI conversion circuit 19 DSV measurement determination circuit 20 Resync 13th bit setting circuit 24 Recording means 25 Recording medium 30 Playback means 31 Binarization circuit 32 Data separator 34 Sync detection circuit 37 Decoder 38 Resync detection circuit 39 Resync detection window generation circuit 40 Resync interpolation circuit 43 Resync presence / absence determination circuit 44 Selector

Claims (3)

[Claims] 1. An information recording method for regularly inserting a resynchronization signal into a recording data string, modulating the recording data into a predetermined recording code, and recording the information on an information recording medium. An information recording method characterized in that the increment of the channel bit length after the insertion of the resynchronization signal is not an integral multiple of the channel bit length corresponding to 1 byte with respect to the channel bit length before the insertion. 2. The resynchronization signal uses a pattern that is not shorter than the minimum inversion interval of the modulation rule of the recording code, and includes a pattern that does not appear in the modulation rule of the recording code. 2. The information recording method according to claim 1, wherein the increment of the channel bit length after insertion is the minimum with respect to the previous channel bit length. 3. The resynchronization signal uses a pattern that is not shorter than the minimum inversion interval of the modulation rule of the recording code, and includes a pattern that does not appear in the modulation rule of the recording code, and suppresses DC level fluctuation of the recording signal. The information recording method according to claim 1, wherein the increase in the channel bit length after the insertion of the resynchronization signal is minimum with respect to the channel bit length before the insertion of the resynchronization signal.