JPH07221187A - Automatic arrangement wiring method of integrated circuit and integrated circuit made using the same - Google Patents

Abstract

PURPOSE:To confirm the operation in the actual circuit after correction by a method wherein a layout automatically arranging spare circuit elements is made in a circuit element not yet formed region using the circuit element layout data, reserve circuit data and the circuit element arrangement requirement data. CONSTITUTION:The region meeting the arrangement requirements of defective logic relieving cells according to the data on previously inputted arrangement requirements is decided by computation out of the circuit element not yet formed regions decised by layout data. The defective logic relieving cells are to be arranged after the decision of the arrangement position thereof. As the results of the arrangement decision, a new layout wherein the defective logic relieving cells 92, 94, 96 and 98 are respectively arranged in the feedthrough cells 32, 34, 36 and 38 in the layout is to be made. Through these procedures, the term, labor and material cost required for the development of integrated circuit can be notably cut down.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit automatic placement and routing method for creating a layout on an actual integrated circuit from a circuit diagram created by a CAD device or the like, and an integrated circuit created by this method. is there.

[0002]

2. Description of the Related Art When a logic circuit is created by a CAD device or the like, even if the size of each circuit element (cell) on the circuit diagram of the logic circuit is almost the same, the type of cell actually formed on the silicon substrate is different. The required area varies greatly depending on the type.
Also, in the actual circuit, each element must be arranged so that the wiring layers do not short-circuit with each other even in the portion where the conducting wires intersect on the circuit diagram. Therefore, in order to integrate many elements in a small area, the layout of how to arrange each element is important. Particularly, in recent years, as the scale of LSI has increased and the number of cells used has increased, the need for efficient layout has increased.

The automatic placement and routing tool automatically creates a layout when a logic circuit created on a computer screen using a CAD device is formed on an actual silicon substrate. By using such a tool, the period required for layout design is shortened. Further, such a layout satisfies a rule (design rule) in which a technical constraint on LSI design is a LIS design condition, and therefore verification in the layout design is unnecessary,
The time required for LSI design can be shortened, and the design cost can be greatly reduced accordingly.

By the way, even if the circuit is designed by a CAD device and the operation of the logic circuit is confirmed by a simulator, various defects are found at the stage of actually prototyping the integrated circuit according to the layout created by the automatic placement and routing tool. It may be done. In such a case, a measure is taken to identify the defective portion and how to correct it. Also, if the countermeasure (correction circuit) is incorrect, time and cost will be seriously damaged. Therefore, not only check the operation of the correction circuit with a simulator, but also use a prototype circuit that is actually corrected and reassembled. You need to confirm that it works properly. Conventionally, when manufacturing a modified prototype circuit, the layout was recreated by returning to the stage of the automatic placement and routing tool, and a new prototype circuit was created based on this layout.

[0005]

However, since it takes about 1 to 2 months to prototype an integrated circuit, the final product release may be delayed if the integrated circuit is prototyped again, and the target time for product release may be missed. There is In addition, even at the prototype stage, several tens of wafers each having a chip mounted thereon must be manufactured in units of several tens of wafers. Therefore, repeated prototypes increase material costs and personnel costs, resulting in product costs. Leading to a rise in.

The present invention has been made based on the above circumstances, and when a defect is found in a prototyped integrated circuit, the operation can be easily confirmed in a corrected actual circuit in a short period of time. An object of the present invention is to provide an automatic circuit placement and routing method and an integrated circuit produced by using this method.

[0007]

In order to solve the above-mentioned problems, an automatic placement and routing method according to a first aspect of the present invention is directed to a first data relating to the layout of circuit elements created from a circuit diagram and the layout Using the second data on the spare circuit element to be arranged in the circuit element non-fabrication area and the third data on the condition of what kind of circuit element is to be arranged in the circuit element non-fabrication area, It is characterized by automatically creating a layout in which spare circuit elements are arranged in the manufacturing area.

According to a second aspect of the present invention, there is provided an automatic placement and routing method according to the first aspect, wherein the circuit element non-fabrication region is a region where a feedthrough cell is formed or a power supply line is formed. It is characterized by that.

According to a third aspect of the present invention, there is provided an integrated circuit, wherein the spare circuit element is provided in the circuit element non-fabrication area based on a layout created by the integrated circuit automatic placement and routing method according to the first or second aspect. Is formed.

[0010]

According to the first aspect of the present invention, the integrated circuit generally has a circuit element non-fabrication region in which cells are not arranged in the layout, no matter how efficiently the cells are arranged. . When a layout is automatically created from a circuit diagram created by a CAD device using an automatic placement and routing tool, data regarding the layout of circuit elements is stored inside the computer. This data naturally includes the first data on the circuit element non-fabricated region, and it is possible to know where in the layout the circuit element non-fabricated region exists from this data.

The circuit element non-fabrication area includes, for example, an area on which wiring for electrically connecting cells and a power supply wiring are formed. For this reason, some circuit elements cannot be formed as spare circuit elements in such regions. Therefore, from the second data, it is possible to know where and what kind of circuit element can be arranged as a spare circuit element in the circuit element non-fabrication area.

Further, when there are a plurality of spare circuit elements that can be arranged in the circuit element non-fabrication area, there is the most suitable spare circuit element to be arranged at that position. By inputting the third data, the spare circuit element most suitable for the area can be selected.

From the above first, second and third data, it is determined which circuit element non-fabrication area and what spare circuit element is to be arranged, and a new layout is created based on this.

According to a second aspect of the present invention, by the above configuration,
Generally, since the original circuit elements are not formed in the area where the feedthrough cells are formed or the area where the power supply wiring is formed, these areas can be used as circuit element non-fabrication areas for forming spare circuit elements.

According to a third aspect of the present invention, by the above configuration,
When an integrated circuit manufactured based on the new layout created as described above contains spare circuit elements suitable for that area in the circuit element non-fabrication area, and a defect is found in the circuit operation. In addition, there is a high possibility that the operation can be confirmed in the state where the circuit configuration is actually corrected by the spare circuit element arranged in the circuit element non-fabrication region.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing steps of an automatic placement and routing method for an integrated circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a part of the layout of the integrated circuit created by the automatic placement and routing tool, and FIG. 3 is a logic diagram. A circuit diagram of a part of an integrated circuit including a defect relief cell, FIG. 4 is a circuit diagram showing a state in which a part of the wiring of the circuit shown in FIG. 3 is corrected by the logic defect relief cell, and FIG. 5 is a logic defect relief. FIG. 6 is a cross-sectional view of an example integrated circuit including a memory cell, and FIG. 6 is a diagram showing a part of a new layout created by arranging logic defect relief cells in feedthrough cells based on the layout of FIG.

An automatic placement and routing method for an integrated circuit according to an embodiment of the present invention comprises the steps shown in the flow chart of FIG. In the figure, in step S1, the layout data created by the automatic placement and routing tool is read, in step S2, the data relating to the logical defect relief cell which is a spare circuit element is input, and in step S3, the placement of the logical defect relief cell is performed. Enter the condition. And step S4
Then, an area where cells are not formed (circuit element non-fabricated area) is calculated from the layout data, and an area conforming to the placement condition of the logic defect relief cell is calculated from the data input above in step S5. Further, the logic defect relief cells are arranged in a predetermined area in step S6, and a new layout in which the logic defect relief cells are arranged is created in step S7 and the data is output.

In the layout of the integrated circuit created by the automatic placement and routing tool shown in FIG. 2, the power supply line (Vd
d) 20 is arranged on the left side, and the ground line (GND) 22 is arranged on the right side. No circuit element is formed in the lower layer of these power supply wirings, which is a circuit element non-production area. Between the power supply line 20 and the ground line 22, there are three rows of regions 24, 26 and 28, which are divided into smaller regions, and each divided region is a cell. These cells include feedthrough cells 32, 34, 36, 38, 40 and other normal cells, and circuit elements such as transistors are formed in the normal cells. Wiring 42, 44, 46, 48, 50
Electrically connect ordinary cells to each other.

Feedthrough cells 32, 34, 36, 3
Reference numerals 8 and 40 are also circuit element non-fabrication areas, and circuit elements such as transistors are not manufactured. Of these, the feedthrough cell 36 is a cell for passing a signal wire connecting the cells of the regions 24 and 28 in the y direction. When the signal wiring is formed on a normal cell, the element of the cell and the signal wiring are short-circuited, and therefore such a cell is required when passing the signal line through the cell region. Further, the feedthrough cell 34 is a cell for adjusting the length of the column 26 in the x direction for power supply wiring. As described above, the feedthrough cell is a cell required when actually laying out each element and wiring of the circuit diagram produced by the CAD device on the integrated circuit, and the automatic placement and routing tool includes these feedthrough cells. The actual layout is determined in the form.

Next, the necessity of the logic defect relief cell will be described. Create a circuit diagram of an integrated circuit with a CAD device,
Even when the circuit operation is confirmed by a simulator, a defect may occur when an integrated circuit is actually prototyped based on the circuit diagram. At that time, even if it is theoretically understood how to correct the problem, it is necessary to confirm with the actual wiring that the modification works properly. If the correction is incorrect or another defect is found, and if such a defect is discovered after moving to the manufacturing stage of the product, time, material,
This is because the labor loss will be enormous.

In such a case, if an appropriate logic defect relief cell for relieving a logic defect is prepared as a spare in a circuit element non-fabrication region, even if a defect is found at the stage of trial manufacture, either It is possible to correct the circuit connection again by using the logic defect relief cell and confirm whether or not it operates properly.
For example, as shown in FIG. 3, it is assumed that there is an integrated circuit in which the inverter 82 is preliminarily formed as a logic defect relief cell. To the left and right of this inverter 82, the originally used AND
There are gates 80 and 82, and the output of AND gate 80 is connected to one input of AND gate 84. Figure 2
AND gate 80
If it is found that an inverter should have been inserted between the AND gate 84 and the AND gate 84, if the wiring 86 can be modified and reconnected as shown in FIG. Can be easily checked.

By the way, in actual products, various specifications have a sufficient margin so that they can be used under severe conditions. For example, the power wiring is sufficiently thicker than that required when the integrated circuit is used under normal circumstances. However, if an operation failure is found in the prototype integrated circuit and it is merely corrected to confirm whether or not the correct logical operation is actually performed, the power wiring that is thick is not necessary. Therefore, a part of the power supply wiring is stripped off by using a device such as a focused ion beam device (FIB) to expose the logic defect relief cell in the lower layer, and the logic defect is formed by using a conductor such as tungsten. Even if the circuit connection is corrected by connecting the terminal of the relief cell and a necessary portion, there is no problem in confirming that the normal operation is performed in this corrected state. In this way, it is not necessary to return to the stage of the automatic placement and routing tool to recreate the layout and recreate a new prototype integrated circuit based on the layout.

By the way, in the conventional integrated circuit, no circuit element is formed in the feedthrough cell 36 of FIG. From the perspective of wanting to integrate many circuit elements in a small area, it is not efficient to leave these regions unused. Therefore, in the present embodiment, the logic defect relief cells are arranged in these circuit element non-fabrication regions.

FIG. 5 shows a CM in the area of the feedthrough cell.
FIG. 6 is a cross-sectional view of an integrated circuit in which an OS inverter is formed as a logic defect relief cell. In the figure, the silicon substrate 6
0 and the diffusion layers 62 and 64 formed on top of Pg
The layer (polysilicon layer) constitutes a transistor 74 for an inverter, which serves as a cell for remedying logic defects. The aluminum layers (Al layers) 68 and 72 are used for input / output of gates or wiring for connecting gates. Also layer 66,
70 is an insulating layer made of silicon dioxide (SiO ₂ ).
The input of the transistor 74 is connected to the Al layer 68, but its output is not connected to the Al tank 72. It is therefore independent of the external circuitry and is not normally used unless it is used to modify circuit connections.

When it is actually necessary to use the transistor 74 of the logic defect relief cell, the Al layer 72 and the insulating layer 70 thereabove are stripped off by the FIB device or the like, and the output terminal of the transistor 74 is taken out. , And connect it to the required place using a tungsten wire or the like. The integrated circuit modified in this way can be checked for operation,
There is no need to go back to the layout stage and recreate the prototype integrated circuit.

Alternatively, in the case of manufacturing a prototype of an actual integrated circuit, generally, in each of a large number of processes, at the stage when those processes are completed, a certain number of wafers that have been completed up to that process are used. Often left. As an example, it is assumed that there are a total of 10 trial production steps, of which the cell layer is formed up to the seventh step and the wiring layer is formed after the eighth step. Since it was found that the prototyped integrated circuit had a logic defect, if an attempt is made to change the wiring by using the logic defect relief cell, only the mask in the wiring process needs to be changed. It is possible to use all the stopped wafers as they are.

Of the steps of forming an integrated circuit, the step of forming cells, particularly the step of forming diffusion layers 62 and 64 of FIG. 5, is the same as the step of forming Al layers 68 and 72 for wiring cells. It takes time and effort compared to. Therefore, a relatively large number of wafers are flown up to the cell manufacturing process including the logic defect relief cell, and for the subsequent processes, only a small number of wafers are flowed first, and the operation is confirmed at the stage of trial manufacture to check for defects. If so, change the circuit connection using the logic defect relief cell, correct the mask in the wiring process if it is confirmed to operate correctly, and use the new mask for the wafer stopped in the cell manufacturing process. Proceed to the wiring process used. By doing so, the number of wafers that are wasted when a prototype integrated circuit has a logic defect can be minimized, and the period, cost, and labor required for the correction can be significantly reduced.

By the way, as shown in FIG. 2, in one integrated circuit, feedthrough cells 32, 34, 36, 38,
There are many such as 40. Therefore, it becomes a problem where and what kind of logic defect relief cell is arranged in these feedthrough cells and power supply wirings. In this embodiment, a computer is used to calculate what kind of logic defect relief cell is to be arranged, and a new layout of an integrated circuit including the logic defect relief cell is automatically created.

FIG. 1 is a flow chart showing a process for automatically creating a layout of an integrated circuit including logic failure relief cells by a computer. First, in step S1, the layout data of the integrated circuit as shown in FIG. 2 created by the automatic placement and routing tool is read.

In step 2, data relating to the logic defect relief cell is input. For example, as explained in FIG.
When arranging a cell for logic defect relief in the lower layer of the feedthrough cell or the power supply wiring, if a cell using the Al layer 72 is arranged, such a cell cannot be used because it is short-circuited with the wiring. Since the areas of the feedthrough cells are different between 32 and 40 in FIG. 2, the types of logic defect relief cells that can be arranged are also limited by their size. The data relating to the logical defect relief cell is data relating to individual layouts of cells arranged as such logical defect relief cells. This data can also be obtained by reading the data prepared in advance as a library into a computer instead of being input by the operator.

In step S3, data relating to arrangement conditions such as what kind of circuit element is to be arranged in the circuit element non-fabrication area is input. For example, it is assumed that there are a plurality of types of logic defect relief cells that can be arranged in a specific feedthrough cell when only the shapes of the feedthrough cells and the logic defect relief cells are taken into consideration. At this time, if the type of the logic defect relief cell to be arranged in the feed-through cell is determined without further consideration, the logic defect relief cell corrects the defect location when a defect occurs in its periphery. The probability that it can be used for is low. Therefore, in order to increase the possibility of making a correction using a prepared logic defect relief cell when a defect occurs, the type of the logic defect relief cell to be arranged can be determined based on some regularity. desirable. In this way, when some kind of logic defect is found, a variety of corrections are available. The condition data for that is the data relating to the arrangement condition here.

More specifically, for example, when a 3-input NAND is used as an original gate, it is often the case that it is desired to add another condition to the input to make it a 4-input NAND. In such a case, if a cell for forming another input to the 3-input NAND is prepared in the lower layer of the feed-through cell or the power supply wiring in the periphery, relief in the case where the logic circuit is changed is easy. You can do it. Alternatively, gates in the same series as the most gates around the feedthrough cell can be prepared in advance as the logic defect relief cell. That is, when some kind of logic defect is discovered,
It is desirable to prepare a type of logic defect relief cell that has the greatest variety of modifications. In this embodiment, a computer is used to automatically determine the optimum logic defect relief cell from the data relating to such arrangement conditions.

In step S4 of FIG. 1, a circuit element unfabricated region in which no transistor is formed is calculated and obtained from the layout data read above. This is because the layout data includes all positional data regarding all elements and wirings on the chip. In step S5, from the data input in step S3 and the circuit element non-fabricated area obtained in step S4, a region that conforms to the placement condition of the logic defect relief cell is calculated based on the data relating to the placement condition input in advance. . When the location for arranging the logic defect relief cell is obtained, in step S6,
A logic defect relief cell as shown in FIG. 3 is arranged.

In this way, the layout of the logic defect relief cells is determined, and when the logic defect relief cells are arranged in the data, new layout data is output in step S7. FIG. 6 is a diagram showing a new layout in which logic defect relief cells 92, 94, 96, 98 are arranged in the regions of the feedthrough cells 32, 34, 36, 38 in the layout of FIG. 2, respectively. . Considering the area of the feedthrough cell shown in FIG. 2, these logic defect relief cells are selected so as to be contained therein. When an integrated circuit including a logic defect relief cell is produced based on the new layout created in this way, when a defect is found somewhere, the integrated circuit uses the logic defect relief cell in the vicinity thereof. It is very likely that you can fix it.

The present invention is not limited to the above embodiment, but various modifications can be made within the scope of the invention.

[0036]

As described above, according to the first aspect of the present invention, the logic defect relief cell included in the new layout data automatically created from the data relating to the placement condition of the logic defect relief cell is , It is very likely to be used for defect relief when a defect is found in the vicinity of the defect, and a layout of an integrated circuit in which logic defect relief cells are formed in advance in the circuit element non-fabrication region can be obtained. , If you prototype an integrated circuit according to this layout,
Even if a defect is found after that, the operation can be confirmed without repairing the integrated circuit again by returning to the layout stage by correcting with the logical defect relief cell. Therefore, it is possible to provide an automatic placement and routing method for an integrated circuit, which can significantly reduce the period, labor, and material cost required for the development of the integrated circuit.

According to the second aspect of the present invention, in addition to the above effects, by providing the logic defect relief cell in the region where the original circuit element is not formed, or in the area where the power supply wiring is formed, the space for space is provided. An automatic placement and routing method for an integrated circuit with high efficiency can be provided.

According to the third aspect of the invention, the logic defect relief cell is formed in advance in the circuit element non-fabricated region by the method according to the first or second aspect of the invention. Even if is found, the operation can be confirmed by correcting with this logic defect relief cell without having to go back to the layout stage and prototype again. An integrated circuit that can significantly reduce labor and material cost can be provided.

[Brief description of drawings]

FIG. 1 is a flowchart showing steps of an automatic placement and routing method for an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a part of a layout of an integrated circuit created by an automatic placement and routing tool.

FIG. 3 is a circuit diagram of a part of an integrated circuit including logic failure relief cells.

FIG. 4 is a circuit diagram showing a state in which a part of the wiring of the circuit shown in FIG. 3 has been corrected by the logic defect relief cell.

FIG. 5 is a cross-sectional view of an example integrated circuit including a logic defect relief cell.

FIG. 6 is a diagram showing a part of a new layout created by arranging logic defect relief cells in feedthrough cells based on the layout of FIG. 2;

[Explanation of symbols]

 20 power supply line (Vdd) 22 ground line (GND) 32, 34, 36, 38, 40 feed through cell 42, 44, 46, 48, 50 wiring 62, 64 diffusion layer 66, 70 insulating layer 68, 72 Al layer 80 , 84 AND gate 82 Inverter 92, 94, 96, 98 Logic defect relief cell

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 8832-4M H01L 21/82 R 27/04 TA

Claims (3)

[Claims] 1. A first data relating to a layout of circuit elements created from a circuit diagram, a second data relating to a spare circuit element to be arranged in a circuit element non-fabrication area in the layout, and a circuit element not existing. Using the third data regarding the condition of what kind of circuit element is to be arranged in the manufacturing area, the layout of the integrated circuit is characterized in that a layout in which spare circuit elements are automatically arranged in the circuit element non-manufacturing area is created. Automatic place and route method. 2. The automatic placement and routing method for an integrated circuit according to claim 1, wherein the circuit element non-fabrication region is a region in which a feedthrough cell is formed or a power supply line is formed. 3. Based on a layout created by the automatic placement and routing method for an integrated circuit according to claim 1 or 2,
An integrated circuit, wherein the spare circuit element is formed in the circuit element non-fabrication region.