WO2021000560A1 - Semiconductor memory preparation method and semiconductor memory - Google Patents

Semiconductor memory preparation method and semiconductor memory Download PDF

Info

Publication number
WO2021000560A1
WO2021000560A1 PCT/CN2020/070436 CN2020070436W WO2021000560A1 WO 2021000560 A1 WO2021000560 A1 WO 2021000560A1 CN 2020070436 W CN2020070436 W CN 2020070436W WO 2021000560 A1 WO2021000560 A1 WO 2021000560A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
basic
semiconductor memory
chip
manufacturing
Prior art date
Application number
PCT/CN2020/070436
Other languages
French (fr)
Chinese (zh)
Inventor
彭泽忠
Original Assignee
成都皮兆永存科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 成都皮兆永存科技有限公司 filed Critical 成都皮兆永存科技有限公司
Publication of WO2021000560A1 publication Critical patent/WO2021000560A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Definitions

  • the invention relates to semiconductors and production and preparation processes.
  • memory chip products of different capacities (such as 4GB, 16GB, and 256GB) generally need to be implemented with different mask sets.
  • advanced memory such as 3D multilayer NAND or OTP memory
  • the price of a mask is several million dollars to tens of millions of dollars.
  • the cost of developing multiple memory products with different capacities is very high.
  • the technical problem to be solved by the present invention is to provide a method for preparing a semiconductor memory, which can produce semiconductor memories of different capacities with the same mask set.
  • a basic memory module array is fabricated on a wafer, and the basic memory module has an IO circuit interface;
  • the IO circuit interfaces of the basic storage modules adjacent in the orthogonal direction are connected by interconnecting wires;
  • the step b is to determine the number of basic memory modules contained in the memory chip and the position of the edge line of the memory chip according to the predetermined memory chip capacity, and then scribing along the edge line of the memory chip and cutting the interconnection line across the edge line at the same time , Separate the entire memory chip from the wafer.
  • a switch is provided on the interconnection line
  • step a the following steps are also included: according to the preset, the state of each switch is initialized.
  • the step b further includes the following sub-step: setting the switch state on the interconnection line at the edge line of the chip to off.
  • the cut-off measure can be to open the switch or mechanically cut off.
  • the IO circuit interface includes at least one of the following types: data lines, control lines, and address lines.
  • the present invention also provides a semiconductor memory prepared by the foregoing semiconductor memory manufacturing method.
  • a set of masks can be used to produce memories with different capacities, which greatly reduces the process cost.
  • the invention realizes the interconnection between basic storage modules on the wafer, and has high transmission speed and high reliability.
  • Figure 1 is a schematic diagram of a prior art memory.
  • Fig. 2 is a three-dimensional schematic diagram of a basic storage module of the first embodiment.
  • FIG. 3 is a schematic diagram of the basic storage module structure of the first embodiment.
  • FIG. 4 is a schematic diagram of the connection relationship between the IO interface and the interconnection line in the first embodiment.
  • FIG. 5 is a schematic diagram of a 2 ⁇ 2 memory cell array according to the first embodiment.
  • FIG. 6 is a three-dimensional schematic diagram of a 2 ⁇ 2 memory cell array in the first embodiment.
  • FIG. 7 is a schematic diagram of the basic storage module structure of the second embodiment.
  • FIG. 8 is a schematic diagram of the connection relationship between the IO interface and the interconnection line in the second embodiment.
  • FIG. 9 is a schematic diagram of a 2 ⁇ 2 memory cell array of the second embodiment.
  • Figure 10 is a schematic diagram of equivalent connections of basic memory modules in the same chip.
  • FIG. 11 is a schematic diagram of dicing in Example 1.
  • FIG. 11 is a schematic diagram of dicing in Example 1.
  • Figure 12 is a schematic diagram of the chip structure of the present invention.
  • Figure 1 shows a prior art memory, which includes a memory matrix composed of an IO circuit and a plurality of memory cells.
  • the IO circuit includes functional modules such as address, data, clock, control, reading and writing, charge pump, power supply, etc.
  • the internal interface of the IO circuit is connected to the word line, bit line, and control line of the memory matrix.
  • the present invention refers to the external interface of the IO circuit as IO circuit interface, used for external data transmission of the memory.
  • a set of masks can only be applied to a specific capacity, for example, the production capacity is 1G
  • the mask used by the memory cannot be used for 8G memory.
  • the present invention provides a process for preparing a bus-type memory, which can use a set of basic-capacity masks to produce an integer multiple of its capacity. For example, if the basic capacity of the mask is 1G, it can be periodically formed on the wafer. For a memory cell with a specific structure with a capacity of 1G (with interconnection lines), an integer number (for example, 8) of memory cells are included in a chip, diced, packaged, and initialized to become a semiconductor memory chip with a capacity of 8G.
  • the first implementation is a first implementation:
  • the three-dimensional schematic diagram of the basic storage module is shown in Fig. 2.
  • 21 is the IO interface formed by multiple IO connection points
  • 22 is the interconnection area, including the cross section of the interconnection.
  • Figure 3 shows the structure of the basic storage module, with arrows representing interconnection lines, and IO in Figures 3 to 10 represents an IO interface.
  • Figure 4 is an extremely simplified specific connection diagram, showing a minimalist IO interface, only ABCD these 4 IO contacts (circuit connection points, similar to pins), 4 ring-shaped connection lines Surrounding the IO interface, the interconnection lines are led out in 4 directions respectively, and the 4 sets of interconnection lines are connected in parallel. In the actual situation, the number of IO contacts is far more than 4, and Figure 4 only uses 4 as an illustration.
  • Figure 5 shows a 2 ⁇ 2 memory cell array.
  • the interconnection lines at the edge lines are cut off during dicing, and the cut interconnection lines are shown by dashed arrows; because they are cut off, they are in a floating state.
  • the interconnection lines connecting adjacent basic storage modules in the array are kept connected to realize the arrow shown, and each IO interface forms a bus-type connection relationship.
  • Figure 6 shows a three-dimensional schematic diagram of the storage array.
  • the basic storage module of this embodiment also includes a controllable interconnection line, which is different from the interconnection line in FIG. 3.
  • the controllable interconnection line is The marked arrow shows, The mark indicates the switch, that is, the on-off control of the interconnection line is realized by controlling the switch.
  • the control terminal of the switch is led out from the IO interface on the top of each storage module unit.
  • Figure 9 shows a 2 ⁇ 2 memory cell array.
  • the switch of each controllable interconnection line outside the black dotted line is turned off, that is, the interconnection line outside the dotted line is inactivated, or called “disable”. ", which is equivalent to the connection relationship shown in Figure 10, that is, a bus connection is formed.
  • Example 1 See Figure 11.
  • the arrow in Figure 11 is a simplified representation of a controllable interconnection line.
  • the predetermined capacity of each basic memory module is 1G
  • a chip with a capacity of 4G is made, and then dicing along the dashed line in FIG. 11 to form 4 4G chips.
  • the interconnection lines at the edge of the chip will be cut off during dicing.
  • the switch can be turned off through the switch control circuit (that is, the interconnection control circuit) during configuration.
  • each basic storage module of the smallest capacity unit can be written with a unique address (Chip ID) during testing or initialization (through NVM or OTP memory programming).
  • the controllable interconnection line can be enabled (connected) or disabled (disconnected) during initialization.
  • each basic storage module also has complete bounding pads.
  • the chip prepared based on the technology of the present invention includes at least two basic storage modules, and the IO interface of each basic storage module forms a bus connection through an interconnection line. After being packaged as a chip, the IO interface is connected to an external storage control circuit, and the external storage control circuit serves as a bus control circuit to perform functions such as addressing.
  • the present invention only needs a mask corresponding to a single basic memory module, and it can be used repeatedly to make basic memory chips on the wafer.
  • Module array in the subsequent process after the array is completed, the memory module group is formed by dicing according to the required capacity. After the memory module group is packaged, it becomes the memory chip of the required capacity.
  • the invention establishes the interconnection between the basic storage modules at the wafer level, and has the characteristics of high speed and high reliability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Disclosed are a semiconductor memory preparation method and a semiconductor memory, which relate to semiconductors and production preparation processes. The semiconductor memory preparation method in the present invention comprises the following steps: a. using a semiconductor integrated circuit manufacturing process to manufacture a basic storage module array on a wafer, wherein a basic storage module is provided with an IO circuit interface; b. scribing the wafer to obtain a storage chip; and c. packaging the memory chip obtained by separation, wherein in step a, IO circuit interfaces of adjacent basic storage modules in an orthogonal direction are connected through an interconnection line; and in step b, the number of basic storage modules contained in the storage chip and the positions of edge lines of the storage chip are determined according to pre-determined capacity of the storage chip, then scribing is performed along the edge lines of the storage chip; meanwhile, interconnection lines crossing the edge lines are cut off, and the whole storage chip is separated from the wafer. By using the technology provided in the present invention, memories with different capacities can be produced by one set of masks, so that the process cost are greatly reduced.

Description

半导体存储器制备方法及半导体存储器Semiconductor memory preparation method and semiconductor memory 技术领域Technical field
本发明涉及半导体及生产制备工艺。The invention relates to semiconductors and production and preparation processes.
背景技术Background technique
在通常的半导体存储器产品，不同容量(如4GB,16GB,256GB)的存储器芯片产品一般需要用不同的掩模套版(Mask Sets)来实现。对于先进存储器的加工工艺(如3D多层NAND或OTP存储器)，必须面临掩模套版的高成本问题，通常一套掩模的价格在几百万美金至上千万美金。相应的，开发多个不同容量的存储器产品的费用就非常高。In general semiconductor memory products, memory chip products of different capacities (such as 4GB, 16GB, and 256GB) generally need to be implemented with different mask sets. For the processing technology of advanced memory (such as 3D multilayer NAND or OTP memory), it is necessary to face the problem of high cost of mask lithography. Usually, the price of a mask is several million dollars to tens of millions of dollars. Correspondingly, the cost of developing multiple memory products with different capacities is very high.
发明内容Summary of the invention
本发明所要解决的技术问题是，提供一种半导体存储器制备方法，能够以同一套掩模套版生产不同容量的半导体存储器。The technical problem to be solved by the present invention is to provide a method for preparing a semiconductor memory, which can produce semiconductor memories of different capacities with the same mask set.
本发明解决所述技术问题采用的技术方案是，半导体存储器制备方法，包括下述步骤：The technical solution adopted by the present invention to solve the technical problem is that a semiconductor memory manufacturing method includes the following steps:
a、采用半导体集成电路制造工艺，在晶圆上制作基本存储模块阵列，基本存储模块具有IO电路接口；a. Using semiconductor integrated circuit manufacturing technology, a basic memory module array is fabricated on a wafer, and the basic memory module has an IO circuit interface;
b、对晶圆划片，得到存储芯片；b. Dicing the wafer to obtain a memory chip;
c、将分离得到的存储芯片进行封装；c. Packaging the separated memory chip;
其特征在于：Its characteristics are:
所述步骤a中，正交方向相邻基本存储模块的IO电路接口通过互联线连接；In the step a, the IO circuit interfaces of the basic storage modules adjacent in the orthogonal direction are connected by interconnecting wires;
所述步骤b为，按照预定的存储芯片容量，确定存储芯片内所包含的基本存储模块的数量及存储芯片边缘线的位置，然后沿存储芯片边缘线划片，同时切断跨越边缘线的互联线，将存储芯片整体从晶圆分离。The step b is to determine the number of basic memory modules contained in the memory chip and the position of the edge line of the memory chip according to the predetermined memory chip capacity, and then scribing along the edge line of the memory chip and cutting the interconnection line across the edge line at the same time , Separate the entire memory chip from the wafer.
还包括下述步骤：向各基本存储模块的存储区写入单元识别信息，例如地址。It also includes the following steps: writing unit identification information, such as an address, to the storage area of each basic storage module.
所述步骤a中，互联线上设置有开关；In the step a, a switch is provided on the interconnection line;
在步骤a以后，还包括下述步骤：依据预设，初始化各开关的状态。After step a, the following steps are also included: according to the preset, the state of each switch is initialized.
所述步骤b中，还包括下述子步骤：将芯片边缘线处的互联线上的开关状态设置为关断。The step b further includes the following sub-step: setting the switch state on the interconnection line at the edge line of the chip to off.
进一步的，还包括下述步骤：对存储芯片边缘线以内的基本存储模块逐一测试，对于异常的基本存储模块，切断其连接至正常基本存储模块的互联线。切断的措施可以是断开开关，或者机械性切断。Further, it also includes the following steps: test the basic memory modules within the edge line of the memory chip one by one, and cut off the interconnection lines connected to the normal basic memory modules for the abnormal basic memory modules. The cut-off measure can be to open the switch or mechanically cut off.
所述IO电路接口至少包括下述种类之一：数据线、控制线、地址线。The IO circuit interface includes at least one of the following types: data lines, control lines, and address lines.
本发明还提供一种采用前述半导体存储器制备方法制备的半导体存储器。The present invention also provides a semiconductor memory prepared by the foregoing semiconductor memory manufacturing method.
采用本发明的技术，能以一套掩模生产不同容量的存储器，极大的降低了工艺成本。本发明在晶圆上实现了各基本存储模块之间的互联，具有高传输速度和高可靠性。Using the technology of the present invention, a set of masks can be used to produce memories with different capacities, which greatly reduces the process cost. The invention realizes the interconnection between basic storage modules on the wafer, and has high transmission speed and high reliability.
附图说明Description of the drawings
图1是现有技术的存储器示意图。Figure 1 is a schematic diagram of a prior art memory.
图2是第一种实施方式的基本存储模块三维示意图。Fig. 2 is a three-dimensional schematic diagram of a basic storage module of the first embodiment.
图3是第一种实施方式的基本存储模块结构示意图。FIG. 3 is a schematic diagram of the basic storage module structure of the first embodiment.
图4是第一种实施方式的IO接口和互联线的连接关系示意图。FIG. 4 is a schematic diagram of the connection relationship between the IO interface and the interconnection line in the first embodiment.
图5是第一种实施方式的2×2的存储单元阵列示意图。FIG. 5 is a schematic diagram of a 2×2 memory cell array according to the first embodiment.
图6是第一种实施方式的2×2的存储单元阵列三维示意图。FIG. 6 is a three-dimensional schematic diagram of a 2×2 memory cell array in the first embodiment.
图7是第二种实施方式的基本存储模块结构示意图。FIG. 7 is a schematic diagram of the basic storage module structure of the second embodiment.
图8是第二种实施方式的IO接口和互联线的连接关系示意图。FIG. 8 is a schematic diagram of the connection relationship between the IO interface and the interconnection line in the second embodiment.
图9是第二种实施方式的2×2的存储单元阵列示意图。FIG. 9 is a schematic diagram of a 2×2 memory cell array of the second embodiment.
图10是同一个芯片内各基本存储模块等效连接示意图。Figure 10 is a schematic diagram of equivalent connections of basic memory modules in the same chip.
图11是实施例1的划片示意图。11 is a schematic diagram of dicing in Example 1. FIG.
图12是本发明的芯片结构示意图。Figure 12 is a schematic diagram of the chip structure of the present invention.
具体实施方式Detailed ways
图1示出了一种现有技术的存储器，其包括IO电路和多个存储器单元构成的存储器矩阵。IO电路包括地址、数据、时钟、控制、读写、电荷泵、电源等功能模块，IO电路的内部接口连接存储器矩阵的字线、位线、控制线，本发明将IO电路的外部接口称为IO电路接口，用于存储器对外的数据传输。在现有技术的制备工艺中，在晶圆上制备存 储器，需要利用掩膜在晶圆上形成存储电路和IO电路，一套掩膜只能适用于一种特定容量，例如，生产容量为1G的存储器所采用的掩膜无法用于8G的存储器。Figure 1 shows a prior art memory, which includes a memory matrix composed of an IO circuit and a plurality of memory cells. The IO circuit includes functional modules such as address, data, clock, control, reading and writing, charge pump, power supply, etc. The internal interface of the IO circuit is connected to the word line, bit line, and control line of the memory matrix. The present invention refers to the external interface of the IO circuit as IO circuit interface, used for external data transmission of the memory. In the prior art manufacturing process, to prepare memory on a wafer, it is necessary to use a mask to form memory circuits and IO circuits on the wafer. A set of masks can only be applied to a specific capacity, for example, the production capacity is 1G The mask used by the memory cannot be used for 8G memory.
本发明提供了一种总线式存储器的制备工艺，可以利用一套基本容量的掩膜生产其整数倍容量的存储器，例如，掩膜的基本容量为1G，则可在晶圆上周期性的形成容量为1G的特定结构的存储单元(带有互联线)，将整数个(例如8个)存储单元列入一个芯片并划片，封装，初始化后即成为容量为8G的半导体存储芯片。The present invention provides a process for preparing a bus-type memory, which can use a set of basic-capacity masks to produce an integer multiple of its capacity. For example, if the basic capacity of the mask is 1G, it can be periodically formed on the wafer For a memory cell with a specific structure with a capacity of 1G (with interconnection lines), an integer number (for example, 8) of memory cells are included in a chip, diced, packaged, and initialized to become a semiconductor memory chip with a capacity of 8G.
第一种实施方式：The first implementation:
基本存储模块三维示意图如图2，21为多个IO连接点形成的IO接口，22为互联线区域，包含了互联线的断面。The three-dimensional schematic diagram of the basic storage module is shown in Fig. 2. 21 is the IO interface formed by multiple IO connection points, and 22 is the interconnection area, including the cross section of the interconnection.
图3示出了基本存储模块的结构，以箭头表示互联线，图3～图10中的IO表示IO接口。图4为一种极度简化的具体连接示意图，示出了一种极简的IO接口，仅有ABCD这4个IO触点(电路连接点，类似于引脚)，4条环状的连接线环绕IO接口，在4个方向分别引出互联线，4组互联线为并联关系。实际情况中，IO的触点数远不止4个，图4仅以4个作为示意。Figure 3 shows the structure of the basic storage module, with arrows representing interconnection lines, and IO in Figures 3 to 10 represents an IO interface. Figure 4 is an extremely simplified specific connection diagram, showing a minimalist IO interface, only ABCD these 4 IO contacts (circuit connection points, similar to pins), 4 ring-shaped connection lines Surrounding the IO interface, the interconnection lines are led out in 4 directions respectively, and the 4 sets of interconnection lines are connected in parallel. In the actual situation, the number of IO contacts is far more than 4, and Figure 4 only uses 4 as an illustration.
图5示出了一个2×2的存储单元阵列，在划片时将边缘线处的互联线切断，切断的互联线以虚线箭头示出；因为被切断，处于浮空的状态。阵列内连接相邻基本存储模块的互联线保持连通，以实现箭头示出，各IO接口形成了总线式的连接关系。图6示出了该存储阵列的三维示意图。Figure 5 shows a 2×2 memory cell array. The interconnection lines at the edge lines are cut off during dicing, and the cut interconnection lines are shown by dashed arrows; because they are cut off, they are in a floating state. The interconnection lines connecting adjacent basic storage modules in the array are kept connected to realize the arrow shown, and each IO interface forms a bus-type connection relationship. Figure 6 shows a three-dimensional schematic diagram of the storage array.
第二种实施方式：The second implementation mode:
参见图7和图8，本实施方式的基本存储模块除了存储电路和IO电路，还包括可控互联线，有别于图3中的互联线。图7中，可控互联线以带有
Figure PCTCN2020070436-appb-000001
标记的箭头示出，
Figure PCTCN2020070436-appb-000002
标记表示开关，即通过控制开关实现对互联线通断的控制。开关的控制端从每个存储模块单元顶部的IO接口处引出。 Referring to FIGS. 7 and 8, in addition to the storage circuit and the IO circuit, the basic storage module of this embodiment also includes a controllable interconnection line, which is different from the interconnection line in FIG. 3. In Figure 7, the controllable interconnection line is
Figure PCTCN2020070436-appb-000001
The marked arrow shows,
Figure PCTCN2020070436-appb-000002
The mark indicates the switch, that is, the on-off control of the interconnection line is realized by controlling the switch. The control terminal of the switch is led out from the IO interface on the top of each storage module unit.
图9示出了一个2×2的存储单元阵列，通过配置互联控制电路将黑色虚线以外的各可控互联线的开关断开，即将虚线以外的互联线失活，或称为关闭，“disable”，其等价于图10所示的连接关系，也就是形成总线式连接。Figure 9 shows a 2×2 memory cell array. By configuring the interconnection control circuit, the switch of each controllable interconnection line outside the black dotted line is turned off, that is, the interconnection line outside the dotted line is inactivated, or called “disable”. ", which is equivalent to the connection relationship shown in Figure 10, that is, a bus connection is formed.
实施例1：参见图11。图11的箭头是可控互联线的简化表示方式。Example 1: See Figure 11. The arrow in Figure 11 is a simplified representation of a controllable interconnection line.
本实施例的半导体存储器制备方法包括下述步骤：The semiconductor memory manufacturing method of this embodiment includes the following steps:
a、采用半导体集成电路制造工艺，在晶圆上制作基本存储模块阵列，每一基本存储模块包括一个IO电路和与IO电路连接的预定容量的存储电路。图11示出了4×4＝16个存储单元，正交方向相邻的存储单元的IO电路D的IO接口通过可控互联线连接；a. Using a semiconductor integrated circuit manufacturing process, a basic memory module array is fabricated on a wafer. Each basic memory module includes an IO circuit and a memory circuit of a predetermined capacity connected to the IO circuit. FIG. 11 shows 4×4=16 storage units, and the IO interfaces of the IO circuits D of the storage units adjacent in the orthogonal direction are connected by a controllable interconnection line;
b、按照预定的存储芯片容量，确定存储芯片内所包含的存储单元的数量，然后划片分离存储芯片。b. Determine the number of memory cells contained in the memory chip according to the predetermined memory chip capacity, and then dicing and separate the memory chip.
c、将分离得到的存储芯片进行封装；c. Packaging the separated memory chip;
例如，步骤a中，预定的每个基本存储模块的容量是1G，制作容量为4G的芯片，则沿图11的虚线划片，形成4个4G的芯片。划片时将会切断芯片边缘位置的互联线，对于并无引出必要的，在配置时， 通过开关的控制电路(即互联控制电路)将其开关断开即可。For example, in step a, the predetermined capacity of each basic memory module is 1G, and a chip with a capacity of 4G is made, and then dicing along the dashed line in FIG. 11 to form 4 4G chips. The interconnection lines at the edge of the chip will be cut off during dicing. For those that are not necessary for lead-out, the switch can be turned off through the switch control circuit (that is, the interconnection control circuit) during configuration.
进一步的，每个最小容量单位的基本存储模块可以在测试或初始化时写入惟一的地址(Chip ID)(通过NVM或OTP存储器编程)。可控互联线可以通过初始化时Enable(连接)或Disable(断开)。每个基本存储模块除完整的存储功能外，还有完整的边界焊盘(bounding pads)。Further, each basic storage module of the smallest capacity unit can be written with a unique address (Chip ID) during testing or initialization (through NVM or OTP memory programming). The controllable interconnection line can be enabled (connected) or disabled (disconnected) during initialization. In addition to complete storage functions, each basic storage module also has complete bounding pads.
参见图12，基于本发明技术制备的芯片，包括了至少两个基本存储模块，各基本存储模块的IO接口通过互联线形成总线式连接。封装为芯片后，IO接口连接至外部存储控制电路，外部存储控制电路作为总线控制电路完成寻址等功能。Referring to FIG. 12, the chip prepared based on the technology of the present invention includes at least two basic storage modules, and the IO interface of each basic storage module forms a bus connection through an interconnection line. After being packaged as a chip, the IO interface is connected to an external storage control circuit, and the external storage control circuit serves as a bus control circuit to perform functions such as addressing.
不同于现有技术的“一种掩模只能制备一种特定容量的存储器芯片”，本发明只需要一个对应于单个基本存储模块的掩模，重复使用即可在晶圆上制作出基本存储模块阵列，在阵列制作完成后的后续工艺中，依据需求容量划片形成存储模块组，存储模块组封装后即成为需求容量大小的存储器芯片，实现了“以一种掩模制备多种容量的存储器芯片”的效果。本发明在晶圆层面建立了基本存储模块之间的互联，具有高速高可靠性的特点。Different from the prior art "a mask can only prepare a memory chip with a specific capacity", the present invention only needs a mask corresponding to a single basic memory module, and it can be used repeatedly to make basic memory chips on the wafer. Module array, in the subsequent process after the array is completed, the memory module group is formed by dicing according to the required capacity. After the memory module group is packaged, it becomes the memory chip of the required capacity. The effect of "memory chip". The invention establishes the interconnection between the basic storage modules at the wafer level, and has the characteristics of high speed and high reliability.

Claims (7)

  1. 半导体存储器制备方法，包括下述步骤：The semiconductor memory manufacturing method includes the following steps:
    a、采用半导体集成电路制造工艺，在晶圆上制作基本存储模块阵列，基本存储模块具有IO电路接口；a. Using semiconductor integrated circuit manufacturing technology, a basic memory module array is fabricated on a wafer, and the basic memory module has an IO circuit interface;
    b、对晶圆划片，得到存储芯片；b. Dicing the wafer to obtain a memory chip;
    c、将分离得到的存储芯片进行封装；c. Packaging the separated memory chip;
    其特征在于：Its characteristics are:
    所述步骤a中，正交方向相邻基本存储模块的IO电路接口通过互联线连接；In the step a, the IO circuit interfaces of the basic storage modules adjacent in the orthogonal direction are connected by interconnecting wires;
    所述步骤b为，按照预定的存储芯片容量，确定存储芯片内所包含的基本存储模块的数量及存储芯片边缘线的位置，然后沿存储芯片边缘线划片，同时切断跨越边缘线的互联线，将存储芯片整体从晶圆分离。The step b is to determine the number of basic memory modules contained in the memory chip and the position of the edge line of the memory chip according to the predetermined memory chip capacity, and then scribing along the edge line of the memory chip and cutting the interconnection line across the edge line at the same time , Separate the entire memory chip from the wafer.
  2. 如权利要求1所述的半导体存储器制备方法，其特征在于，还包括下述步骤：5. The method of manufacturing a semiconductor memory according to claim 1, further comprising the following steps:
    向各基本存储模块的存储区写入单元识别信息。Write cell identification information to the storage area of each basic storage module.
  3. 如权利要求1所述的半导体存储器制备方法，其特征在于，The method for manufacturing a semiconductor memory according to claim 1, wherein:
    所述步骤a中，互联线上设置有开关；In the step a, a switch is provided on the interconnection line;
    在步骤a以后，还包括下述步骤：依据预设，初始化各开关的状态。After step a, the following steps are also included: according to the preset, the state of each switch is initialized.
  4. 如权利要求1所述的半导体存储器制备方法，其特征在于，所述步骤b中，还包括下述子步骤：将芯片边缘线处的互联线上的开关状态设置为关断。The method for manufacturing a semiconductor memory according to claim 1, wherein said step b further comprises the following sub-step: setting the switch state on the interconnection line at the edge line of the chip to off.
  5. 如权利要求1所述的半导体存储器制备方法，其特征在于，还包括下述步骤：对存储芯片边缘线以内的基本存储模块逐一测试，对于异常的基本存储模块，切断其连接至正常基本存储模块的互联线。2. The semiconductor memory manufacturing method of claim 1, further comprising the step of: testing the basic memory modules within the edge line of the memory chip one by one, and disconnecting the abnormal basic memory module from the normal basic memory module Interconnection line.
  6. 如权利要求1所述的半导体存储器制备方法，其特征在于，所述IO电路接口至少包括下述种类之一：数据线、控制线、地址线。5. The method for manufacturing a semiconductor memory according to claim 1, wherein the IO circuit interface includes at least one of the following types: data lines, control lines, and address lines.
  7. 采用权利要求1、2、3、4、5或6所述的半导体存储器制备方法制备的半导体存储器。A semiconductor memory manufactured by the method of manufacturing a semiconductor memory according to claim 1, 2, 3, 4, 5 or 6.
PCT/CN2020/070436 2019-07-03 2020-01-06 Semiconductor memory preparation method and semiconductor memory WO2021000560A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910592710.0 2019-07-03
CN201910592710.0A CN110491785A (en) 2019-07-03 2019-07-03 Semiconductor memory preparation method and semiconductor memory

Publications (1)

Publication Number Publication Date
WO2021000560A1 true WO2021000560A1 (en) 2021-01-07

Family

ID=68545955

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/070436 WO2021000560A1 (en) 2019-07-03 2020-01-06 Semiconductor memory preparation method and semiconductor memory

Country Status (2)

Country Link
CN (1) CN110491785A (en)
WO (1) WO2021000560A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110491785A (en) * 2019-07-03 2019-11-22 成都皮兆永存科技有限公司 Semiconductor memory preparation method and semiconductor memory
US11721585B2 (en) * 2021-08-02 2023-08-08 Jack Zezhong Peng Method for fabricating semiconductor memory and the semiconductor memory

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078096A (en) * 1997-03-31 2000-06-20 Sharp Kabushiki Semiconductor integrated circuit device having a short circuit preventing circuit
CN1463036A (en) * 2001-07-10 2003-12-24 株式会社东芝 Chip of memory, chip-on-chip device of using same and its mfg. method
CN2613887Y (en) * 2003-02-22 2004-04-28 鲍刚 Card type semiconductor memory
CN1716602A (en) * 2004-06-29 2006-01-04 尔必达存储器股份有限公司 Stacked semiconductor memory device
CN110491785A (en) * 2019-07-03 2019-11-22 成都皮兆永存科技有限公司 Semiconductor memory preparation method and semiconductor memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267389A (en) * 2000-03-21 2001-09-28 Hiroshima Nippon Denki Kk System and method for producing semiconductor memory
KR102384733B1 (en) * 2017-09-26 2022-04-08 삼성전자주식회사 Semiconductor memory devices, methods of operating semiconductor memory devices and memory systems

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078096A (en) * 1997-03-31 2000-06-20 Sharp Kabushiki Semiconductor integrated circuit device having a short circuit preventing circuit
CN1463036A (en) * 2001-07-10 2003-12-24 株式会社东芝 Chip of memory, chip-on-chip device of using same and its mfg. method
CN2613887Y (en) * 2003-02-22 2004-04-28 鲍刚 Card type semiconductor memory
CN1716602A (en) * 2004-06-29 2006-01-04 尔必达存储器股份有限公司 Stacked semiconductor memory device
CN110491785A (en) * 2019-07-03 2019-11-22 成都皮兆永存科技有限公司 Semiconductor memory preparation method and semiconductor memory

Also Published As

Publication number Publication date
CN110491785A (en) 2019-11-22

Similar Documents

Publication Publication Date Title
CN105793928B (en) Three-dimensional NOR flash memory system with configurable pins
US9300298B2 (en) Programmable logic circuit using three-dimensional stacking techniques
KR100895073B1 (en) 3-d-memory device for large storage capacity
US7126196B2 (en) Self-testing printed circuit board comprising electrically programmable three-dimensional memory
EP0541288B1 (en) Circuit module redundacy architecture
US8994404B1 (en) Semiconductor device and structure
US8446772B2 (en) Memory die self-disable if programmable element is not trusted
CN101261945A (en) Fabrication method of semiconductor structure
TW201432886A (en) Three-dimensional flash memory system
JP2009266258A (en) Semiconductor device
WO2021000560A1 (en) Semiconductor memory preparation method and semiconductor memory
JP2008085342A (en) Method for identifying and/or programming integrated circuit
US6963511B2 (en) Semiconductor integrated circuit
US10998014B2 (en) Semiconductor dies supporting multiple packaging configurations and associated methods
US20250031455A1 (en) Three-dimensional device and manufacturing method thereof
US10002653B2 (en) Die stack address bus having a programmable width
CN104424379B (en) Verify part of good voltage island structure
US6578157B1 (en) Method and apparatus for recovery of useful areas of partially defective direct rambus rimm components
CN107068195B (en) Three-dimensional chip with fault repairing device and fault repairing and data reading method
US11721585B2 (en) Method for fabricating semiconductor memory and the semiconductor memory
CN100477213C (en) Programmable integrated circuit chip and method of operation thereof
JPS59119743A (en) Redundant configuration method for integrated circuits
CN118585387B (en) Chip, chip testing method and electronic equipment
US9093445B2 (en) Packaging identical chips in a stacked structure
US20240258269A1 (en) Wafer-level packaging method for semiconductor and semiconductor package

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20834271

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20834271

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20834271

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 21/09/2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20834271

Country of ref document: EP

Kind code of ref document: A1