CN110491785A - Semiconductor memory preparation method and semiconductor memory - Google Patents
Semiconductor memory preparation method and semiconductor memory Download PDFInfo
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- CN110491785A CN110491785A CN201910592710.0A CN201910592710A CN110491785A CN 110491785 A CN110491785 A CN 110491785A CN 201910592710 A CN201910592710 A CN 201910592710A CN 110491785 A CN110491785 A CN 110491785A
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- semiconductor memory
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Abstract
Semiconductor memory preparation method and semiconductor memory are related to semiconductor and process for producing.Semiconductor memory preparation method of the invention includes the following steps: a, using semiconductor integrated circuit manufacturing process, and basic storage module array is made on wafer, and basic storage module has I/O circuit interface；B, to Wafer Dicing, storage chip is obtained；C, isolated storage chip is packaged；In the step a, the I/O circuit interface of the adjacent basic storage module of orthogonal direction is connected by interconnection line；The step b is, according to scheduled storage chip capacity, the quantity for the basic storage module for being included in storage chip and the position of storage chip edge line are determined, then along storage chip edge line scribing, the interconnection line for cutting off bounding edge line simultaneously, storage chip is whole from wafer separate.Using technology of the invention, the memory of different capabilities can be produced with mask set, greatly reduces process costs.
Description
Technical field
The present invention relates to semiconductor and process for producing.
Background technique
In common semiconductor memory product, the storage core flake products one of different capabilities (such as 4GB, 16GB, 256GB)
As need with different mask registering (Mask Sets) Lai Shixian.For processing technology (such as 3D multilayer NAND of advanced memory
Or otp memory), it is necessary to the high cost problem of mask registering is faced, the price of usual mask set is supreme in millions of U.S. dollars
Ten million U.S. dollar.Correspondingly, the expense for developing the memory product of multiple and different capacity is just very high.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of semiconductor memory preparation methods, can be with same set of
The semiconductor memory of mask registering production different capabilities.
The present invention solve the technical problem the technical solution adopted is that, semiconductor memory preparation method, including following
Step:
A, using semiconductor integrated circuit manufacturing process, basic storage module array is made on wafer, substantially storage mould
Block has I/O circuit interface；
B, to Wafer Dicing, storage chip is obtained；
C, isolated storage chip is packaged；
It is characterized by:
In the step a, the I/O circuit interface of the adjacent basic storage module of orthogonal direction is connected by interconnection line；
The step b is, according to scheduled storage chip capacity, to determine the basic storage module for being included in storage chip
Quantity and storage chip edge line position, then along storage chip edge line scribing, while cutting off the mutual of bounding edge line
On line, storage chip is whole from wafer separate.
It further include following step: to the memory block writing unit identification information of each basic storage module, such as address.
In the step a, switch is provided on interconnection line；
Further include following step after step a: according to presetting, initializing the state of each switch.
Further include following sub-steps in the step b: setting the switch state on the interconnection line at chip edge line to
Shutdown.
Further, further include following step: the basic storage module within storage chip edge line is tested one by one, it is right
In abnormal basic storage module, its interconnection line for being connected to normal basic storage module is cut off.The measure of cutting can be disconnected
Switch or mechanicalness cutting.
The I/O circuit interface includes at least one of following types: data line, control line, address wire.
The present invention also provides a kind of semiconductor memories prepared using aforesaid semiconductor memory preparation method.
Using technology of the invention, the memory of different capabilities can be produced with mask set, greatly reduce technique at
This.The present invention realizes the interconnection between each basic storage module on wafer, has high transmission speed and high reliability.
Detailed description of the invention
Fig. 1 is the memory schematic diagram of the prior art.
Fig. 2 is the basic storage module schematic three dimensional views of the first embodiment.
Fig. 3 is the basic storage module structural schematic diagram of the first embodiment.
Fig. 4 is the I/O interface of the first embodiment and the connection relationship diagram of interconnection line.
Fig. 5 is the memory cell array schematic diagram of the 2 × 2 of the first embodiment.
Fig. 6 is the memory cell array schematic three dimensional views of the 2 × 2 of the first embodiment.
Fig. 7 is the basic storage module structural schematic diagram of second of embodiment.
Fig. 8 is the I/O interface of second of embodiment and the connection relationship diagram of interconnection line.
Fig. 9 is the memory cell array schematic diagram of the 2 × 2 of second of embodiment.
Figure 10 is each basic storage module Equivalent conjunction schematic diagram in the same chip.
Figure 11 is the scribing schematic diagram of embodiment 1.
Figure 12 is chip structure schematic diagram of the invention.
Specific embodiment
Fig. 1 shows a kind of memory of prior art comprising the storage of I/O circuit and multiple memory cells composition
Device matrix.I/O circuit includes the functional modules such as address, data, clock, control, read-write, charge pump, power supply, the inside of I/O circuit
Interface connects the wordline of memory matrix, bit line, control line, and the external interface of I/O circuit is known as I/O circuit interface by the present invention,
The data transmission external for memory.In the preparation process of the prior art, memory is prepared on wafer, is needed to utilize and be covered
Film forms storage circuit and I/O circuit on wafer, and a set of exposure mask may be only available for a kind of specified vol, for example, production capacity is
Exposure mask used by the memory of 1G is not used to the memory of 8G.
The present invention provides a kind of preparation processes of bus type memory, can use the exposure mask production of a set of basic capacity
The memory of its integral multiple capacity, for example, the basic capacity of exposure mask is 1G, then it is 1G that capacity can be periodically formed on wafer
Specific structure storage unit (have interconnection line), integer (such as 8) storage unit is included in a chip and scribing,
Encapsulation becomes the semiconductor memory chip that capacity is 8G after initialization.
The first embodiment:
Basic storage module schematic three dimensional views such as Fig. 2,21 I/O interfaces formed for multiple IO tie points, 22 be interconnection line area
Domain contains the section of interconnection line.
Fig. 3 shows the structure of basic storage module, is depicted with arrows interconnection line, and the I O table in Fig. 3~Figure 10 shows that IO connects
Mouthful.Fig. 4 is a kind of specific connection schematic diagram of extreme facility, shows a kind of extremely simple I/O interface, this 4 IO touchings of only ABCD
Point (circuit connection point, be similar to pin), 4 cricoid connecting lines draw interconnection line around I/O interface, in 4 directions respectively, and 4
Group interconnection line is parallel relationship.In actual conditions, the number of contacts of IO is far above 4, and Fig. 4 is only using 4 as signal.
Fig. 5 shows one 2 × 2 memory cell array, cuts off the interconnection line at edge line in scribing, cutting
Interconnection line is shown with dotted arrow；Because being cut off, the state in floating.The adjacent basic storage module of connection is mutual in array
On line keeps connection, and to realize that arrow is shown, each I/O interface forms the connection relationship of bus type.Fig. 6 shows the storage battle array
The schematic three dimensional views of column.
Second of embodiment:
Referring to figs. 7 and 8, the basic storage module of present embodiment further includes controllable in addition to storage circuit and I/O circuit
Interconnection line, the interconnection line being different from Fig. 3.In Fig. 7, controllable interconnection line is to haveThe arrow of label is shown,Label indicates
Switch realizes the control to interconnection line on-off by control switch.The control terminal of switch is at the top of each memory module unit
I/O interface at draw.
Fig. 9 shows one 2 × 2 memory cell array, will be other than black dotted lines by configuring intarconnected cotrol circuit
The switch of each controllable interconnection line disconnects, i.e., inactivates the interconnection line other than dotted line, or to close, " disable " is equivalent to
Connection relationship shown in Fig. 10, that is, form bus type connection.
Embodiment 1: referring to Figure 11.The arrow of Figure 11 is the simplification representation of controllable interconnection line.
The semiconductor memory preparation method of the present embodiment includes the following steps:
A, using semiconductor integrated circuit manufacturing process, basic storage module array is made on wafer, it is each to deposit substantially
Storage module includes the storage circuit of an I/O circuit and the predetermined volumes connecting with I/O circuit.Figure 11 shows 4 × 4=16 and deposits
The I/O interface of storage unit, the I/O circuit D of the adjacent storage unit of orthogonal direction is connected by controllable interconnection line；
B, it according to scheduled storage chip capacity, determines the quantity for the storage unit for being included in storage chip, then draws
Piece separates storage chip.
C, isolated storage chip is packaged；
For example, the capacity of scheduled each basic storage module is 1G in step a, production capacity is the chip of 4G, then edge
The dotted line scribing of Figure 11, forms the chip of 4 4G.The interconnection line that chip edge position will be cut off when scribing, draws for having no
It is necessary out, in configuration, disconnection is switched by the control circuit (i.e. intarconnected cotrol circuit) of switch.
Further, the basic storage module of each minimum capacity unit can be written only in test or initialization
Address (Chip ID) (is programmed) by NVM or otp memory.Enable (connection) when controllable interconnection line can pass through initialization
Or Disable (disconnection).Each basic storage module is in addition to complete store function, and there are also complete perimeter bonding pads
(bounding pads)。
It include at least two basic storage modules based on the chip of the technology of the present invention preparation referring to Figure 12, it is each to deposit substantially
The I/O interface for storing up module forms bus type connection by interconnection line.After being encapsulated as chip, I/O interface is connected to external storage control
Circuit, external storage control circuit complete the functions such as addressing as bus control circuit.
Different from " memory chip that a kind of mask can only prepare a kind of specified vol " of the prior art, the present invention is only needed
The mask for corresponding to single basic storage module is wanted, reuse can produce basic storage module battle array on wafer
Column form memory module group, the encapsulation of memory module group according to demand capacity scribing in the subsequent technique after array completes
The memory chip for becoming demand capacity size afterwards realizes " memory chip of a variety of capacity is prepared with a kind of mask "
Effect.The present invention establishes the interconnection between basic storage module in wafer level, has the characteristics that high speed high reliability.
Claims (7)
1. semiconductor memory preparation method, includes the following steps:
A, using semiconductor integrated circuit manufacturing process, basic storage module array, basic storage module tool are made on wafer
There is I/O circuit interface；
B, to Wafer Dicing, storage chip is obtained；
C, isolated storage chip is packaged；
It is characterized by:
In the step a, the I/O circuit interface of the adjacent basic storage module of orthogonal direction is connected by interconnection line；
The step b is, according to scheduled storage chip capacity, to determine the number for the basic storage module for being included in storage chip
The position of amount and storage chip edge line, then along storage chip edge line scribing, while cutting off the interconnection line of bounding edge line,
Storage chip is whole from wafer separate.
2. semiconductor memory preparation method as described in claim 1, which is characterized in that further include following step:
To the memory block writing unit identification information of each basic storage module.
3. semiconductor memory preparation method as described in claim 1, which is characterized in that
In the step a, switch is provided on interconnection line；
Further include following step after step a: according to presetting, initializing the state of each switch.
4. semiconductor memory preparation method as described in claim 1, which is characterized in that further include following in the step b
Sub-step: the switch state on the interconnection line at chip edge line is set as turning off.
5. semiconductor memory preparation method as described in claim 1, which is characterized in that further include following step: to storage
Basic storage module within chip edge line is tested one by one, for abnormal basic storage module, is cut off it and is connected to normally
The interconnection line of basic storage module.
6. semiconductor memory preparation method as described in claim 1, which is characterized in that the I/O circuit interface includes at least
One of following types: data line, control line, address wire.
7. using the semiconductor memory of the preparation of semiconductor memory preparation method described in claim 1,2,3,4,5 or 6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910592710.0A CN110491785A (en) | 2019-07-03 | 2019-07-03 | Semiconductor memory preparation method and semiconductor memory |
| PCT/CN2020/070436 WO2021000560A1 (en) | 2019-07-03 | 2020-01-06 | Semiconductor memory preparation method and semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910592710.0A CN110491785A (en) | 2019-07-03 | 2019-07-03 | Semiconductor memory preparation method and semiconductor memory |
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| Publication Number | Publication Date |
|---|---|
| CN110491785A true CN110491785A (en) | 2019-11-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910592710.0A Pending CN110491785A (en) | 2019-07-03 | 2019-07-03 | Semiconductor memory preparation method and semiconductor memory |
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|---|---|
| CN (1) | CN110491785A (en) |
| WO (1) | WO2021000560A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021000560A1 (en) * | 2019-07-03 | 2021-01-07 | 成都皮兆永存科技有限公司 | Semiconductor memory preparation method and semiconductor memory |
| US20220037207A1 (en) * | 2020-08-01 | 2022-02-03 | Jack Zezhong Peng | Method for fabricating semiconductor memory and the semiconductor memory |
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| US6078096A (en) * | 1997-03-31 | 2000-06-20 | Sharp Kabushiki | Semiconductor integrated circuit device having a short circuit preventing circuit |
| CN1314702A (en) * | 2000-03-21 | 2001-09-26 | 日本电气株式会社 | Producing system of semiconductor storage and method for producing semiconductor storage |
| CN1463036A (en) * | 2001-07-10 | 2003-12-24 | 株式会社东芝 | Chip of memory, chip-on-chip device of using same and its mfg. method |
| CN2613887Y (en) * | 2003-02-22 | 2004-04-28 | 鲍刚 | Card type semiconductor memory |
| CN1716602A (en) * | 2004-06-29 | 2006-01-04 | 尔必达存储器股份有限公司 | Stacked semiconductor memory device |
| CN109559779A (en) * | 2017-09-26 | 2019-04-02 | 三星电子株式会社 | Semiconductor memory system and the method for operating semiconductor memory system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491785A (en) * | 2019-07-03 | 2019-11-22 | 成都皮兆永存科技有限公司 | Semiconductor memory preparation method and semiconductor memory |
-
2019
- 2019-07-03 CN CN201910592710.0A patent/CN110491785A/en active Pending
-
2020
- 2020-01-06 WO PCT/CN2020/070436 patent/WO2021000560A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6078096A (en) * | 1997-03-31 | 2000-06-20 | Sharp Kabushiki | Semiconductor integrated circuit device having a short circuit preventing circuit |
| CN1314702A (en) * | 2000-03-21 | 2001-09-26 | 日本电气株式会社 | Producing system of semiconductor storage and method for producing semiconductor storage |
| CN1463036A (en) * | 2001-07-10 | 2003-12-24 | 株式会社东芝 | Chip of memory, chip-on-chip device of using same and its mfg. method |
| CN2613887Y (en) * | 2003-02-22 | 2004-04-28 | 鲍刚 | Card type semiconductor memory |
| CN1716602A (en) * | 2004-06-29 | 2006-01-04 | 尔必达存储器股份有限公司 | Stacked semiconductor memory device |
| CN109559779A (en) * | 2017-09-26 | 2019-04-02 | 三星电子株式会社 | Semiconductor memory system and the method for operating semiconductor memory system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021000560A1 (en) * | 2019-07-03 | 2021-01-07 | 成都皮兆永存科技有限公司 | Semiconductor memory preparation method and semiconductor memory |
| US20220037207A1 (en) * | 2020-08-01 | 2022-02-03 | Jack Zezhong Peng | Method for fabricating semiconductor memory and the semiconductor memory |
| US11721585B2 (en) * | 2021-08-02 | 2023-08-08 | Jack Zezhong Peng | Method for fabricating semiconductor memory and the semiconductor memory |
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| Publication number | Publication date |
|---|---|
| WO2021000560A1 (en) | 2021-01-07 |
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Application publication date: 20191122 |