JPH07221180A - Interlayer connecting structure and forming method thereof in semiconductor device - Google Patents

Abstract

PURPOSE:To provide the method forming of interlayer connecting structure requiring neither of the margin left for miss alignment of a stepper and the dispersion in the processing dimensions nor of the buried contact holes. CONSTITUTION:A connecting part forming layer 15 is deposited on a lower wiring layer 13 through the intermediary of an intermediate layer 14 and then patterned firstly to be processed in a wiring shape, later, the connecting part forming layer 15 excluding the connecting parts 15 a is removed to form the connecting parts 15a. Next, an interlayer insulating film 17 is buried in the removed parts excluding the connecting parts 15a so that upper wiring layers 18 may be formed on the interlayer insulating film 17 in the electrically connected state with the connecting parts 15a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlayer connection structure in a semiconductor device and a method for forming the same, and more particularly to an interlayer connection structure for connecting wiring layers in a semiconductor device having a multilayer wiring structure and a method for forming the same.

[0002]

2. Description of the Related Art In the manufacture of LSIs and VLSIs, multilayer wiring and miniaturization are in progress. In the formation of the connection portion for connecting the wiring layers in this multilayer wiring structure, as shown in FIG. 9, the wiring 93 in the lower layer is the same as the size (diameter) D of the connection hole 92 formed in the interlayer insulating film 91. When the size (width) L is about the same, the connection hole 92 is displaced from the wiring 93 due to variations in processing dimensions and misalignment of the stepper, so-called trenching occurs.

The portion where the trenching occurs has a high aspect ratio and remains as a void, which is not preferable. Therefore, conventionally, as shown in FIG.
By increasing the width of the wiring 93 as the tray of the connection hole 92, the margin M for the misalignment of the stepper and the variation of the processing dimension is secured.

[0004]

However, if the margin M for the misalignment of the stepper and the variation of the processing dimension is secured, the wiring 93 cannot be formed at the minimum processing dimension at the place where the connection hole 92 is formed, so that the degree of integration is lowered. There was a problem. That is, in FIG. 11, the minimum processing dimension is S1, whereas the wiring interval S2 in the portion where the connection hole 92 does not exist requires S2 = S1 + 2M. In general, the margin (so-called wiring cover) M for misalignment of steppers and variations in processing dimensions is
About 0.1 to 0.2 μm is required. Particularly, in the case of a gate array or the like, this wiring pitch S2 is
Since it is the main factor that determines the (Grid) interval, it also affects the size of the entire chip.

Further, in the conventional method of forming the interlayer connection structure, after forming the connection hole, the connection portion between wiring layers (so-called embedded plug) is formed by embedding a conductive material such as tungsten. However, in the above-described conventional forming method, since the connection hole tends to become smaller along with the miniaturization, the aspect ratio is unavoidably increased, and thus there is a problem that embedding defects and the like are likely to occur.

For this reason, there is a tendency to use a CVD (chemical vapor deposition) method or the like instead of the sputtering method for burying the connection hole, but the CVD method raises the chip cost as compared with the sputtering method. Further, even if the CVD method is used to fill the connection hole, the metal layer such as a so-called barrier metal or adhesion layer is actually deposited by the sputtering method, so that the coverage of the connection portion is deteriorated. After all, a defective embedding occurs.

Further, when, for example, tungsten (W) is used as the conductive material to be embedded in the connection hole, there are the following problems. That is, as the plug forming method using tungsten, not only the contact hole but also the W
There is a blanket W-CVD method for forming a film. In this blanket W-CVD process, from the viewpoint of adhesion between the interlayer insulating film and the W film, as shown in FIG. 12, W is formed on the interlayer insulating film 95 laminated on the lower wiring layer 94.
Before forming the film 96, it is necessary to form the adhesion layer 97 made of a titanium-based conductive material such as Ti or TiN.

As is apparent from FIG. 12, the adhesion layer 97 is formed not only on the flat surface but also on the inner wall inside the connection hole 98. Reference numeral 99 is an upper wiring layer.
However, if a titanium-based material having a resistivity higher than that of tungsten is present in the connection hole 98, there is a problem in that the amount of charge handled in the connection hole is reduced accordingly. As an example, the resistivity of tungsten is 5.6.
5 × 10 ^-6 Ωcm, the resistivity of titanium is 42.0 × 10 ^-6
Ωcm.

Further, when tungsten is embedded in the connection hole 98, the orientation becomes perpendicular to the bottom surface and the inner peripheral surface of the connection hole 98, and the orientation in the connection hole 98 is not aligned in a fixed direction. There are problems that the resistance of the part becomes high, the path when the current flows is not constant, and the heat is generated by concentrating partially.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an interlayer connection structure in a semiconductor device capable of setting a large amount of charge to be handled in a connection portion between wiring layers. is there. A further object of the present invention is to provide a method for forming an interlayer connection structure in a semiconductor device, which does not require a margin for misalignment of steppers and variations in processing dimensions, and does not require burying of connection parts.

[0011]

An interlayer connection structure according to claim 1 is an interlayer connection structure for connecting between wiring layers in a semiconductor device having a multilayer wiring structure, wherein a lower wiring layer and a lower wiring layer are formed on the lower wiring layer. Connection consisting of a laminated interlayer insulating film, an upper wiring layer formed on the interlayer insulating film, and a single metal layer that penetrates the interlayer insulating film and electrically connects the upper wiring layer and the lower wiring layer And a section.

According to a second aspect of the present invention, there is provided a method for forming an interlayer connection structure, which comprises a step of sequentially depositing a lower wiring layer and a connection portion forming layer and patterning the wiring layers at the same time to perform wiring processing, and a step of patterning the connection portion forming layer to form the connection portion. And a step of filling a portion other than the connecting portion with an interlayer insulating film, and a step of forming an upper wiring layer on the interlayer insulating film while being electrically connected to the connecting portion. And

According to a third aspect of the present invention, there is provided a method of forming an interlayer connection structure, which comprises sequentially depositing a lower wiring layer and a connection portion forming layer, patterning the connection portion forming layer to form a connection portion, and connecting the connection portion. Patterning the lower wiring layer by using as a part of the mask to process the wiring, a step of filling the portion other than the connecting portion with an interlayer insulating film, and a state in which the connecting portion is electrically connected to the interlayer insulating film. And a step of forming an upper wiring layer.

The method for forming an interlayer connection structure according to claim 4 is the method for forming an interlayer connection structure according to claim 2 or 3, wherein an intermediate layer made of a conductive material is provided between the lower wiring layer and the connection part formation layer. It is characterized by arranging.

[0015]

In the interlayer connection structure according to claim 1, since the connecting portion connecting the wiring layers is made of a single metal layer, the amount of charge handled at the connecting portion is the resistance of the material of the single metal layer forming the connecting portion. It depends only on the rate. Therefore, by using, for example, tungsten having a low resistivity as the material of the single metal layer, it is possible to set the handling charge amount of the connection portion to be large.

In the method for forming an interlayer connection structure according to claim 2, after depositing a connection portion forming layer on the lower wiring layer in advance, patterning is performed to form a wiring shape, and then the connection portion forming layer is patterned. The connection portion is formed by removing the connection portion forming layer other than the connection portion. Then, the removed portion other than the connection portion is filled with an interlayer insulating film, and the upper wiring layer is formed thereon in a state of being electrically connected to the connection portion.

As a result, a margin for misalignment of steppers and variations in processing dimensions is not required, so that the space between wirings can be reduced to the minimum processing dimension and high integration can be achieved. Further, since it is not necessary to embed the connecting portion as in the conventional case, there is no defective embedding of the connecting portion, the yield is high, and metal sputtering is sufficient instead of metal CVD, which is inexpensive.

In the method of forming an interlayer connection structure according to a third aspect of the present invention, a lower wiring layer and a connecting portion forming layer are sequentially deposited, and the connecting portion forming layer is first patterned to form a connecting portion.
Then, the lower wiring layer is patterned by using both the resist and the connection portion as a mask to form the wiring shape, the removed portion is filled with an interlayer insulating film, and the upper wiring layer is electrically connected to the connection portion. It is formed in the state.

As a result, even if the connecting portion is misaligned with the lower layer wiring, the wiring shape can be corrected by the amount of the displacement of the connecting portion, and the side surface of the lower layer wiring and the side surface of the connecting portion can always be machined so as to be flush with each other. Therefore, the contact area between the lower layer wiring and the connection portion is always constant, and variations in resistance can be suppressed.
Further, since no margin is required for misalignment of steppers and variations in processing dimensions, the inter-wiring space can be reduced to the minimum processing dimension, and high integration can be achieved.
Furthermore, since it is not necessary to embed the connecting portion, there is no defective embedding of the connecting portion, the yield is high, and the metal CV
Even if it is not D, metal sputtering is sufficient and it is inexpensive.

In the method of forming an interlayer connection structure according to claim 4, the intermediate layer disposed between the lower wiring layer and the connection part formation layer is formed when the connection part formation layer is patterned to form the connection part. Acts as a stopper. Further, this intermediate layer also acts as a reinforcement of the EM (electro migration) resistance of the lower wiring layer, and also acts as an antireflection film when wiring the lower wiring layer. Further, by disposing the intermediate layer, when detecting the end point during etching of the connection portion forming layer, a difference in emission intensity occurs between the connection portion forming layer and the intermediate layer, which facilitates the end point detection. .

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1A to 1D are process diagrams of the manufacturing process according to the first embodiment of the present invention. First, Fig. 1
In (a), the lower wiring layer 13, the intermediate layer 14, and the connection portion forming layer 15 are sequentially deposited on the interlayer insulating film 11 with the barrier metal 12 interposed therebetween. The barrier metal 12 is for reinforcing the EM resistance of the lower wiring layer 13. As the barrier metal 12, a titanium-based conductive material such as Ti or TiN, or a laminated structure thereof is generally used. If the lower wiring layer 13 can be used as a substitute, the barrier metal 12 may be omitted. The lower wiring layer 13 has low resistance and EM
Highly resistant material such as Al, Al-Si, Al-Si
-A wiring material such as Cu.

The intermediate layer 14 includes the connecting portion forming layer 15 and the RIE.
(reactive ion etching) Made of materials with a high selection ratio,
It acts as a stopper when forming the connection portion, acts as a reinforcement of the EM resistance of the lower wiring layer 13 like the barrier metal 12, and also acts as an antireflection film when wiring the lower wiring layer 13. Eggplant Further, by disposing the intermediate layer 14, a difference in emission intensity is generated between the connection portion forming layer 15 and the intermediate layer 14 at the time of detecting the end point when the connection portion forming layer 15 is etched. The action and effect of facilitating As a material of the intermediate layer 14,
A titanium-based conductive material such as Ti, TiN, or TiON is used.

As the material of the connecting portion forming layer 15, not only tungsten (W) but also a Ti or Al-based conductive material is used. In the above laminated structure, after wiring is performed with the lower layer wiring pattern 21 having the shape shown in FIG. 2, a resist pattern 22 having the shape shown in the same figure is formed. Here, if the lower layer wiring is about the same size as the connection portion, the resist pattern 22 is set to cover the lower layer wiring pattern 21. Although not shown, if the lower layer wiring is sufficiently large, a square pattern of which one side is d may be used. When the lower layer wiring pattern 21 is thin, setting the resist pattern 22 as shown in FIG. 2 can guarantee the misalignment between the left and right sides in FIG. Further, even when the components are misaligned downward, there is no problem in practical use because only the cross-sectional area of the connecting portion is reduced.

FIG. 1A shows an example in which a misalignment of M'to the right occurs. In this state, the resist 16 is used as a mask, and only the connecting portion forming layer 15 is etched by RIE using the intermediate layer 14 as a stopper to form a connecting portion (plug) 15a as shown in FIG. 1B. In order to facilitate understanding of the structure, stereoscopic images corresponding to FIGS. 1 (a) and 1 (b) are shown in FIGS. 3 (a) and 3 (b). In this way
The connection portion 15a is formed in the same process as the lower wiring layer 13.

After that, as shown in FIG. 1C, a portion other than the connecting portion 15a is filled with an interlayer insulating film 17. In the process of forming the interlayer insulating film 17, SOG (spin on glass)
Well-known planarization methods such as the s) method and CMP (chemical mechanical polish) method may be used, and the interlayer insulating film 17 is formed so that only the connecting portion 15a is exposed regardless of which planarization method is used. When the CMP method is used, the connecting portion 15a can be used as a polishing stopper.

Then, as shown in FIG. 1D, the upper wiring layer 18 is formed in a state of being electrically connected to the connecting portion 15a. At this time, if the upper wiring layer 18 and the connecting portion 15a are made of a material having a selective ratio, the upper wiring layer 18 also connects to the connecting portion 15a.
No covering is required for a.

As described above, the connection portion forming layer 15 is deposited on the lower wiring layer 13 in advance and then patterned to be processed into a wiring shape. Then, the connection portion forming layer 15 is patterned to be more than the interlayer insulating film 17. First, the connection portion 15a is formed,
By filling the portion other than the connection portion 15a removed by this patterning with the interlayer insulating film 17, a margin for misalignment of the stepper and variations in processing dimensions is not required, so that the inter-wiring space is
As shown in FIG. 2, it becomes S3. This space S between wiring
3 can be reduced to the minimum processing size. Therefore, high integration is possible.

Further, since sputtered metal can be used as the material for the fine connection portion as well, it is inexpensive, and since the etching back of the connection portion forming layer 15 is not required, the height variation of the connection portion 15a is small. Also, the number of steps is reduced, and seams and voids do not occur. Furthermore, FIG.
(A), the so the cross-sectional shape of the connecting portion 15a can be formed in a rectangular cross section than that of the circular conventional ^{(b) (1-π 2} /4) d 2 have spread sectional area , The current density also decreases. Therefore, the EM resistance increases and the resistance also decreases.

FIGS. 5A to 5C and FIG. 6A,
FIG. 6B is a process diagram of the manufacturing process according to the second embodiment of the present invention. First, in FIG. 5A, the lower wiring layer 3 is formed on the interlayer insulating film 31 with the barrier metal 32 interposed therebetween.
3, intermediate layer 34, connection portion forming layer 35 and stopper 36
Are sequentially deposited.

The barrier metal 32 is for reinforcing the EM resistance of the lower wiring layer 33. As the barrier metal 32, a material excellent in EM resistance such as Ti
Generally, a titanium-based conductive material such as TiN or TiN, or a laminated structure thereof is used. The barrier metal 32 may be omitted if the lower wiring layer 33 can be substituted.

The lower wiring layer 33 is made of a material having a low resistance and a high EM resistance, such as Al, Al-Si, Al-.
A wiring material such as Si-Cu is used. Middle layer 34
Is made of a material having a RIE selectivity with respect to the connection portion forming layer 35. By arranging the intermediate layer 33 between the lower wiring layer 33 and the connection portion forming layer 35, it is possible to obtain the same action and effect as in the case of the above embodiment. As a material for the intermediate layer 34, a titanium-based conductive material such as Ti, TiN, or TiON is used.

As the material of the connecting portion forming layer 35, not only W but also Ti or Al based conductive material is used. As the stopper 36, the barrier metal 32, the lower wiring layer 33
And a material that can act as a mask when the intermediate layer 34 is etched by RIE, such as SiN or SiO.
₂ etc. are used. All of these metal materials are inexpensive when formed by a sputtering method. After depositing the film having the above-mentioned laminated structure, the resist 37 for forming the connection portion is patterned.

Next, the connecting portion forming layer 35 is etched by RIE using the intermediate layer 34 as a stopper. At this time, if the stopper 36 is made of SiN or SiO _2, it is usually different from the device that performs RIE on the connection portion forming layer 35. Therefore, the stopper 36 is first RIEed and then the connection part forming layer 35 is RIEed as it is, or after the resist is once peeled off, the stopper 36a is used as a mask to form the connection part forming layer 3
RIE 5 As a result, the connecting portion 35a is formed. Which method is used is arbitrary.

In FIG. 5C, the lower wiring 33 is resist-patterned. In the figure, it is assumed that a misalignment occurs in the right direction. In this state, the intermediate layer 34, the lower wiring layer 33 and the barrier metal 32 are exposed to R by using the resist 38 and the stopper 36 as a mask.
Etching by IE and processing into a wiring shape as shown in FIG. 6A (32a to 34a). At this time, since the stopper 36a exists in the connecting portion 35a, the wiring shape can be represented by a logical expression of (wiring data) and (connection portion data).

Next, in FIG. 6B, an interlayer insulating film 39 is formed on the portion other than the connection portion 35a which is removed by patterning. The interlayer insulating film 39 is flattened so that the connection portion 35a is exposed. As the flattening method at this time, a well-known SOG method or CMP method can be used, but the CMP method is most effective, and the connection portion 35 is used.
Since a can be used as a CMP stopper, it is possible to suppress variations in film thickness of the interlayer insulating film 39. An upper wiring layer is formed on the interlayer insulating film 39 while being electrically connected to the connection portion 35a. The description of the formation of the upper wiring layer is omitted here.

As described above, the lower wiring layer 33 and the connecting portion forming layer 35 are sequentially deposited, the connecting portion forming layer 35 is first patterned to form the connecting portion 35a, and then both the resist 38 and the connecting portion 35a are formed. By patterning the lower wiring layer 33 using the mask as a mask and processing the lower wiring 33a, even if the connecting portion 35a is misaligned with the lower wiring 33a as shown in FIG. 7B,
The wiring shape can be corrected by an amount corresponding to the displacement of the connection portion 35a, and the side surface of the lower layer wiring 33a and the side surface of the connection portion 35a can be processed so as to be flush with each other.

Therefore, the lower wiring 33a and the connecting portion 35 are
The contact area of a is always constant, and the variation in resistance can be suppressed. Further, since a margin for misalignment of steppers and variations in processing dimensions is not required, high integration can be achieved. Further, since it is not necessary to embed the connecting portion 35a, there is no defective embedding of the connecting portion 35a, the yield is high, and metal sputtering is sufficient instead of metal CVD, which is inexpensive.

In the interlayer connection structure formed by the forming method of each of the above embodiments, as is clear from FIG.
The connecting portion 44 that penetrates the interlayer insulating film 41 and electrically connects the lower wiring layer 42 and the upper wiring layer 43 is formed by a single metal layer made of, for example, tungsten (W). As a result, the amount of charge handled by the connecting portion 44 is determined only by the resistivity of tungsten, which is the material forming the connecting portion 44. Therefore, as shown in the conventional example of FIG. 12, compared with the case where the titanium-based adhesion layer 97 is present in the connection hole 98 in addition to the plug material (W), the amount of charge handled in the connection portion 44 is large. It can be set.

Further, in the forming method of each of the above embodiments,
When depositing the connecting portion forming layers 15 and 35, a conductive material such as tungsten is deposited on a flat underlayer (intermediate layers 14 and 34), so that the orientation of the connecting portion 44 becomes vertical to the underlayer. Since they are aligned in one direction, the resistance of the connection portion 44 is reduced, the path of the current is constant, and heat is not concentrated and concentrated in a part as in the conventional case.

[0040]

As described above, according to the first aspect of the present invention, since the connecting portion connecting the wiring layers is composed of the single metal layer, the handling charge amount of the connecting portion forms the connecting portion. Since it is determined only by the resistivity of the material of the single metal layer,
It is possible to set the handling charge amount of the connecting portion to be larger than that of the conventional connecting portion including the adhesion layer.

According to the second aspect of the present invention, after depositing the connecting portion forming layer on the lower wiring layer, the connecting portion forming layer is patterned to be processed into a wiring shape first, and then the connecting portion forming layer is patterned to form a portion other than the connecting portion. The connection part is formed by removing the connection part formation layer, and thereafter, the part other than the connection part is filled with an interlayer insulating film, and the upper wiring layer is formed on the connection part in a state of being electrically connected to the connection part. As a result, a margin for misalignment of the stepper and fluctuation of the processing size is not required, so that the space between the wirings can be reduced to the minimum processing size and high integration can be achieved. Further, since it is not necessary to bury the connecting portion, there is no defective filling of the connecting portion, the yield is high, and metal sputtering is sufficient instead of metal CVD, which is inexpensive.

According to the second aspect of the present invention, the lower wiring layer and the connecting portion forming layer are sequentially deposited, the connecting portion forming layer is first patterned to form the connecting portion, and then both the resist and the connecting portion are formed. By using the mask as a pattern, the lower wiring layer is patterned and processed into a wiring shape, the removed portion is filled with an interlayer insulating film, and the upper wiring layer is formed on it in a state of being electrically connected to the connecting portion. Even if there is a misalignment of the connection part with the lower layer wiring, the wiring shape can be corrected by the amount of the misalignment of the connection part and the side surface of the lower layer wiring and the side surface of the connection part can be machined so that the side surface of the lower layer wiring and the side surface of the connection part can always be machined. The contact area of the parts is always constant, and variations in resistance can be suppressed.

Further, since no margin is required for misalignment of steppers and variation in processing size, the space between wirings can be reduced to the minimum processing size and high integration can be achieved. Further, since it is not necessary to embed the connecting portion, there is no defective embedding of the connecting portion, the yield is high, and metal sputtering is sufficient instead of metal CVD, which is inexpensive.

According to the fourth aspect of the present invention, the intermediate layer is arranged between the lower wiring layer and the connecting portion forming layer, so that the intermediate layer patterns the connecting portion forming layer to form the connecting portion. Not only can it be used as a stopper when forming, but it can also be used as an antireflection film when reinforcing the EM resistance of the lower wiring layer and when processing the wiring of the lower wiring layer. In addition, by disposing the intermediate layer, a difference in emission intensity occurs between the connection portion forming layer and the intermediate layer at the time of detecting the end point during etching of the connection portion forming layer, which facilitates the end point detection. You can also get the effect.

[Brief description of drawings]

FIG. 1 is a process drawing of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a pattern diagram showing a lower layer wiring pattern and a resist pattern.

FIG. 3 is a perspective view showing a three-dimensional image of a manufacturing process.

FIG. 4 is a cross-sectional view of a connecting portion.

FIG. 5 is a process diagram (1) of the manufacturing process according to the second embodiment of the present invention.

FIG. 6 is a process diagram (2) of the manufacturing process according to the second embodiment of the present invention.

FIG. 7 is a plan pattern diagram showing a positional relationship between a lower layer wiring and a connection portion.

FIG. 8 is a cross-sectional view showing an interlayer connection structure according to the present invention.

FIG. 9 is a cross-sectional view showing a conventional example (No. 1).

FIG. 10 is a sectional view showing a conventional example (No. 2).

FIG. 11 is a plan view showing a conventional example (No. 2).

FIG. 12 is a sectional view showing a conventional example (No. 3).

[Explanation of symbols]

 11, 17, 31, 39, 41 Interlayer insulating film 12, 32 Barrier metal 13, 33, 42 Lower wiring layer 14, 34 Intermediate layer 15, 35 Connection part forming layer 15a, 35a, 44 Connection part 16, 37, 38 Resist 18,43 Upper wiring layer

Claims (4)

[Claims] 1. An interlayer connection structure for connecting respective wiring layers in a semiconductor device having a multilayer wiring structure, comprising: a lower wiring layer; an interlayer insulating film laminated on the lower wiring layer; and an interlayer insulating film on the interlayer insulating film. An interlayer comprising a formed upper wiring layer and a connecting portion formed of a single metal layer that penetrates the interlayer insulating film and electrically connects the upper wiring layer and the lower wiring layer. Connection structure. 2. A method for forming an interlayer connection structure for connecting wiring layers in a semiconductor device having a multilayer wiring structure, which comprises depositing a lower wiring layer and a connection portion forming layer in sequence and simultaneously patterning and processing the wiring. A step of patterning the connecting portion forming layer to form a connecting portion, a step of filling a portion other than the connecting portion with an interlayer insulating film, and a state of being electrically connected to the connecting portion on the interlayer insulating film. And a step of forming an upper wiring layer. 3. A method of forming an interlayer connection structure for connecting wiring layers in a semiconductor device having a multilayer wiring structure, which comprises depositing a lower wiring layer and a connection portion formation layer in order, and patterning the connection portion formation layer. To form a connection part, a step of patterning the lower wiring layer by using the connection part as a part of a mask to perform a wiring process, a step of filling a part other than the connection part with an interlayer insulating film, And a step of forming an upper wiring layer in a state of being electrically connected to the connection portion on an insulating film. 4. The method for forming an interlayer connection structure according to claim 2 or 3, wherein an intermediate layer made of a conductive material is arranged between the lower wiring layer and the connection part formation layer. Method of forming connection structure.