JPH0722070B2 - Ceramic capacitor and manufacturing method thereof - Google Patents

Ceramic capacitor and manufacturing method thereof

Info

Publication number
JPH0722070B2
JPH0722070B2 JP6087791A JP6087791A JPH0722070B2 JP H0722070 B2 JPH0722070 B2 JP H0722070B2 JP 6087791 A JP6087791 A JP 6087791A JP 6087791 A JP6087791 A JP 6087791A JP H0722070 B2 JPH0722070 B2 JP H0722070B2
Authority
JP
Japan
Prior art keywords
capacitor
capacity
manufacturing
capacitance
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6087791A
Other languages
Japanese (ja)
Other versions
JPH04255206A (en
Inventor
洋一 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JUDEN KENKYUSHO KK
Original Assignee
JUDEN KENKYUSHO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JUDEN KENKYUSHO KK filed Critical JUDEN KENKYUSHO KK
Priority to JP6087791A priority Critical patent/JPH0722070B2/en
Publication of JPH04255206A publication Critical patent/JPH04255206A/en
Publication of JPH0722070B2 publication Critical patent/JPH0722070B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は容量誤差の非常に少な
ラミックコンデンサ及びその製造方法に関するもので
ある。
The present invention relates to have very small capacity error
It relates Se la ceramic capacitor and a manufacturing method thereof.

【0002】[0002]

【従来の技術】セラミックコンデンサは、磁器誘電体を
利用したもので、最近は電子部品の小型化の要求により
積層型のものが多く採用されている。この積層型のセラ
ミックコンデンサは、誘電体セラミックグリーンシート
上に内部電極となる導電膜を印刷形成し、このシートを
積層すると共に圧着し、所定の容量となるように型抜き
した後焼成し、焼結積層体の側面に内部電極膜を接続す
る外部引出電極を設けてコンデンサチップを形成し、更
に回路への実装に適するように電子部品化するものであ
る。 電子部品化手段は、ベース板に形成した一対の電極
膜に前記チップを接着し、電極膜には外部リード線を接
続し、外部リード線のみを突出せしめる状態でその他の
部分を樹脂でモールドしてなるものである。
2. Description of the Related Art Ceramic capacitors use a porcelain dielectric, and in recent years, a laminated type has been widely used due to a demand for miniaturization of electronic parts. In this multilayer ceramic capacitor, a conductive film to be an internal electrode is formed by printing on a dielectric ceramic green sheet, the sheets are stacked and pressure-bonded, die-cutting is performed to obtain a predetermined capacitance, and then firing and firing are performed. An external extraction electrode for connecting an internal electrode film is provided on the side surface of the bonded laminated body to form a capacitor chip, which is then made into an electronic component suitable for mounting on a circuit.
It The electronic component forming means adheres the chip to a pair of electrode films formed on the base plate , connects external lead wires to the electrode films, and molds other parts with resin in a state where only the external lead wires are projected. It will be.

【0003】[0003]

【発明が解決しようとする課題】ところで前記のコンデ
ンサ部品に使用される積層型のコンデンサチップや非積
層型のコンデンサチップでは、誘電体であるセラミック
の厚さ、型抜きに際しての微妙な面積の相違等の原因
で、一般に200PF程度の容量のもので±8%程度
製造上の容量誤差が生ずる。而もコンデンサ部品のコ
ンデンサチップは、単一のものを使用するので、コ
ンサチップ自体の容量誤差がそのまま電子部品としての
容量誤差となってしまう。このため電子部品としての
品歩溜りが悪いと共に、電子部品としても、そのコンデ
ンサ容量の許容誤差が必然的に大きくなってしまい、必
ずしも品質が良い電子部とは云えない。そこで本発明
は、容量誤差の少ないコンデンサを効率良く製出する手
段を提案したものである。
By the way, the above-mentioned conde
In multilayer capacitor chips and non-multilayer capacitor chips used for sensor parts, the cause may be the thickness of the ceramic, which is the dielectric material, and the subtle differences in area during die cutting.
In general, a capacitor having a capacity of about 200 PF causes a manufacturing capacity error of about ± 8%. In addition,
Capacitor chips, because it uses a single thing, co-down de
The capacitance error of the sensor chip itself is
There will be a capacity error. Therefore with the manufacturing <br/> Shinafu reservoir as an electronic component worse, as the electronic component, the tolerance of the capacitor capacitance becomes necessarily large, not be said necessarily the quality is good electronic components. Therefore, the present invention proposes a means for efficiently producing a capacitor with a small capacitance error.

【0004】[0004]

【課題を解決するための手段】本発明に係るセラミック
コンデンサは、セラミックコンデンサチップを内蔵した
電子部品に於いて、設計値容量の数分の一の容量にして
且つ予め容量を正確に測定し、その容量のプラスマイナ
スの製造誤差に応じて適宜分類した小容量のコンデンサ
チップを、前記各小容量コンデンサの製造時の容量誤差
を互いに補完して設計値容量と一致する所定数の組み合
わせとして内蔵したことを特徴とするものであるまた
前記のコンデンサに於いて、特にベース板背面にコンデ
ンサ容量微調整用の電極膜を形成したことを特徴とする
ものである。
A ceramic capacitor according to the present invention has a built-in ceramic capacitor chip.
For electronic parts, make the capacity a fraction of the design value capacity
In addition, the capacity is accurately measured in advance, and the capacity
Small-capacity capacitors appropriately classified according to manufacturing error
Capacitance error when manufacturing each small capacitance capacitor
A predetermined number of combinations that complement each other and match the design value capacity.
It is characterized in that it has built in as Align. Also
The above-mentioned capacitor is characterized in that an electrode film for fine adjustment of the capacitor capacity is formed on the back surface of the base plate.

【0005】また本発明に係るセラミックコンデンサの
製造方法は、特に内蔵するコンデンサチップを、設計容
量の数分の一の小容量のセラミックコンデンサチップを
組み合わせてなるもので、小容量のコンデンサチップを
焼成し、小容量のコンデンサチップを予め測定してその
容量のプラスマイナスの製造誤差に応じて分類し、この
小容量のコンデンサチップをその製造誤差を互いに補完
する所定数の組み合わせとして設計値と一致させ、前記
所定数のセラミックコンデンサチップを従前手法で電子
部品化してなることを特徴とするものであるまた前記
セラミックコンデンサの製造方法に於いて、ベース板
の背面に調整用電極膜を形成すると共に、微調整用電
極膜の面積が相違するベース板を複数形成し、小容量の
コンデンサチップの組み合わせで補完できない微小容量
誤差を補うベース板を選択して使用することを特徴とす
るものである。
Further, in the method for manufacturing a ceramic capacitor according to the present invention, the built-in capacitor chip is particularly designed.
A small capacity ceramic capacitor chip that is a fraction of the amount
It is a combination of small capacity capacitor chips.
After firing, measure a small-capacity capacitor chip in advance and
This is classified according to the manufacturing error of plus or minus of the capacity.
Small capacitor chips complement each other's manufacturing errors
Match the design value as a predetermined number of combinations
A predetermined number of ceramic capacitor chips are electronically
And it is characterized in that formed by part of. In the method of manufacturing a ceramic capacitor described above, a fine adjustment electrode film is formed on the back surface of the base plate, and a plurality of base plates having different areas of the fine adjustment electrode film are formed to reduce the capacity of the capacitor.
Minute capacitance that cannot be complemented by a combination of capacitor chips
The feature is that a base plate that compensates for an error is selected and used.

【0006】[0006]

【作用】小容量のコンデンサチップの容量に数%の誤差
があっても、プラス、マイナスの誤差を有するものを組
み合わせることによって全体の容量を設計値容量とする
ことができる。またベース板背面の調整用電極膜はコン
デンサチップの内部電極膜並びにコンデンサチップを接
続する電極膜との間に静電容量を構成することになり、
電極膜の面積の多少でコンデンサの全体の容量の微調整
が可能となる。
Even if the capacitance of the small-capacity capacitor chip has an error of several%, the total capacitance can be made the design value capacitance by combining those having the plus and minus errors. Further, the adjustment electrode film on the back surface of the base plate constitutes a capacitance between the internal electrode film of the capacitor chip and the electrode film connecting the capacitor chip,
The capacitance of the entire capacitor can be finely adjusted depending on the area of the electrode film.

【0007】[0007]

【実施例】次に本発明の実施例を積層型のセラミックコ
ンデンサの場合について,その製造手順に添って説明す
る。最初に積層型のセラミックコンデンサチップ1を形
成するもので,これは従来と同様に誘電体セラミックグ
リーンシート11上に内部電極膜12を印刷形成し,こ
のシートを積層すると共に圧着し,所定の大きさに型抜
きして焼成し,焼結後積層体の側面に交互に重ねた各電
極膜12と接続する外部引出電極13を設けて形成して
なるものである。このコンデンサチップ1を形成するに
際にして製出せんとするコンデンサの容量を例えば30
0PFとすると,前記コンデンサチップ1は三分の一の
容量となる100PFを基準として形成する。100P
Fのセラミックコンデンサチップ1は,その容量誤差を
最大±10%とすると,110〜90PFのものが製出
されることになる。そこで110〜90PFのチップ1
を各個測定して適当な分別例えば110〜108PFの
チップ1a,108〜106PFのチップ1b,106
〜104PFのチップ1c……92〜90PFのチップ
1jのように分別しておく。
Next, an embodiment of the present invention will be described in the case of a laminated type ceramic capacitor along with its manufacturing procedure. First, a laminated ceramic capacitor chip 1 is formed. This is the same as the conventional method, in which an internal electrode film 12 is printed and formed on a dielectric ceramic green sheet 11, and this sheet is laminated and pressure-bonded to a predetermined size. Further, it is formed by punching, firing, and sintering, and then providing external lead-out electrodes 13 connected to the alternately laminated electrode films 12 on the side surface of the laminated body. For example, when the capacitor chip 1 is formed, the capacity of the capacitor to be produced is 30
If 0PF is set, the capacitor chip 1 is formed with 100PF, which is one third of the capacitance, as a reference. 100P
If the capacitance error of the F ceramic capacitor chip 1 is ± 10% at the maximum, a ceramic capacitor chip 1 of 110 to 90 PF will be produced. So, the chip 1 of 110-90PF
Are individually measured and appropriately sorted, for example, 110 to 108PF chips 1a and 108 to 106PF chips 1b and 106.
.About.104 PF chip 1c ... Separated like 92 to 90 PF chip 1j.

【0008】また前記チップ1を組み込むベース板2
は,表面にチップ1を接着(ハンダ若しくは導電性接着
剤を用いる)する一対の電極膜21及び電極膜21と接
続してなる外部リード線22を設けると共に背面に調整
用電極膜23を設けたもので,特に調整用電極膜23の
面積の異なるベース板2a,2b……を形成しておく。
而して300PFの容量のコンデンサを製出せんとする
場合は,分別したチップ1a〜1jの間から例えば1b
(108〜106PF),1f(100〜98PF)1
j(94〜92PF)の三個を選択すると,これを並列
にベース板2に組み込むと容量は302〜296PFと
なる。そこで現実の容量を測定し,302PFに近い値
であるならば調整用電極膜23の面積の少ないベース板
を使用し,逆に296PFに近い値であったなら調整用
電極膜23の面積の大きいベース板を使用すると製出さ
れるコンデンサは300PFとなる。この様にしてコン
デンサチップ1b,1f,1jをベース板2に組み込ん
だ後,樹脂3でモールドして電子部品として供するもの
である。
A base plate 2 incorporating the chip 1
Is provided with a pair of electrode films 21 for adhering the chip 1 (using solder or a conductive adhesive) on the surface and an external lead wire 22 connected to the electrode film 21, and an adjustment electrode film 23 on the back surface. In particular, base plates 2a, 2b ... Having different areas of the adjustment electrode film 23 are formed.
When a capacitor having a capacity of 300 PF is not produced, for example, 1 b is selected from among the sorted chips 1a to 1j.
(108 to 106PF), 1f (100 to 98PF) 1
When three of j (94 to 92 PF) are selected and they are installed in parallel in the base plate 2, the capacity becomes 302 to 296 PF. Then, the actual capacitance is measured, and if the value is close to 302 PF, a base plate with a small area of the adjusting electrode film 23 is used. Conversely, if the value is close to 296 PF, the area of the adjusting electrode film 23 is large. If the base plate is used, the capacitor produced will be 300 PF. After the capacitor chips 1b, 1f, 1j are assembled in the base plate 2 in this manner, they are molded with the resin 3 to serve as electronic parts.

【0009】従ってコンデンサチップ1は特に厳密な容
量が請求されず、通常の製造誤差の範囲内で形成するれ
ば良く、これを誤差の大小プラスマイナスに応じて分別
すると共に、適宜組み合わせてその誤差を互いに補完し
て使用することで、より精度の良いコンデンサ電子部品
を得ることができる。而もコンデンサチップ1は適宜な
組み合わせによって無駄なく使用され、更にベース板2
の背面に形成した電極膜23の面積の調整によって1P
F単位での調整まで可能となったものである。またコン
デンサチップの並列接続となるため、共振尖鋭度Qが高
くなり、本発明品を使用した回路の感度が向上するもの
である。尚本発明は前記実施例に限定されるものでな
く、コンデンサチップは非積層型でも良く、更には一つ
のコンデンサに組み込むチップの数、並びにチップの分
別の範囲は任意に定めることができるものである。
Therefore, the capacitor chip 1 is particularly strict.
Do not charge the quantity and form within normal manufacturing error
You just need to sort this according to the size of the error plus or minus
And combine them appropriately to complement each other.
It is possible to obtain a more accurate capacitor electronic component by using the same . Thus even capacitor chip 1 is used without waste by appropriate combination, further base plate 2
1P by adjusting the area of the electrode film 23 formed on the back surface of the
It is also possible to make adjustments in F units. Further, since the capacitor chips are connected in parallel, the resonance sharpness Q is increased and the sensitivity of the circuit using the product of the present invention is improved. The present invention is not limited to the above embodiment, the capacitor chip may be a non-stacked type, and the number of chips to be incorporated in one capacitor and the range of chip separation can be arbitrarily determined. is there.

【0010】[0010]

【発明の効果】本発明は以上のように製出しようとする
コンデンサの数分の一の容量を有するコンデンサチップ
製出し、これをその容量の製造誤差に応じて分別した
製造誤差を互いに補完する組み合わせで、セラミツ
クコンデンサの製造上当然に生ずる容量誤差を吸収で
き、設計容量と誤差の少ない高品質のコンデンサ電子部
品を提供できると共に、コンデンサチップの無駄が無く
なり、製品歩留りも高めるものである。更にはチップを
組み込むベース板背面に電極膜を設けると、電極膜の面
積の大小で、微小容量の調整が可能となって、より精度
が高い高品質の製品を提供できるものである。
As described above, the present invention provides a capacitor chip having a capacitance which is a fraction of that of the capacitor to be produced.
The out Ltd., it was fractionated in accordance with this manufacturing error of its capacity
Later , the combination of manufacturing errors will complement each other.
Capacitance error that naturally occurs in the production of capacitor can be absorbed
, High quality capacitor electronics with less error than design capacity
Products can be provided, and there is no waste of capacitor chips.
It also increases the product yield. Furthermore the kick set the electrode film on the base plate back surface incorporating chip, the surface of the electrode film
Higher accuracy because it is possible to adjust a small capacity with the product size
Can provide high quality products.

【図面の簡単な説明】[Brief description of drawings]

【図1】コンデンサチップの一部裁断した斜視図であ
る。
FIG. 1 is a partially cutaway perspective view of a capacitor chip.

【図2】コンデンサ部品の製造の説明図である。FIG. 2 is an explanatory view of manufacturing a capacitor component.

【図3】コンデンサ部品の樹脂モールト前の側面図であ
る。
FIG. 3 is a side view of the capacitor component before the resin molding.

【図4】コンデンサ部品の外観図である。FIG. 4 is an external view of a capacitor component.

【符号の説明】[Explanation of symbols]

1,1a,1b……1j コンデンサチップ 2 ベース板 21 電極膜 22 外部リード線 23 調整用電極膜 3 樹脂 1, 1a, 1b ... 1j Capacitor chip 2 Base plate 21 Electrode film 22 External lead wire 23 Adjustment electrode film 3 Resin

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 ベース板の表面に一対の電極膜を形成
し、この電極膜間に焼成したセラミックコンデンサチッ
プを導電接着し、前記電極膜に外部リード線を接続する
と共に、外部リード線のみを外部に突出せしめて他の全
体を樹脂モールドしてなるセラミックコンデンサに於い
て、設計値容量の数分の一の容量にして且つ予め容量を
正確に測定し、その容量のプラスマイナスの製造誤差に
応じて適宜分類した小容量のコンデンサチップを、前記
各小容量コンデンサの製造時の容量誤差を互いに補完し
て設計値容量と一致する所定数の組み合わせとし、前記
電極膜間に導電接着してなることを特徴とするセラミッ
クコンデンサ。
1. A pair of electrode films are formed on the surface of a base plate.
The ceramic capacitor chip fired between the electrode films
Conductively adhere the cable to the electrode film and connect the external lead wire to the electrode film.
At the same time, in a ceramic capacitor made by projecting only the external lead wire to the outside and molding the other part with resin, set the capacitance to a fraction of the design value capacitance and set the capacitance in advance.
Accurately measure and to the manufacturing error of plus or minus of the capacity
The small-capacity capacitor chips appropriately classified according to
Compensating for the capacitance error during manufacturing of each small-capacity capacitor
And a predetermined number of combinations that match the design value capacity,
A ceramic capacitor characterized in that it is electrically conductively bonded between electrode films .
【請求項2】 請求項1記載のセラミックコンデンサに
於いて、ベース板背面にコンデンサ容量微調整用の電極
膜を形成したことを特徴とするセラミックコンデンサ。
2. The ceramic capacitor according to claim 1, wherein an electrode film for fine adjustment of the capacitor capacity is formed on the back surface of the base plate.
【請求項3】 設計容量の数分の一の小容量のセラミッ
クコンデンサチップを焼成し、小容量のコンデンサチッ
プを予め測定してその容量のプラスマイナの製造誤差
に応じて分類し、別にベース板の表面に一対の電極膜を
形成し、この電極膜間に前記小容量のコンデンサチップ
をその製造誤差を互いに補完する所定数の組み合わせと
して設計値と一致させ、前記所定数のセラミックコンデ
ンサチップを前記電極膜間に導電接着し、前記電極膜に
外部リード線を接続すると共に、外部リード線のみを外
部に突出せしめて樹脂モールドしてなることを特徴とす
るセラミックコンデンサの製造方法。
3. A small capacity ceramic which is a fraction of the design capacity.
The capacitor chip is fired to
Plus minus of a manufacturing error of its capacity measured in advance-flops
According to the above, a pair of electrode films are separately set on the surface of the base plate.
Forming the small capacitance capacitor chip between the electrode films
And a predetermined number of combinations that complement the manufacturing error
To match the design value and set the specified number of ceramic capacitors.
Sensor chip by conductive adhesion between the electrode films
Connect the external lead wires and disconnect only the external lead wires.
A method of manufacturing a ceramic capacitor, which is characterized in that it is made to project to a portion and resin-molded .
【請求項4】請求項3記載のセラミックコンデンサの製
造方法に於いて、ベース板の背面に調整用電極膜を形
成すると共に、微調整用電極膜の面積が相違するベース
板を複数形成し、小容量のコンデンサチップの組み合わ
せで補完できない微小容量誤差を補うベース板を選択し
て使用することを特徴とするセラミックコンデンサの製
造方法。
4. A ceramic capacitor according to claim 3 .
In the manufacturing method, a fine adjustment electrode film is formed on the back surface of the base plate, and a plurality of base plates having different areas of the fine adjustment electrode film are formed to combine a small capacity capacitor chip.
A method of manufacturing a ceramic capacitor, which comprises selecting and using a base plate that compensates for a minute capacitance error that cannot be compensated for .
JP6087791A 1991-02-06 1991-02-06 Ceramic capacitor and manufacturing method thereof Expired - Lifetime JPH0722070B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6087791A JPH0722070B2 (en) 1991-02-06 1991-02-06 Ceramic capacitor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6087791A JPH0722070B2 (en) 1991-02-06 1991-02-06 Ceramic capacitor and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH04255206A JPH04255206A (en) 1992-09-10
JPH0722070B2 true JPH0722070B2 (en) 1995-03-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP6087791A Expired - Lifetime JPH0722070B2 (en) 1991-02-06 1991-02-06 Ceramic capacitor and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0722070B2 (en)

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* Cited by examiner, † Cited by third party
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CN100555739C (en) 2004-08-03 2009-10-28 日立金属株式会社 Irreversible circuit element

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