JPH07220466A - Apparatus for controlling accessing to memory - Google Patents

Abstract

PURPOSE:To access a memory at higher speeds. CONSTITUTION:A judging circuit 125 checks a memory address fed from a CPU and latched by a latch circuit 103. In other words, it is checked whether a column address of the address is carried. As a result, if it is detected that the column address is carried, the address is specified by a RAS and a CAS to make access to a DRAM. If the address is not carried, the operation is switched to a first page mode and only the CAS is used to access the DRAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device, and more particularly to a memory access control device for high speed access to a bit map memory of a raster scan type image processing device such as a laser beam printer. .

[0002]

2. Description of the Related Art A conventional bit map memory controller (memory access circuit) in an image processing apparatus is shown in FIG.
It is configured like. When accessing for writing data under the control of the CPU (not shown), the latch circuit 203 latches the address given via the address bus 212 in accordance with the address latch signal 215, and the latch output 223 is sent to the adder circuit 204. By generating the address as the address of the next memory access and controlling the selectors 205 and 206 by the sequencer (SEQ) 202, the timing control as shown in FIG. 5 is performed. Further, the read modify write may be performed by the timing control as shown in FIG.

5 to 6, the numbers (0, 1, 2, ...) Affixed to the clock signal are numbers for convenience of description below, and are arbitrary times, for example, a clock. Used to count the time from "0".

In FIG. 4, 201 is a timing circuit for timing with a CPU (not shown) using a strobe signal and a clock signal 209, 211 is a start signal to a sequencer (SEQ) 202, and 216 is a low address. / Signal for switching the column address (COLE
N), 218 is data shifted by the shifter (SH) 207, 219 is data shifted out by the shifter (SH), 208 is shift data or shift-out data selected according to the ZND signal 217 from the SEQ 202 and the memory data 222 Is a selector that outputs.

[0005]

However, in the above-mentioned conventional example, as shown in the timing chart of FIG. 5, the data supplied via the data bus 213 is converted into the shift value supplied via the shift value bus 214. According to the shift, the shifter (SH) 207 shifts the output data, and when writing the output data to the memory, the carry output from the column address to the row address is detected by adding to the address output from the CPU (not shown). Since it has not been done, the RAS 220 is reissued every time. This is the same in the case of the read modify write shown in FIG. Therefore, there is a problem that the access speed to the memory does not increase. In the example shown in FIG. 5, it takes a time corresponding to 10 clocks for writing two data, and in the read modify write shown in FIG. 6, a time corresponding to 16 clocks for two read modify writes. Requires.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a memory access control device capable of high-speed access to a memory.

[0007]

To achieve the above object, the memory access control device of the present invention has the following configuration. That is, a memory access control device for controlling an access operation to a DRAM, wherein a latch means for latching a memory address input from an external device and a carry address from a column address for the memory address latched by the latch means. The memory access control device further comprises a discriminating means for discriminating whether or not occurs, and the operation mode capable of high-speed access is switched according to the discrimination result of the discriminating means.

[0008]

With the above structure, the present invention determines whether or not a carry from the column address occurs when accessing the DRAM, and according to the result of the determination, the DRAM can be accessed at high speed. , First page mode, nibble mode, or static column mode.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a DR which is a typical embodiment of the present invention.
It is a block diagram showing a configuration of a memory access circuit for controlling access to AM.

In FIG. 1, 101 is a CPU (not shown).
A timing circuit for timing with, 102 is a sequencer (SEQ) for controlling a series of operations, and 103 is a C
A latch circuit (LAT) for latching an address given by PU, 104 an adder circuit for generating an address at the time of DRAM access, 105 a circuit for generating RAS from the upper part of the address, and 106 a memory A circuit for generating an address, 107 is a barrel shifter (SH),
108 is a selector, 109 is a system clock, 110
Is a bus strobe signal output from the CPU, 111 is a start signal to the sequencer (SEQ) 102, 112 is an address bus, 113 is a data bus, 114 is a bus for inputting a shift value to the barrel shifter, and 115 is an address latch. Signal 116 is a signal (COLEN) for switching a row address / column address, 117 is a DRAM
This is a signal (ZND) that is enabled during access.

Further, 118 is a barrel shifter (SH) 10.
7 shifted data, 119 shifted data by barrel shifter, 120 RAS signal, 12
1 is a memory address, 122 is a data bus, 123 is a latched address, 124 is an output address of the adder circuit 104, 125 is a circuit for determining whether a column address of the latched address causes a carry, and 126 is a sequencer ( This signal returns to the SEQ) 102 whether or not there is a carry.

Next, an explanation of the operation of the circuit having the above configuration will be given with reference to FIG.
This is performed with reference to the timing chart shown in. In this embodiment, in the DRAM access, the operation mode is changed depending on whether or not a carry occurs, and when the carry does not occur, the operation is performed in the first page mode.

(1) When a carry occurs When this occurs, memory access is performed in the same manner as in the conventional method as shown in FIG.

(2) When carry does not occur In this case, the DRAM access timing is as shown in FIG. That is, when the address is latched, whether or not the column address (lower address) carries in the output of the adder circuit 104 is judged by the judging circuit 125, and the sequencer (SEQ) 102 has no carry. Inform. In this manner, the memory access circuit of the present embodiment performs the operation of specifying the memory address by giving RAS and CAS in the same manner as in the conventional case when the clock signal is "0" to "3". In writing, the first page mode is set, and RAS is not given and only CAS is given to access.

Therefore, comparing the clocks required for writing the two data in FIGS. 2 and 5, the operation of the clock signals "4" to "6" is unnecessary in the first page mode when no carry occurs. The access time is shortened accordingly.

Therefore, according to the present embodiment, in the access operation to the DRAM, the column address (lower address) of the access address is accessed by switching the operation mode according to the determination result as to whether or not a carry occurs. If the error does not occur, it is possible to access the DRAM in an operation mode that allows faster access. This enables high speed access to the DRAM.

Further, according to the timing chart as shown in FIG. 3, even in the read modify write operation in the first page mode, high speed memory access can be realized as compared with the conventional example shown in FIG. In this case as well, since RAS is not applied in the read-modify-write of the second data, the memory access becomes faster accordingly.

In this embodiment, the case of performing the write operation to the memory in the first page mode has been described, but the present invention is not limited to this. For example, it is possible to use static columns, nibbles, etc., which are other high-speed access modes.

[0020]

As described above, according to the present invention, D
At the time of accessing the RAM, it is determined whether or not a carry from the column address occurs, and DR is determined according to the determination result.
The access to the AM is switched to an operation mode such as a fast page mode, a nibble mode, or a static column mode, which enables high-speed access. The effect is that the memory access can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory access circuit that is a typical embodiment of the present invention.

FIG. 2 is a timing chart when writing to a memory.

FIG. 3 is a timing chart at the time of a read modify write to a memory.

FIG. 4 is a block diagram showing a configuration of a conventional memory access circuit.

FIG. 5 is a timing chart at the time of writing to a memory according to a conventional example.

FIG. 6 is a timing chart at the time of read-modify-write to the memory according to the conventional example.

[Explanation of symbols]

 102 Sequencer (SEQ) 103 Latch circuit 104 Adder circuit 125 Discrimination circuit

Claims (2)

[Claims] 1. A memory access control device for controlling an access operation to a DRAM, comprising latch means for latching a memory address input from an external device, and a memory address latched by the latch means from a column address. The memory access control device is characterized in that it has a discriminating means for discriminating whether or not the carry occurs, and switches the operation mode capable of high-speed access according to the discrimination result of the discriminating means. 2. The high-speed accessible operation mode includes:
The memory access control device according to claim 1, comprising a first page mode, a nibble mode, and a static column mode.