JPH07219852A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To keep the program secrecy of a customer by carrying out the coding processing based on the output or/and input data addresses that momentarily change. CONSTITUTION:The address signal. groups A1-AM which are given to a semiconductor memory device from a microcomputer, etc., are decoded by an address decoder B, and a certain address is designated at a memory cell part A. The part A outputs the data signal groups d1-dN which are stored in the addresses based on the designated address. Then these groups d1-dN are inputted to the exclusive OR gates G1-GN serving as the coding circuits. Meanwhile N pieces of signals, i.e., some of those groups A1-AM supplied from the outside of the semiconductor memory device are inputted to one of both input terminals of each of groups G1-GM. In such a constitution, the value D1-DN obtained by securing the exclusive OR for each bit are outputted to the outside of the semiconductor memory device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and a microcomputer using the semiconductor memory, and a semiconductor memory device and a microcomputer having a function of maintaining confidentiality of the contents of the memory requiring security protection for a third party. Involved in the system.

[0002]

2. Description of the Related Art FIG. 5 shows an encryption circuit of a conventional security memory device shown in Japanese Patent Laid-Open No. 55-67782.

[0003] an input terminal A ₁ to A _M which incorporate address signal group from the semiconductor memory device outside the memory device M ₁ ~M _N writable by the user, and the memory cell portion A for storing a user program, the address signal a decoder B for decoding a group a ₁ to a _M, and written by the signal group output from the memory cell portion a d ₁ to d _N and the user according to the address the address specified memory device M ₁ ~M _N exclusive specifically an encryption circuit G ₁ ~G _N ORing, and at terminals D ₁ to D _N for outputting a signal to the semiconductor memory device outside.

[0004] The output d ₁ to d _N of the ROM array portion A written the program outputs an encryption circuit writable memory device M ₁ ~M _N by user G ₁ ~G _N
Are exclusive-OR'd with and coded into terminals D ₁ -D _N
Is output to. By integrating the above encryption circuit on the same semiconductor as the memory, a third party can be provided with a confidentiality retaining function.

Below, M = 4, N = 4 in the circuit of FIG.
An example in the case of (M ₄ , M ₃ , M ₂ , M ₁ ) = (1000) is shown. Output d ₁ to d ₄ of the ROM array portion A is outputted after being encrypted D ₁ to D ₄ by M ₁ ~M ₄ and encryption circuit G ₁ ~G _4.

(Example) When N = 4, (M ₄ , M ₃ , M ₂ , M ₁ ) = (1000) M = 4, (A ₄ , A ₃ , A ₂ , A ₁ ) = A _H Then, A _H (d ₄ , d ₃ , d ₂ , d ₁ ) → (D ₄ , D ₃ , D ₂ , D ₁ ) 0 _H (0000) → (1000) 1 _H (1100) → (0100) 2 _H (0110) → (1110) 3 _H (0101) → (1101) 4 _H (1111) → (0111) 5 _H (1001) → (0001) ······· Output of the semiconductor memory device shown in FIG. On the side of the microcomputer receiving D _{1 to DN} , the memory devices M _{1 to MN are connected.}
And decoding circuit of the encryption circuit and the same configuration is provided comprising an exclusive OR circuit G ₁ ~G _N.

[0007]

Since the signal output from the ROM is the program itself developed by each customer (user), a third party can easily understand the user program by analyzing this signal. It is possible. In order to prevent this action, a method has been taken in which a signal output from a ROM is encrypted by taking an exclusive OR with certain data so that it cannot be easily analyzed. However, in this method, since the encryption is unique and simple, there is a high risk that the encryption process is relatively easily guessed by analyzing the output signal.

According to the present invention, a small-scale circuit is added to the semiconductor memory to realize more complicated encryption, and the encrypted signal output from the memory is appropriately decrypted inside the microcomputer. , Is intended to maintain the confidentiality of customer programs.

[0009]

The semiconductor memory device of the present invention is provided with an encryption means (for example, an exclusive OR circuit) for encrypting the other part of the output data based on a part of the output data. It is characterized by that. Further, it is characterized in that an encryption means for encrypting the other part of the output data is provided based on the result of logically operating a part of the output data. Further, it is characterized in that an encryption control means for controlling execution / non-execution of encryption is added for each bit of the output data based on the stored data of a specific address (for example, an initial address).

Further, the semiconductor memory device of the present invention is characterized by being provided with an encryption means (for example, an exclusive OR circuit) for encrypting output data based on a part or all of an input address. To do. Further, it is characterized in that an encryption means for encrypting output data is provided based on a result of logically operating a part or all of the input address. Further, it is characterized in that an encryption control means for controlling execution / non-execution of encryption is added for each bit of the output data based on the storage data of the specific address.

Further, the semiconductor memory device of the present invention is provided with an encryption means for encrypting the other part of the output data based on part or all of the output data and part or all of the input address. It is what

[0012]

According to the present invention, the encryption process is executed based on the output data or / and the input address, which changes from moment to moment, rather than the constant data as in the past. Also,
The execution / non-execution of the encryption is controlled for each bit of the output data based on the stored data of the specific address.

As described above, more complicated encryption processing is executed.

[0014]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 is an internal configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

Input terminals A _{1 to} A _M for fetching an address signal group from the outside of the semiconductor memory device, a memory cell section A for storing a user program, and address signal groups A _{1 to} A _M.
And a signal group d _{1 to} d _N output from the memory cell unit A according to a designated address.
An inner N of address signal groups A ₁ to A _M (A ₁ in FIG. 1 to
A _N) and the exclusive with the encryption circuit G ₁ ~G _N ORing, terminals D ₁ to D _N for outputting a signal to the semiconductor memory device external
Composed of.

Address signal groups A _{1 to} A _M given to the semiconductor memory device from a microcomputer or the like are decoded by an address decoder B and specify a certain address of the memory cell portion A. The memory cell unit A outputs the data signal groups d _{1 to} d _N stored at the specified address according to the specified address. Output data signal group d ₁ ~
d _N XOR is encrypted circuit gate G ₁ ~G _N
Entered in. The other one of the input terminals of the exclusive OR gate G ₁ ~G _{N, N} of signal which is a part of the earlier semiconductor memory device inputted from the outside address signal group A ₁ to A _M is input There is. As a result, the data signal groups d _{1 to} d _N and the address signal _N are provided outside the semiconductor memory device.
D _{1 to} D _N, which are values obtained by taking the exclusive OR for each corresponding bit of the book signal (A _{1 to} A _{N in} FIG. 1), are output.

In FIG. 1, the N address signal groups A _{1 to} A _M are designated as A _{1 to} A _N , but any one may be selected. Also, regarding the input method to the encryption circuit, similarly, any bit of the address can be input.

Below, M = 8 and N = 4 in the circuit of FIG.
An example in the case of is shown. Data d ₁ to d ₄ stored in the address specified by the address A ₁ to A ₈ are exclusive of four bits A ₁ to A ₄ bit units of the address signal group is taken, D ₁ .About.D ₄ is output to the outside of the semiconductor memory device. (Example) If M = 8 and A _H = (A ₈ A ₇ A ₆ A ₅ A ₄ A ₃ A ₂ A ₁ ) N = 4, then A _H (A ₄ A ₃ A ₂ A ₁ ) (d ₄ d _{3 d 2 d 1) → (} D 4 D 3 D 2 D 1) 00H (0000) (1101) → (1101) 01H (0001) (1011) → (1010) 02H (0010) (0101) → (0111) 03H (0011) (1111) → (1100) 04H (0100) (0011) → (0111) 05H (0101) (1100) → (1001) In this semiconductor memory device, all the memory cell parts A in FIG. Even if the data is stored, it will be output as a different value when output.

A _H (A ₄ A ₃ A ₂ A ₁ ) (d ₄ d ₃ d ₂ d ₁ ) → (D ₄ D ₃ D ₂ D ₁ ) 00H (0000) (1101) → (1101) 01H (0001 ) (1101) → (1100) 02H (0010) (1101) → (1111) 03H (0011) (1101) → (1110) 04H (0100) (1101) → (1001) 05H (0101) (1101) → ( 1000) On the side of the microcomputer which receives the outputs D _{1 to DN} of the semiconductor memory device, the exclusive OR gates G ₁ to
Similar to G _N, the decoding circuit comprising an address A ₁ to A _N and D ₁ to D _N from the exclusive OR gate for receiving as its input is provided.

In the above embodiment, a part of the input address is used for encryption. However, for example, when the number of input address bits = the number of output data bits, the entire input address is used for encryption. Used.

Further, in the above embodiment, the input address is used as it is, and the encryption is performed by taking the exclusive OR of the input address and the output data, but the input address is logically operated and the result is obtained. The encryption may be performed by taking the exclusive OR with the output data. Also in this case, a decryption circuit having the same configuration as the encryption circuit including the logical operation circuit is provided on the microcomputer side.

FIG. 2 shows a semiconductor memory device Y according to another embodiment of the present invention and a microcomputer Z connected thereto.
FIG.

The input terminal A ₁ to A _M which incorporate address signal group from the semiconductor memory device outside the memory cell portion A for storing a user program, the address signal group A ₁ to A _M
And a register B for decoding the signal groups d _{1 to} d _N output from the memory cell A when a specific address is designated (a latch signal L is output when the specific address is designated by the decoder B). Value of the register C and N of the address signal groups A _{1 to} A _M (A ₁ to A in FIG. 2).
A _N ) and AND gates E _{1 to} E that take the logical product in bit units
_N and the memory cell section A according to the specified address
Output signal groups d _{1 to} d _N and AND gates E _{1 to} E
_A semiconductor memory device Y composed of encryption circuits G _{1 to} GN that perform exclusive OR in bit units with the output of _N and output terminal groups D _{1 to DN} is used as a memory device. an address signal group μA ₁ ~μA _M output from the conventional microcomputer X which is connected to the address signal group a ₁ to a _M of the device, which is connected to the output terminals D ₁ to D _N of the semiconductor memory device inputs Terminal group μD _{1 to} μD _N and address μA output from conventional microcomputer
_When a specific address of _{1 to} μA _M is designated, a signal L is issued from the decoder B and an address decoder R which issues a signal μL at the same time, and a signal μL is issued, μD _{1 to} μ
A register P that latches D _N and AND gates I _{1 to} I that logically AND the value of the register P and _N of the address signal groups A _{1 to} A _M (A _{1 to} A _{N in} FIG. 2) in bit units. _N and a data signal group μD _{1 to} μ input from the semiconductor memory device
A decryption circuit (decryption circuit) H _{1 to} H _N for exclusive ORing the outputs of D _N and AND gates I _{1 to} I _N in bit units
This system is composed of a microcomputer Z composed of.

When the "certain specific address" from which the signals L and μL are output is other than address 0 (A _{1 to} A _M , μA _{1 to} μA _M are all "0"), the register C, Since the system does not operate normally unless the same value is set in P, the registers C and P must be reset when the system is started.

FIG. 3 shows a schematic flow of the operation of this system.

After the power is turned on, the microcomputer is initialized and the initial address (address 0) is output from the conventional microcomputer.

[0028] Initial address outputted from a conventional microcomputer is passed to the input terminal group A ₁ to A _M of the semiconductor memory device through terminals μA ₁ ~μA _M.
At this time, it is also input to the address decoder R in the microcomputer.

The address decoder R receives the initial address (address 0) and outputs the latch signal μL to the register P.

In the semiconductor memory device, the memory cell section A designates from the decoder B according to the input initial address, and at the same time, the latch signal L is output to the register C.

The initial address 0 from the memory cell section A
The data signal groups d _{1 to} d _N stored in the address are output. At this time, since the specified initial address is address 0, A _{1 to} A _N are all “0”. Therefore, the AND gate E ₁ to E _N outputs all "0", from the encryption circuit in which an exclusive OR gate G ₁ ~G _N is the input signal d ₁ to d _N is output as it is.

At the same time, according to the latch signal L, the data signal groups d _{1 to} d _N are latched in the register C.

The data signals D _{1 to DN} (= d _{1 to} d _N ) output from the semiconductor memory device are input from the input terminals μD _{1 to} μD _N of the microcomputer.

Input data signal group μD _{1 to} μD _N
Are latched in the register P according to the latch signal μ L. As a result, the same value as the register C in the semiconductor memory device is latched in the register P.

Since the initial address is the address 0, the outputs of the AND gates I _{1 to} I _N are all “0” regardless of the value of the register P. As a result, the input data signal groups μD _{1 to} μD _N are directly input to the conventional microcomputer through the exclusive OR gate groups H _{1 to} H _N which are the decryption circuits.

By the above, the initial address (address 0)
The conventional microcomputer can obtain the unencrypted data as is.

Next, the next address (different from the initial address) is designated, and in the semiconductor memory device, the outputs d _{1 to} d _N from the designated memory cell section A and the address signal groups A _{1 to} A are designated. Value of logical product of _N and register C (E _{1 to} E
Encryption is performed by taking the exclusive OR with the output of _N ).

The data D _{1 to} D _N output from the semiconductor memory device are fetched by the microcomputer as μD _{1 to} μD _N , and the logic of the address signal groups A _{1 to} A _N and the register P is the same as in the semiconductor memory device. Product value (I ₁ ~ I _N
Output) is decrypted by taking the exclusive OR with the output, and passed to the conventional microcomputer for processing.

The encryption principle of the present invention is based on the following logical mathematics.

Basically, the encryption is performed by taking the exclusive OR with the address signal. However, if the data (latch in registers C and P) stored at the initial address here is "1". If it is "0", encryption is not performed. From the following logical mathematics, the value encrypted by exclusive OR is decrypted by taking exclusive OR again with the signal used for encryption.

A: signal before encryption, c: register C,
Specific bit of P, b: specific bit of address signal Ax (encryption) a + (b · c) (+: exclusive OR) (decryption) {a + (b · c)} + (b · c ) = A + (b · c) +
(B.c) = a + {(b.c) + (b.c)} = a + 0 = a Note: x + y = bar-x.y + x.bar-y FIG. 4 shows still another embodiment of the present invention. 3 is an internal configuration diagram of a semiconductor memory device Y and a microcomputer Z connected thereto. FIG.

Input terminals A _{1 to} A _M for fetching an address signal group from the outside of the semiconductor memory device, a memory cell section A for storing a user program, and address signal groups A _{1 to} A _M.
And a signal group d _{1 to} d _N output from the memory cell unit A according to a designated address.
Of several (in FIG. 4, d ₁ , d ₂ , d ₃ ) logical operation circuit E for performing a logical operation, the operation result of the logical operation circuit E,
And the remaining data signal group (in FIG. ₄ d 4 ~d _N) and an exclusive OR encryption circuit G ₄ ~G _N did not the logical operation by the logic operation circuit E, the signal to the semiconductor memory device external using the semiconductor memory device Y configured as a memory device at terminals D ₁ to D _N for outputting, output from a conventional microcomputer X which is connected to the address signal group a ₁ to a _M of the semiconductor memory device Address signal group μA ₁ ~ μ
Of A _M and, a wired input terminals μD ₁ ~μD _N to the output terminals D ₁ to D _N of the semiconductor memory device, the data signal group μD ₁ ~μD _N inputted from the semiconductor memory device Y,
A logical operation circuit F, which has the same signal as the signal input to the logical operation circuit E inside the semiconductor memory device as an input signal, and is composed of the same logical circuit as the logical operation circuit E, and the operation result of the logical operation circuit F , The remaining data signal group that has not been logically operated by the logical operation circuit F (μD _{4 to} μD _{N in} FIG. 4)
This system is composed of a microcomputer Z which is composed of cryptanalysis circuits H _{4 to} H _N that take exclusive OR.

The outline of the operation is as follows: An address signal generated from a conventional microcomputer is output to the outside of the microcomputer Z through output terminals μA _{1 to} μA _M.

The address signals μA _{1 to} μA _M output from the microcomputer Z are input to the decoder B through the input terminals A _{1 to} A _M and decoded.

In accordance with the address designated by the decoder B, the data signal groups d _{1 to} d _N are output from the memory cell unit A, of which d ₁ , d ₂ , d ₃ are D ₁ , D ₂ , D _{3 as they are.}
The data is output from the terminal to the outside of the semiconductor memory device Y, and at the same time, is input to the logical operation circuit E installed inside the semiconductor memory device.

The arithmetic operation result from the logical operation circuit E, exclusive OR at the exclusive OR gate G ₄ ~G _N and each bit of the d ₄ to d _N output from the memory cell portion A bets To be

The output of the exclusive OR gate G ₄ ~G _N is outputted through the output terminal D ₄ to D _N to the semiconductor memory device Y outside.

D output from the semiconductor memory device Y
_{1 to DN} are input to the microcomputer Z through the input terminals μD _{1 to} μD _N. ΜD ₁ , μD ₂ , μD ₃
Is input to the conventional microcomputer as it is, and at the same time, is input to the same logical operation circuit F as the logical operation circuit E provided inside the microcomputer Z.

The output of the logical operation circuit F is μD _{4 to} μ
Each bit of D _N and exclusive OR gates H _{4 to} H _N are exclusive ORed, and the result is input to a conventional microcomputer.

A conventional microcomputer fetches input N-bit data (this is nothing but a program created by each customer) and operates.

Below, M = 8 and N = in the circuit of FIG.
8. The logical operation circuits E and F show an example of a logical sum. Of the data d _{1 to} d ₈ output from the memory cell A, d ₁ ,
d ₂ and d ₃ are directly output as D ₁ , D ₂ and D ₃ , and d
₄ to d ₈ are output as D _{4 to} D _{8 obtained} by taking the exclusive OR for each bit and the logical operation result (logical sum) of d ₁ , d ₂ , and d ₃ .

(Example) If M = 8, A _H = (A ₈ A ₇ A ₆ A ₅ A ₄ A ₃ A ₂ A ₁ ) N = 8 A ₃ + A ₂ + A ₁ = B, then A _H (d ₈ d ₇ d ₆ d ₅ d ₄ d ₃ d ₂ d ₁ ) B → (D ₈ D ₇ D ₆ D ₅ D ₄ D ₃ D ₂ D ₁ ) 00H (10101010) 1 → (01010010) 01H (01010101) 1 → ( 10101101) 02H (11111111) 1 → (00000011) 03H (00000000) 0 → (00000000) 04H (11000111) 1 → (00111111) 05H (1010000) 0 → (1010000) In the above embodiment, a part of the output data is Encryption is performed by taking the exclusive OR of the result of logical operation and other output data, but as a configuration that uses the output data as it is Good. For example, when the output data is 8 bits (d ₁ , d ₂ , ..., D ₈ ), the exclusive OR of d ₁ and d ₄ and d ₅ is taken, and d ₂ and d ₆ and d ₇ are taken. an exclusive OR operation, and further, by taking the exclusive OR of d ₃ and d _8, for encryption. A decoding circuit including the same exclusive OR circuit is provided on the microcomputer side.

Further, also in the embodiment of FIG. 4, a bit unit / encryption execution / non-execution control means based on the storage data of a specific address may be added, similar to the embodiment of FIG.

In each of the above embodiments, the encryption processing is performed based on only one of the input address and the output data. However, the embodiment of FIG. 1 and the embodiment of FIG. 4 are combined. , For example, a logical operation is performed on the result of logically operating a part of the input address and a result of logically operating a part of the output data, and the result is encrypted by exclusive ORing with the rest of the output data. It may be configured to perform. In this case as well, a decoding circuit including a logical operation circuit and an exclusive OR gate having the same configuration is provided on the microcomputer side.

[0055]

According to the present invention, the signal output from the semiconductor memory device is an encrypted program created by the user. Moreover, the encryption method is not a simple and unique method of performing a logical operation with fixed data, but a method of deciding whether or not to perform encryption based on several bits of stored data. As a result, it becomes possible for a third party to obtain a semiconductor memory device having a high confidentiality protection function whose encryption method cannot be easily known.

The signal output from the semiconductor memory device according to the present invention is an encrypted program created by the user. Moreover, the encryption method is not a simple and unique method of performing a logical operation with fixed data, but a method in which an encrypted signal (a partner of the logical operation) is different for each designated address. As a result, it becomes possible for a third party to obtain a semiconductor memory device having a high confidentiality protection function in which the encryption method cannot be easily known.

Furthermore, a higher level of confidentiality is provided by the method in which the bit to be encrypted and the bit not to be encrypted are determined by the data such as the randomly written initial address.

Further, in the present encryption method, unlike the prior art, it is not necessary to have a memory other than a program to be stored, which is written by the user when used, so that the circuit can be simplified and the encrypted signal can be used. There is no need to write.

[Brief description of drawings]

FIG. 1 is an internal configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a semiconductor memory device and a microcomputer connected thereto according to another embodiment of the present invention.

FIG. 3 is a schematic flow chart of the operation of the embodiment in FIG.

FIG. 4 is an internal configuration diagram of a semiconductor memory device and a microcomputer connected thereto according to still another embodiment of the present invention.

FIG. 5 is an internal configuration diagram of a conventional semiconductor memory device.

[Explanation of symbols]

G ₁ ~G _N XOR gates C register E ₁ to E _N AND gates E and logic circuit

Claims (7)

[Claims] 1. A semiconductor memory device comprising: an encryption means for encrypting the other part of the output data based on a part of the output data. 2. The semiconductor memory device according to claim 1, further comprising encryption means for encrypting the other part of the output data based on a result of logically operating a part of the output data. . 3. The encryption control means for controlling execution / non-execution of encryption for each bit of output data based on stored data of a specific address. 2. The semiconductor memory device according to item 2. 4. A semiconductor memory device comprising an encryption means for encrypting output data based on part or all of an input address. 5. The semiconductor memory device according to claim 4, further comprising encryption means for encrypting output data based on a result of logically operating a part or all of an input address. 6. The encryption control means for controlling execution / non-execution of encryption for each bit of output data on the basis of stored data of a specific address. 5. The semiconductor memory device according to item 5. 7. A semiconductor memory device comprising an encryption means for encrypting the other part of the output data based on part of the output data and part or all of the input address.