JPH07212770A - Digital signal processing unit for image pickup device - Google Patents

Abstract

PURPOSE:To improve the accuracy of an A/D converter and to extend a dynamic range by using delay circuits so as to increase data for lines thereby providing similar effect to the increase in number of bits of the A/D converter. CONSTITUTION:Data converted into digital data by an n-bit A/D converter 3 are given to four delay circuits 4, from which picture element data for four lines are generated. Data obtained by multiplying a coefficient k1 with the data not delayed at a multiplier 7 and data obtained by multiplying a coefficient k2 with the data delayed by 4H at a multiplier 8 are added by an adder 5 to obtain data in (n+1) bits. The (n+1)-bit data and n-bit data delayed by 1H are given to a signal circuit 6, in which they are processed. In this case, since the adder 5 acts as a low pass filter the coefficients k1, k2 are selected to be 0 to 1/2 in order to avoid the deterioration in the vertical resolution. Thus, the accuracy in n-bits or over is obtained for the A/D converter 3, a rated input level to the A/D converter is reduced to be a half of a maximum input range or below, then the dynamic range is extended and the arithmetic operation accuracy at a low frequency requiring gradation is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device for an image pickup device, which digitally processes pixel signals of a solid-state image pickup device which outputs mixed pixel signals used in a digital image pickup device.

[0002]

2. Description of the Related Art Conventionally, as shown in the conventional example of FIG. 2, a signal from an image pickup device having a color filter in each pixel is subjected to pre-processing circuit clamp, sample hold and amplification, and then subjected to analog / digital conversion by an AD converter. To do. The digital data was input to the digital signal processing device as it was with the same number of bits as the AD converter.

For example, description will be made with reference to FIG. When the pixel array of the solid-state image sensor is arranged as shown in FIG. 4, the signal of the line without delay is a ₀₀ (n), a
₀₁ (n), 1 line delay signal to b ₀₀ (n), b
₀₁ (n), 2 line delay signal is a ₁₀ (n), a
₁₁ (n), n is the number of bits of the AD converter. a
₀₀ (n) and a ₁₀ (n) signals, a ₀₁ (n) and a ₁₁ (n)
Are signals having color filters of the same color. Assuming that the conventional 3-line processing is performed according to FIG. 2, RGB and Y are calculated according to the following equation. However, for Y, pass a low-pass filter,
After that, it is assumed that aperture compensation is applied in the vertical direction.

R = d ₁₁ (a ₀₀ (n) + a ₁₀ (n)) + d ₁₂ (a ₀₁ (n) + a ₁₁ (n)) + 2d ₁₃ b ₀₀ (n) + 2d ₁₄ b ₀₁ ( n)… Number 1 G = d ₂₁ (a ₀₀ (n) + a ₁₀ (n)) + d ₂₂ (a ₀₁ (n) + a ₁₁ (n)) + 2d ₂₃ b ₀₀ (n) + 2d ₂₄ b ₀₁ (n)… Number 2 B = d ₃₁ (a ₀₀ (n) + a ₁₀ (n)) + d ₃₂ (a ₀₁ (n) + a ₁₁ (n)) + 2d ₃₃ b ₀₀ (n) + 2d ₃₄ b ₀₁ (n)… Number 3 Y = b ₀₀ (n) + b ₀₁ (n) + h (-(a ₀₀ (n) + a ₀₁ (n)) + (2b ₀₀ (n) + 2b ₀₁ ( n))-(a ₁₀ (n) + a ₁₁ (n))) (Equation 4) As described above, there is a term that must be doubled in the three-line processing. The resolution has not increased.

[0005]

According to the above conventional example,
In this digital signal processing device, the data at the time of input has the best accuracy and is deteriorated by a digital filter, gamma processing, etc. during the signal processing. For example, when a 3-tap FIR low-pass filter is present during the luminance signal processing, the characteristic is as shown in the following equation.

[0006]

[Equation 5]

According to this, it can be seen that the current signal is multiplied by ¼ and ½ and added respectively. Such processing frequently appears during digital signal processing. The deterioration of the number of data bits due to division of digital data is shown below.
There is data loss due to division.

[0008] Further, in the addition, the data is not deteriorated by adding the data. The state of data by adding digital data is shown below.

[0009] In this way, there is an advantage that the number of bits of data increases by adding.

In the subtraction, the number of bits of data is reduced by subtracting the data. The figure below shows how the number of data bits is reduced by subtracting digital data.

[0011] As described above, the subtraction causes bit deterioration in the data.

In the digital gamma processing, there is a portion around the center of the signal level where the signal is partially amplified, and the resolution of the digital data also deteriorates there. The deterioration of data resolution due to multiplication of digital data is shown below. However, as long as the number of bits is secured, the data will not be lost.

[0013] Thus, during digital processing, the number of data bits deteriorates during subtraction and division. In addition, the number of data bits is increased in addition, and the number of data bits is increased in multiplication, but the resolution of data deteriorates.

In a typical digital circuit design, data rounding error is minimized. For example, in the case of the 3-line processing shown in the conventional embodiment, in order to minimize the data rounding error, the non-delay line and the 2-line delay line are processed by n bits, and the 1-line delay line is processed. The processing corresponding to n + 1 bits is performed because of data compatibility with other lines. In this case, the 1-line delay processing is equivalent to doubling and using n-bit data. This means that the data resolution deteriorates when n + 1-bit digital signal processing is performed in consideration of rounding of digital data as described above.

As described above, there is a great possibility that data will be deteriorated by each arithmetic processing during digital signal processing. Therefore, increasing the number of bits of the AD converter to minimize this deterioration can be mentioned as a countermeasure, but at present, it is difficult to obtain an inexpensive and low power consumption AD converter for a digital camera. It is said that 10 bits is the limit. Therefore, it is necessary to increase the number of bits in digital signal processing in order to improve the calculation accuracy while keeping the number of bits of the AD converter as it is. In addition, it is necessary to increase the dynamic range for the white level when using the AD converter by increasing the number of bits in digital signal processing.
The importance of expanding the dynamic range for this white level was published in Broadcasting Technology Magazine, Showa 57, 1 ".
"High-latitude camera that eliminates the white-collapse phenomenon".

The present invention provides the same effect as when the number of bits of the AD converter is increased by 1 by increasing the number of bits of the conventional 3 line processing by 2 lines, thereby improving the accuracy of the AD converter or the AD converter. The purpose is to expand the dynamic range of.

Further, the prior patent application No. Hei 4-137073
As shown in the automatic gain control circuit, the degree of amplification on the analog side is suppressed by performing digital amplification after AD conversion,
There is a method of reducing power consumption. According to this method, when the number of bits of the AD converter is 9 bits, the analog AGC
Digital A for the first time with 3 to 4 times amplification
Use GC. Therefore, unless analog amplification is used to some extent to raise the signal level, quantization noise becomes large when digital amplification is performed. In order to reduce power consumption, it is necessary to reduce the amplification degree on the analog side. Therefore, it is necessary to increase the number of bits of the AD converter in order to suppress the quantization noise and increase the ratio of digital amplification.

[0018]

[Means for Solving the Problems] The following processing is performed in order to improve the bit precision while the number of bits of the AD converter is suppressed. A signal from a solid-state image sensor that outputs a pixel mixture signal is stored for four lines, and data without delay among them is multiplied by a coefficient k ₁ and 4-line delay data is multiplied by a coefficient k ₂ , and those data and 2-line delay are stored. Data is added, and 3 lines are processed with 3 lines of the signal and the other 2 lines.

The following processing is performed in order to improve the bit precision while the number of bits of the AD converter is suppressed. The signals from the solid-state image sensor which outputs the pixel mixed signal are stored for four lines, and the line output without delay among them is connected to the delay for two pixels and is multiplied by the coefficient k ₃ . A delay of 2 pixels is connected to the 4-line delay output and is multiplied by a coefficient k ₄ . The delay of 4 pixels is connected to the 2-line delay output, and the data without pixel delay is multiplied by the coefficient k ₅ . The 4-pixel delay data is multiplied by the coefficient k ₆ .
Data obtained by adding the 2-pixel delay data of the 2-line delay output data and the data obtained by multiplying the coefficient k ₃ , coefficient k ₄ , coefficient k ₅ , and coefficient k _6, and 2-pixel delay data of the 1-line delay output data, 3-line processing is performed with 2-pixel delay data of 3-line delay output data.

The following processing is performed in order to improve the bit precision while the number of bits of the AD converter is suppressed. A signal from a solid-state image sensor that outputs a pixel mixed signal is stored for two lines, one line delay data of which is connected to a four-pixel delay, and a coefficient k ₇ is multiplied without the pixel delay, and a coefficient is added to the four-pixel delay. Multiplying by k ₈ , the 2-pixel delay data and the coefficients k ₇ , k
Add the data multiplied by ₈ . Three-line processing is performed using this addition data, the data delayed by two pixels from the data without line delay, and the data delayed by two pixels from the two-line delay data.

[0021]

[Function] 1 with the same color filter from the solid-state image sensor
When the AD converter has n bits by adding the pixel signals for every line, the accuracy of n + 1 bits can be obtained. Thereby, the input level of the AD converter can be input at a level lower than the conventional level. A
Although noise may increase when the D converter input level is made lower than in the conventional case, the noise level can be suppressed because it can have an effect similar to that of a low-pass filter by addition between lines. This is shown below.

For example, description will be made with reference to FIG. When the pixel array of the solid-state imaging device is arranged as shown in FIG. 3, the signal of the line without delay is a ₀₀ (n), a
₀₁ (n), 1 line delay signal to b ₀₀ (n), b
₀₁ (n), 2 line delay signal is a ₁₀ (n), a
₁₁ (n), 3 line delay signal to b ₁₀ (n), b
₁₁ (n), 4 line delay signal is a ₂₀ (n), a
₂₁ (n), where n is the number of bits of the AD converter. a
₀₀ (n), a ₁₀ (n) and a ₂₀ (n) signals, a
₀₁ (n), a ₁₁ (n) and a ₂₁ (n) signals, b ₀₀ (n)
The signals b ₁₀ (n) and b ₀₁ (n) and b ₁₁ (n) are signals having color filters of the same color. If 5-line processing is performed, RGB and Y are calculated according to the following equation. However, Y is assumed to have passed through a low pass filter and have an aperture.

R = m ₁₁ (k ₁ a ₀₀ (n) + a ₁₀ (n) + k ₂ a ₂₀ (n)) + m ₁₂ (k ₁ a ₀₁ (n) + a ₁₁ (n) + k ₂ a ₂₁ (n)) + m ₁₃ (b ₀₀ (n) + b ₁₀ (n)) + m ₁₄ (b ₀₁ (n) + b ₁₁ (n))… Number 6 G = m ₂₁ (k ₁ a ₀₀ (n) + a ₁₀ (n) + k ₂ a ₂₀ (n)) + m ₂₂ (k ₁ a ₀₁ (n) + a ₁₁ (n) + k ₂ a ₂₁ (n)) + m ₂₃ (b ₀₀ (n) + b ₁₀ (n)) + m ₂₄ (b ₀₁ (n) + b ₁₁ (n))… Equation 7 B = m ₃₁ (k ₁ a ₀₀ (n) + a ₁₀ (n) + k ₂ a ₂₀ (n)) + m ₃₂ (k ₁ a ₀₁ (n) + a ₁₁ (n) + k ₂ a ₂₁ (n)) + m ₃₃ (b ₀₀ (n) + b ₁₀ (n)) + m ₃₄ (b ₀₁ (n) + b ₁₁ (n))… Number 8 Y = (k ₁ a ₀₀ (n) + a ₁₀ (n) + k ₂ a ₂₀ (n)) + (k ₁ a ₀₁ (n ) + a ₁₁ (n) + k ₂ a ₂₁ (n)) + h (-(b ₀₀ (n) + b ₀₁ (n)) + (k ₁ a ₀₀ (n) + a ₁₀ (n) + k ₂ a ₂₀ (n)) + (k ₁ a ₀₁ (n) + a ₁₁ (n) + k ₂ a ₂₁ (n))-(b ₁₀ (n) + b ₁₁ (n)))… Number 9 addition Looking at the increase in the number of bits due to, a (n + 1) <= k ₁ a ₀₀ (n) + a ₁₀ (n ) + k ₂ a ₂₀ (n) ... There is an increase in the number of bits in this way (however,
k ₁ and k ₂ are about 1/2). However, a ₁₀ (n) is a
_Since there is a delay of two lines with respect to ₀₀ (n), the z-transform is H ₁ (z) = k ₁ + 1 / z + k ₂ / z ² ... Equation 11 and k ₁ and k ₂ are each 1/2 In terms of frequency characteristics, H ₁ (f) = 2cos ² (πfT) ... However, T is a sampling period. This is 1
Since this is a low-pass filter that becomes 0 at a frequency of / 2T, it is shown that the addition increases the number of data bits by 1 bit, but there is also deterioration of high frequencies. Therefore, the addition reduces the vertical resolution. Further, as an advantage, it is possible to reduce noise due to uneven dark current of each pixel.

In order to correct the deterioration of this high frequency component,
The values of k ₁ and k ₂ are selected within the range of 0 or more and 1/2 or less, and the optimum values are set. Setting k ₁ and k ₂ to 0 is equivalent to 3-line processing.

As described above, the 5-line processing does not have a term for doubling the 5-line processing, and the processing of the n-bit AD converter can be increased to n + 1 bits. Therefore, the input level of the AD converter is conventionally set. Even if it is set lower than the above, the accuracy can be ensured and the dynamic range of the AD converter can be expanded.

The values of k _{1 and 2} affect the frequency characteristic in the vertical direction, and if k _{1 and 2} = 1/2 are reduced, the bit expansion effect for high frequencies gradually decreases. Therefore, it can be seen that the bit expansion effect is obtained at relatively low frequencies. From the above example, assuming that the number of significant digits is 12 bits, the resolution of data can be expanded in the low frequency region by using the 5-line processing of the present invention. For high frequencies, this is close to the 3-line processing. This is a rational means for digital signal processing because it is close to performing conventional processing at a high frequency that does not require gradation while increasing bit precision at a low frequency that requires gradation.

Even if addition (low-pass filtering) is not performed in the vertical direction, addition of pixel signals having color filters of the same color in the horizontal direction (low-pass filtering) can also have the same effect of improving bit precision. it can. The same can be done by the three-line processing as long as it is limited to the horizontal direction. Further, considering the horizontal direction in the 5-line processing, the coefficient to be multiplied by the multiplier existing in the present invention can be further reduced, and the deterioration of high frequency can be further suppressed.

[0028]

EXAMPLE A first example shown in FIG. 1 will be described. 1
Is a solid-state image sensor, 2 is a pre-processing circuit, 3 is an AD converter, 4 is
Is a 1-line delay, 5 is an adder, 6 is a digital signal processing, 7 is a multiplier, and 8 is a multiplier. A pixel mixture signal is generated from the solid-state image sensor 1, and the preprocessing circuit 2 performs preprocessing. Analog-to-digital conversion is performed by the n-bit AD converter 3, and pixel data for four lines is recorded with four one-line delays. In the adder 5, the data without delay and the first
The coefficient k ₁ is multiplied by the multiplier 7 and the output of the multiplier 7
The data of 4-line delay is multiplied by the coefficient k _{2 in the second} multiplier 8 and the output of the multiplier 8 is added. As a result, n-bit data becomes n + 1-bit data. In the digital signal processing 6, n-bit data of delay 1 line, n-bit data of delay 3 line, and n + generated in the adder 5
Perform processing using 1-bit data. The adder 5 has a function as a low pass filter. Therefore, there is a possibility that the high-frequency component deteriorates and the resolution in the vertical direction deteriorates, and the coefficient k ₁ and coefficient k ₂ values must be set to 0 or more and 1/2 or less.

With this configuration, it is possible to obtain accuracy higher than that of the 9-bit AD converter by using, for example, a 9-bit AD converter. Therefore, the rated input level of the 9-bit AD converter is set to half the maximum input range, but it can be set to a level lower than that. When the coefficients k ₁ and k ₂ are set to 1/4, the accuracy is equivalent to an increase of 0.58 bits as compared with the conventional 3-line processing. Therefore, the rated input level of the AD converter is about 0 of the maximum input range. It can be lowered to 66 times. However, in order to standardize the data, the middle line of the three lines must be multiplied by 1.33. At this rated level, the dynamic range of the 9-bit AD converter is doubled to 3.00 times the conventional range. Since the saturation value of the current solid-state image sensor is about three times the rated value, it is sufficient. The conventional 3-line processing requires a knee expansion circuit because the compression ratio above the rated level is ½ in order to triple the dynamic range. However, according to the present invention, no knee compression extension is required. Therefore, it has the advantage that the circuit configuration is simple. Further, since a light low pass is applied in the vertical direction, it is possible to reduce noise due to variations in dark current of the solid-state image sensor. This makes it possible to improve the bit accuracy for low frequencies that require relatively gradation, but for high frequencies that do not require gradation, it is almost the same as the conventional 3-line processing. Is. In addition, since this process works as a low-pass filter, it also has a high-frequency deterioration.
The adjustment of the high frequency signal deterioration is performed by adjusting the coefficients k ₁ and k ₂ .

FIG. 4 shows a second embodiment of the present invention. 1 is a solid-state imaging device, 2 is a pre-processing circuit, 3 is an n-bit AD converter, 4 is 1 line delay, 9 is 1 pixel delay, 10 is a multiplier, 11 is a multiplier, 12 is a multiplier, and 13 is a multiplier. Bowl, 14
Is an adder, and 6 is a digital signal processing device. The difference from the first embodiment is that the pixel data addition direction is considered not only in the vertical direction but also in the horizontal direction. Therefore, 1
A pixel delay of 9 is provided. With this configuration, the input data of the multiplier 10, the multiplier 11, the multiplier 12, and the multiplier 13 is data having filters of the same color. This is clear when looking at FIG. The portion corresponding to the central position of these data is directly input to the adder 14.
The multiplier 10 multiplies the 2-line-delayed pixel data by a coefficient k _5, and then inputs it to the adder 14. The multiplier 11 multiplies the 2-pixel delay data after 4-line delay by the coefficient k _4, and then inputs the data to the adder 14. The multiplier 12 multiplies the 4-pixel delay data after 2-line delay by a coefficient k ₆ and then inputs the data to the adder 14. The multiplier 13 multiplies the 2-pixel delay data without line delay by a coefficient k _3, and then inputs the data to the adder 14. Output of adder 14 and 1 pixel delay of 1 line delay 2 pixel delay 9
3 and the output data of the 1-pixel delay 9 of the 2-line delay and 2-pixel delay are used for the 3-line processing in the digital signal processing device 6. A feature of this second embodiment is that the effect is similar to that of the first embodiment, but the values of the coefficients k ₃ , k ₄ , k ₅ , k ₆ can be made smaller than k ₁ , k ₂ . Therefore, the deterioration of the high frequency is less than that of the first embodiment.

Further, in the configuration of FIG. 4, each of the line without delay and the line with 4 lines delay is set to 4 pixels delay,
In the line without delay, the outputs of no pixel delay, 2 pixel delay and 4 pixel delay are multiplied by coefficients k ₉ , k ₃ and k ₁₀ , respectively, and in 2 line delay, there is no pixel delay and 4 pixel delay output respectively. Multiplying the coefficients k ₅ and k ₆ and multiplying the outputs of no pixel delay, 2 pixel delay and 4 pixel delay by the coefficients k ₁₁ , k ₄ and k ₁₂ in the 4-line delay and adding them, and 2 In the line delay, those delayed by 2 pixels are added, and the data, 1 line delayed 2 pixel delayed data, and 3 line delayed 2 pixel delayed data are subjected to 3 line processing.

FIG. 5 shows a third embodiment of the present invention. 1 is a solid-state image sensor, 2 is a pre-processing circuit, 3 is an n-bit AD converter, 4 is 1 line delay, 9 is 1 pixel delay, 15 is a multiplier, 16 is a multiplier, 17 is an adder, 6 is a digital It is a signal processing device. The difference from the first embodiment is that the first embodiment performs addition in the vertical direction, whereas the third embodiment performs addition in the horizontal direction.
2 pixel delay is provided without line delay, and 4 is provided for 1 line delay
The pixel delay is arranged, the two-pixel delay is arranged in the two-line delay, and the multiplier 15 calculates a coefficient k _{7 for the} two-line delay data.
The multiplier 16 multiplies the 2-line delay 4-pixel delay data by k _8, and the data is added by the 2-line delay 2-pixel delay data and the adder 17. As is clear from FIG. 3, these additions add data having color filters of the same color. The digital signal processing device 6 performs 3 line processing by 3 lines of 2 pixel delay data without line delay, 2 line delay 2 pixel delay data, and output data of the adder 17. The effect is similar to that of the first embodiment, but since the addition is performed in the horizontal direction, there is no image deterioration in the vertical direction. However, it has horizontal image degradation.

[0033]

By increasing the number of lines by 2 lines as compared with the conventional 3-line processing, or by delaying pixels in the horizontal direction, A
The same effect can be obtained as when the number of bits of the D converter is increased by α bits. Therefore, the input level of the AD converter can be lowered and the dynamic range of the AD converter can be expanded. Alternatively, in the digital signal processing, it is possible to increase the calculation accuracy at a low frequency that requires a relatively high gradation, and to perform the same processing as the conventional 3-line processing at a high frequency that does not require a gradation.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

FIG. 3 is a diagram showing a pixel arrangement.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor, 2 ... Pre-processing circuit, 3 ... AD converter, 4 ... 1 line delay, 5 ... Adder, 6 ... Digital signal processing, 7 ... Multiplier, 8 ... Multiplier, 9 ... 1 pixel delay , 10 ... Multiplier, 11 ... Multiplier, 12 ... Multiplier, 13 ... Multiplier, 14 ... Adder, 15 ... Multiplier, 16 ... Multiplier, 17 ... Adder.

Claims (4)

[Claims] 1. Solid-state photodetection elements are arranged in an array on a single substrate, and each photodetection element has a color filter of magenta, cyan, green, yellow, etc., and is alternately arranged for each line depending on the operating frequency. (Magenta and cyan, green and yellow), (magenta and yellow, green and cyan)
A solid-state image sensor for outputting a mixed pixel signal of two colors from a photo-detecting element having each color filter; and a control signal generated from a mixed signal signal from the solid-state image sensor by a digital signal processing result by a pixel signal process. A pre-processing circuit for clamping, sample-holding, and amplifying with;
An n-bit AD converter that performs analog-to-digital conversion using a signal from the preprocessing circuit as an operating frequency as a clock; and an n-bit output for the four lines of the solid-state image sensor output signal from the AD converter as an operating frequency And a storage means for taking in as a reading frequency;
_{A first} multiplier for multiplying by 1; a second multiplier for multiplying a 4-line delayed signal by a coefficient k ₂ ; a first multiplier generated from a color filter of the same color among 5 lines including the signal from the storage means 1 multiplier output, 2 line delay output, 2nd
And an output of the multiplier to obtain pixel data of n + 1 bit; and an output of the adder and a total of 3 lines of pixel signals from the solid-state image sensor of 2 lines not input to the adder. A digital signal processing device for processing, and a digital signal processing device for an image pickup device. 2. The solid-state image pickup device according to claim 1, the preprocessing circuit according to claim 1, the n-bit AD converter according to claim 1, and a storage capacity for four lines. 2. The storage means according to claim 1, further comprising: a first and second pixel delay for delaying two pixels in the line without delay according to claim 1, 1 according to the storage means according to claim 1. In the line delay, the third and fourth pixel delays delayed by two pixels; and in the two line delays by the storage means according to claim 1, the fifth, sixth, seventh, and eighth pixel delays delayed by four pixels. ;
In the 3-line delay by the storage means according to claim 1, a ninth and a tenth pixel delay delayed by two pixels; and in the 4-line delay by the storage means according to claim 1, 2
Second multiplying coefficient k ₄ to the output of the pixel delay of said 12; eleventh and twelfth pixel delay and delaying pixels; first multiplier and multiplying the coefficient k ₃ to the output of the second pixel delay multipliers and; fourth multiplier and multiplying the coefficient k ₆ to the output of the pixel delay said 8; said third multiplier and multiplying the coefficient k ₅ to the pixel signals for two lines delayed the storage means An output of the first, second, third, fourth multiplier and an output of the sixth pixel delay; an output of the fourth pixel delay and an output of the tenth pixel delay; The digital signal processing device according to claim 1, wherein the digital signal processing device according to claim 1 performs three-line processing by the output of the adder. 3. The solid-state imaging device according to claim 1, the pre-processing circuit according to claim 1, the n-bit AD converter according to claim 1, and the pre-processing circuit according to claim 1. Storage means for delaying the output of the AD converter by two lines; first and second pixel delays for performing pixel delay of the pixel signal in the line without delay; pixel of pixel signal in the one-line delay by the storage means 3rd, 4th, 5th, 6th pixel delays for delaying; 7th, 8th pixel delays for delaying pixel signals of the pixel signal in the 2-line delay by the storage means; a first multiplier that multiplies k ₇ ; a second multiplier that multiplies the output of the sixth pixel delay by a coefficient k ₈ ; an output of the first multiplier and an output of the second multiplier And an adder for adding the output of the fourth pixel delay; and the second pixel delay output, 8. A digital signal processing device for an image pickup device, comprising: the pixel delay output of 8; and the digital signal processing device according to claim 1, which performs 3 line processing by the output of the adder. 4. The solid-state image pickup device according to claim 1, the preprocessing circuit according to claim 1, the n-bit AD converter according to claim 1, and a storage capacity for four lines. The storage means according to claim 1, further comprising: the first, second, third, and fourth delay lines for delaying four pixels in the line without delay according to claim 1.
Pixel delay of 5; 6th pixel delay delayed by 2 pixels in the 1 line delay by the storage means according to claim 1; The 7th, 8th, 9th and 10th pixel delays delayed by pixels; and the 11th and 12th pixel delays delayed by 2 pixels in the 3-line delay by said storage means according to claim 1; In the four-line delay by the storage means described, the thirteenth, fourteenth, fifteenth, and sixteenth pixel delays delayed by four pixels; in the line without delay according to claim 1, the n bits according to claim 1. A first multiplier that multiplies the output of the AD converter of the above by a coefficient k ₉ ; a second multiplier that multiplies the output of the second pixel delay by a coefficient k ₃ ; third multiplier and multiplying the k _10; the storage of claim 1 The multiplied by coefficient k ₅ to the pixel signals for two lines delayed by the stage 4 multipliers and; fifth multiplier for multiplying a coefficient k ₆ to the output of the pixel delay said 10 and; the storage of claim 1 The pixel signal delayed by 4 lines by the means has a coefficient k ₁₁
A sixth multiplier multiplying the; and eighth multiplier for multiplying the coefficient k ₁₂ in the output of the pixel delay of said 16; seventh multiplier and multiplying the coefficient k ₄ to the output of the pixel delay said 14 The first,
The outputs of the multipliers 2, 3, 4, 5, 6, 7, and 8
An adder for adding the output of the pixel delay of the above; the output of the sixth pixel delay, the output of the twelfth pixel delay, and the output of the adder for performing three-line processing. A digital signal processing device for an imaging device, comprising: a digital signal processing device;