JP3562275B2 - Luminance signal processing circuit in imaging device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a luminance signal processing circuit in an imaging device, and more particularly to a luminance signal processing circuit in an imaging device using a solid-state imaging device.
[0002]
[Prior art]
2. Description of the Related Art In an imaging apparatus using a solid-state imaging device, a vertical contour correction circuit is conventionally known as a circuit for processing a luminance signal of a video signal output from the solid-state imaging device. FIG. 6 is a block diagram showing an example of the conventional luminance signal processing circuit. This conventional luminance signal processing circuit is a vertical contour correction circuit, and a luminance signal obtained by subjecting a video signal output from a solid-state imaging device (not shown) to a predetermined signal processing is 1H (H is a horizontal scanning period; the same applies hereinafter). The signals are delayed by a total of 2H by the delay circuits 1 and 2 and supplied to the adder 3, while being directly supplied to the adder 3 and added.
[0003]
The output signal of the adder 3 is halved in amplitude by the attenuator 4 to be a signal as shown by b in FIG. The subtracter 5 subtracts the output signal b of the attenuator 4 from the luminance signal shown by a in FIG. 7 and delayed by 1H by the 1H delay circuit 1, and outputs a contour correction signal shown by c in FIG. The output contour correction signal c of the subtractor 5 is supplied to the adder 6. The luminance signal a delayed by 1H by the 1H delay circuit 1 is added to the contour correction signal c by the adder 6, and a luminance signal whose vertical contour (edge) is emphasized as shown in FIG. Is output. FIG. 2B shows the emphasized frequency band when this vertical contour correction circuit is used in a conventional interline solid-state imaging device.
[0004]
On the other hand, an imaging apparatus using a solid-state imaging device of an all-pixel readout method has been conventionally known (for example, Japanese Patent Application Laid-Open No. Hei 5-304678). FIG. 8 is a schematic configuration diagram of an example of an imaging device using the solid-state imaging device of the all-pixel readout method. In the figure, a plurality of two-dimensionally arranged pixels are respectively formed in an imaging region 11 of a CCD imaging device using a charge transfer device (CCD) as a solid-state imaging device, and light incident through a color filter (not shown) is photoelectrically converted. A plurality of photosensors 12 for converting and accumulating signal charges are provided, and a plurality of vertical transfer CCDs 13 for vertically transferring signal charges from the photosensors 12 in each column among the plurality of photosensors 12 are provided. ing.
[0005]
The vertical transfer CCD 13 vertically transfers the signal charges from each pixel without mixing, and transfers the signal charges for two lines to the two horizontal transfer CCDs 14 and 15 arranged in parallel. The distribution of the signal charges to the two horizontal transfer CCDs 14 and 15 is performed by the distribution transfer gate 16 in line units. The horizontal transfer CCDs 14 and 15 are driven in two phases, horizontally transfer the signal charges from the vertical transfer CCD 13 and supply the signal charges to the output units 17 and 18 to output dot-sequential two-channel pixel signals. As described above, in the image pickup apparatus using the solid-state image pickup device of the all-pixel readout method, all the pixels are independently read out and transferred in one field period.
[0006]
Here, as shown in FIG. 9, four pixels of two pixels in the horizontal direction and two pixels in the vertical direction are used as a basic unit as a color filter on the incident light side of the imaging region 11 of the solid-state imaging device of the all-pixel readout method. In the first row, a color filter section W that transmits white light and a color filter section G that transmits green light are alternately arranged for each pixel pitch. In the second row, a color filter section Cy that transmits cyan light is provided. When a color filter unit Ye that transmits yellow light is used alternately at every pixel pitch, a signal component of white light transmitted through the color filter units W and G is used in the first field (A field). A luminance signal is obtained from a signal component w + g (= r + 2g + b), which is the sum of w and the green light signal component g.
[0007]
In the second field (B field), a luminance signal is obtained by a signal component cy + ye (= r + 2g + b), which is a sum of a signal component cy of cyan light and a signal component ye of yellow light transmitted through the color filter portions Cy and Ye. . Note that r, g, and b are output signals of the CCD image sensor for red light, green light, and blue light.
[0008]
[Problems to be solved by the invention]
However, the relationship between the intensity of the incident light and the signal level obtained by photoelectrically converting the light transmitted through the color filter unit by the CCD image sensor in each of the four color filter units W, G, Cy, and Ye. Are not the same, and the incident light intensity when the output level reaches a saturation level at which the output level is saturated is different.
[0009]
Therefore, if any one of the image sensor output signals for the incident light transmitted through the four color filter units W, G, Cy, and Ye is saturated, the first field and the second field are used. As a result, the balance of the luminance signal is lost, and a level difference between fields occurs as flicker of the luminance signal.
[0010]
However, when the conventional luminance signal processing circuit shown in FIG. 6 is applied for reading out all pixels, the added amount of the contour component can be varied, but the contour component can be varied according to the situation. As a result, the flicker of the luminance signal could not be suppressed.
[0011]
The present invention has been made in view of the above points, and has as its object to provide a luminance signal processing circuit in an imaging device capable of changing a contour component in a vertical direction according to a situation.
[0012]
It is another object of the present invention to provide a luminance signal processing circuit in an imaging device capable of suppressing luminance flicker.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a filter circuit that receives a luminance signal obtained by performing predetermined signal processing on a pixel signal output from a solid-state imaging device and provides a predetermined frequency characteristic in a vertical direction. And characteristic varying means for substantially varying the frequency characteristic of the filter circuit in accordance with the situation of the luminance signal.
[0014]
According to the present invention, the vertical frequency characteristics of the luminance signal are varied according to the state of the luminance signal. Therefore, it is possible to obtain a luminance signal in which the contour component in the vertical direction is varied according to the state of the luminance signal.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of a luminance signal processing circuit in an imaging device according to the present invention. In this embodiment, a luminance signal processing circuit applied to a well-known all-pixel readout imaging apparatus performs predetermined signal processing on a pixel signal output from an all-pixel readout solid-state imaging device (not shown). The obtained luminance signal is supplied to a vertical high-pass filter (V-HPF) 21 and a vertical band-pass filter (V-BPF) 22.
[0016]
Here, as color filters arranged on the incident light side of the imaging region of the solid-state imaging device, for example, the four color filter units W, G, Cy, and Ye shown in FIG. When a color filter having four pixels arranged at a two-pixel pitch as a basic unit is used, the input signals of the V-HPF 21 and the V-BPF 22 are solid-state imaging of incident light transmitted through the color filter units W and G in the first field. The output pixel signals of the elements are dot-sequential signals alternately synthesized in time series for each pixel, and the second field is the output pixel signal of the solid-state imaging element with respect to the incident light transmitted through the color filters Cy and Ye. Are dot-sequential signals alternately synthesized in time series for each pixel. The flicker of the luminance signal is caused by the level difference between the fields. Therefore, when 250 TV lines are used in one field, the vertical signal includes 500 TV vertical components.
[0017]
In FIG. 1, the V-HPF 21 has frequency characteristics as shown in FIG. 2A, for example, and selects a high frequency vertical frequency component of 250 TV or more in one field and supplies it to the multiplier 23. The multiplier 23 multiplies the high frequency vertical frequency component of the luminance signal input from the V-HPF 21 by a preset coefficient K (where 0 ≦ K ≦ 1).
[0018]
On the other hand, the V-BPF 22 has a frequency characteristic as shown in FIG. 2B, for example, and selects a vertical frequency component centered on 250 TV lines and supplies it to the multiplier 24. The multiplier 24 multiplies the vertical frequency component of the luminance signal input from the V-BPF 22 by a preset coefficient 1-K.
[0019]
Here, the multiplication coefficient K is, for example, when a color filter having four pixels as a basic unit shown in FIG. 9 is used, the output of the image sensor with respect to the incident light transmitted through the color filter units W, G, Cy, and Ye, respectively. Whether or not the signal has been saturated is detected by comparing it with a threshold value. If any one of the image sensor output signals is saturated, it is set to “0” by the control signal CTL, and all the image sensors are In a normal case where the output signal is not saturated, it is set to “1”.
[0020]
Therefore, when luminance flicker does not occur, K = 1, so that the output luminance signal of the V-HPF 21 is supplied to the horizontal low-pass filter (H-LPF) 26 through the multiplier 23 and the adder 25, while The output signal of the V-BPF 22 is cut off by the multiplier 24. The overall frequency characteristic of the circuit in this case is indicated by I in FIG.
[0021]
On the other hand, if even one of the image sensor output signals of the four color filter units causes saturation of the image sensor output signal, which causes luminance flicker, K = 0, so that the output brightness of the V-HPF 21 While the signal is blocked by the multiplier 23, the signal from which 500 TV luminance flicker components have been removed by the V-BPF 22 is supplied to a horizontal low-pass filter (H-LPF) 26 through a multiplier 24 and an adder 25. You. The overall frequency characteristic of the circuit in this case is indicated by II in FIG. The output luminance signal of the adder 25 is output after the high frequency components in the horizontal direction are removed by the H-LPF 26.
[0022]
The control of the multiplication coefficient K is not limited to the above embodiment. For example, a pseudo luminance signal (w + g in one field, cy + ye in the other field) is generated and the pseudo luminance signal is generated. When the actual luminance signal exceeds the saturation level, the multiplication coefficient K may be variably controlled according to a gain curve set in advance according to the value of the difference. In this case, as a total frequency characteristic of the circuit, for example, a characteristic indicated by III between I and II in FIG. 2C is obtained.
[0023]
Next, a second embodiment of the present invention will be described. FIG. 3 shows a block diagram of the second embodiment of the present invention. In the figure, among the luminance signals obtained by subjecting pixel signals output from a solid-state image pickup device (not shown) of an all-pixel readout method to predetermined signal processing, a luminance signal A2 of the first field is directly multiplied by a multiplier. The signal is delayed by 1H, supplied to the multiplier 33 as a luminance signal A1, and delayed by 2H and supplied to the multiplier 31 as a luminance signal A0.
[0024]
The luminance signal of the second field is delayed by 1H and supplied to the multiplier 34 as a luminance signal B1, and is delayed by 2H and supplied to the multiplier 32 as a luminance signal B0. The multipliers 31 and 35 are circuits that multiply the input luminance signal by a multiplication coefficient K3, the multipliers 32 and 34 are circuits that multiply the input luminance signal by a multiplication coefficient K2, and the multiplier 33 is a circuit that multiplies the input luminance signal by the input luminance signal. This is a circuit that multiplies the multiplication coefficient K1.
[0025]
The output signals of the multipliers 31 to 35 are supplied to an adder 36, where they are added and synthesized and output. Each multiplication coefficient of the multipliers 31 to 35 is controlled by the control signal CTL. The control signal CTL controls the values of the multiplication coefficients K1, K2, and K3 depending on the situation. For example, by setting K1 = 0.5, K2 = 0, and K3 = −0.25, a luminance signal provided with the V-BPF characteristic is output from the adder 36. Further, for example, by setting K1 = 0.5, K2 = −0.125, and K3 = −0.125, the luminance signal provided with the combined characteristic of the V-BPF characteristic and the V-HPF characteristic is output from the adder 36. Is output.
[0026]
【Example】
Next, examples of the present invention will be described. FIG. 4 is a configuration diagram of a first embodiment of a luminance signal processing circuit in the imaging apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. FIG. 4 shows an example of the first embodiment. The V-HPF 21 includes shift registers 41 to 46, adders 47 to 50, and a subtractor 51. The V-BPF 22 includes shift registers 52 to 54, an adder 55, and a subtractor 56.
[0027]
In FIG. 4, among the luminance signals obtained by subjecting pixel signals output from a solid-state imaging device (not shown) of the all-pixel readout method to predetermined signal processing, the luminance signal A2 of the first field is stored in the shift register 45. It is supplied and shifted rightward by 4 bits to make the value 1/16 times, while being supplied to the shift register 54 and shifted rightward by 2 bits to make the value 1/4 times.
[0028]
The luminance signal A1 obtained by delaying the luminance signal A2 by 1H is supplied to the shift register 43 and shifted rightward by 2 bits, and the value is reduced to 1/4 times. Then, it is shifted rightward by one bit, and the value is reduced by half. Further, the luminance signal A0 obtained by delaying the luminance signal A2 by 2H is supplied to the shift register 41, and is shifted rightward by 4 bits to make the value 1/16 times, while being supplied to the shift register 52. Then, the data is shifted rightward by 2 bits, and the value is reduced to 1/4 times.
[0029]
Further, the luminance signal of the second field is delayed by 1H to be a luminance signal B1, supplied to the shift register 44, and shifted rightward by 2 bits, and the value is made 1/4 times. The luminance signal B0 obtained by delaying the luminance signal B1 by 1H is supplied to the shift register 42 and shifted rightward by 2 bits, and the value is reduced to 1/4 times. The output signal of the shift register 43 is supplied to the shift register 46, further shifted rightward by one bit, and supplied to the adder 47, where it is added to the output signal of the shift register 43 which has not been delayed. As a result, a luminance signal A1 whose value has been multiplied by 3/8 is extracted from the adder 47.
[0030]
The output luminance signal A1 of the adder 47 is added by the adder 49 to the addition signal of the output luminance signal A0 of the shift register 41 output from the adder 48 and the output luminance signal A2 of the shift register 45. The output signal of the adder 49 is supplied to a subtractor 51, where the addition signal of the output luminance signal B0 of the shift register 42 and the output luminance signal B1 of the shift register 44 output from the adder 50 is subtracted, and the luminance is subtracted. A vertical high frequency component of the signal is output.
[0031]
On the other hand, the luminance signal A1 shifted rightward by one bit by the shift register 53 and halved in value is taken out of the adder 55 and shifted rightward by two bits by the shift register 52 to be shifted in value by two bits. A subtractor 56 subtracts an addition signal of the luminance signal A0 that has been multiplied by 1/4 and the luminance signal A2 that has been shifted by 2 bits to the right by the shift register 54 and has a value of 1/4. A vertical middle frequency component of the luminance signal is extracted.
[0032]
Next, a second embodiment of the present invention will be described. FIG. 5 is a configuration diagram of a second embodiment of the luminance signal processing circuit in the imaging apparatus according to the present invention. In the figure, the luminance signal A of the first field delayed by 4H by the 1H delay circuits 61a to 64a cascaded in four stages is added to the luminance signal of the first field which has not been delayed by the adder 65a. The luminance signal of the first field delayed by 3H from the 1H delay circuit 63a and the luminance signal of the first field delayed by 1H from the 1H delay circuit 61a are added by an adder 66a.
[0033]
The output signals of the adders 65a and 66a are multiplied by multiplier coefficients K3 and K2 in multipliers 67a and 68a, respectively, and then added in an adder 69a. The 2H-delayed luminance signal of the first field extracted from the 1H delay circuit 62a is multiplied by a multiplication coefficient K1 by a multiplier 70a, and then supplied to a subtractor 71a, where it is supplied from an adder 69a. The added signal is subtracted and output.
[0034]
The luminance signal B of the second field also performs the same processing as the luminance signal of the first field by a circuit including 1H delay circuits 61b to 64b, adders 65a, 65b, 69b, multipliers 67b, 68b, 70b, and a subtractor 71b. Will be applied.
[0035]
Note that the present invention is not limited to the above-described embodiments and examples. For example, the configuration of a color filter is not limited to FIG. 9. For example, a magenta light A color filter provided with a color filter portion Mg that transmits light may be used, or a color filter including three types of color filter portions G, Cy, and Ye may be used. Further, the imaging device does not have to be of the all-pixel reading method.
[0036]
【The invention's effect】
As described above, according to the present invention, the filter characteristics in the vertical direction are made variable according to the situation, and therefore, the luminance which gives priority to the vertical resolution or S / N according to the situation is given according to the situation. A signal can be obtained. Further, according to the present invention, since the filter characteristics in the vertical direction are switched by the saturation detection signal of the luminance signal, luminance flicker generated when the luminance signal is saturated can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a first embodiment of the present invention.
FIG. 2 is a diagram illustrating frequency characteristics of each unit in FIG. 1;
FIG. 3 is a block diagram of a second embodiment of the present invention.
FIG. 4 is a configuration diagram of a first embodiment of the present invention.
FIG. 5 is a configuration diagram of a system according to a second embodiment of the present invention.
FIG. 6 is a block diagram of an example of the related art.
FIG. 7 is a signal waveform diagram of each unit in FIG. 6;
FIG. 8 is a schematic configuration diagram of an example of an imaging device using a solid-state imaging device of an all-pixel readout method.
FIG. 9 is a diagram illustrating an example of a color filter.
[Explanation of symbols]
21 Vertical high-pass filter (V-HPF)
22 Vertical low-pass filter (V-BPF)
23, 24, 31 to 35 Multipliers 25, 36, 47 to 50, 55 Adder 26 Horizontal low-pass filter (H-LPF)
41-46, 52-54 Shift register 51, 56 Subtractor

Claims (4)

A filter circuit that receives a luminance signal obtained by performing predetermined signal processing on a pixel signal output from the solid-state imaging device, and provides a predetermined frequency characteristic in a vertical direction,
A luminance signal processing circuit in an imaging device, comprising: a characteristic varying unit that substantially varies a frequency characteristic of the filter circuit according to a state of the luminance signal. The filter circuit includes a vertical high-pass filter to which the luminance signal is input, and a vertical band-pass filter to which the luminance signal is input, and the characteristic varying unit outputs the vertical high-pass filter an output signal of the vertical high-pass filter. A first multiplier for multiplying by a coefficient K, a second multiplier for multiplying an output signal of the vertical bandpass filter by a coefficient (1−K), and an output signal of the first and second multipliers 2. The luminance signal processing circuit according to claim 1, further comprising an adder that performs the operation. The filter circuit includes a plurality of first multipliers to which luminance signals of a plurality of lines of a first field are separately input, and a plurality of second multipliers to which luminance signals of a plurality of lines of a second field are separately input. And an adder for adding and combining the respective output signals of the first and second multipliers. The characteristic varying means calculates the multiplication coefficients of the first and second multipliers respectively by the luminance signal. The luminance signal processing circuit according to claim 1, wherein the luminance signal processing circuit is a unit that changes according to a situation. When the output signal of the solid-state imaging device with respect to the incident light transmitted through any of the plurality of color filter units constituting the color filter provided on the incident light side of the imaging region of the solid-state imaging device is saturated, the characteristic variable 4. The luminance signal processing circuit according to claim 1, wherein the luminance signal having a frequency characteristic from which a high frequency component in a vertical direction is removed is output by the means.

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