JPH07212309A - Signal disconnection detection circuit - Google Patents

Abstract

PURPOSE:To exactly judge the disconnection state of an input signal and the input state of the signal. CONSTITUTION:Input signals (a) inputted from an input terminal T1 are successively delayed by delay circuits 2-1 to 2-N, and the input signals (a) are latched to flip flops 3-1 to 3-N by these delayed signals b1 to b3. By inputting these latched signals C1 to C3 in an AND element 1, the disconnection of the input signal is decided from a self correlation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal disconnection detecting circuit for preventing malfunction due to noise or the like and detecting an input disconnection from a transmission line.

[0002]

2. Description of the Related Art Conventionally, a signal disconnection detection method in an optical digital transmission system has been based on a photoelectric conversion circuit provided in a repeater or a terminal station and a multiplication factor of the photoelectric conversion circuit based on peak detection of a photoelectrically converted electric signal. An automatic gain control circuit (hereinafter abbreviated as "AGC") for controlling the output has been used.

This prior art method detects the peak value of the output voltage of the AGC by utilizing the fact that the multiplication factor of the photoelectric conversion circuit and the gain of the AGC are maximized when the optical input signal is cut off. The signal disconnection is detected from this peak value.

Further, in this prior art, a method has been proposed in which a timing signal is extracted from a received signal from a transmission line to identify the transmission line signal. In this method, since the timing signal component in the clock extraction unit becomes small when the signal is broken, the signal break is detected by determining the level of this signal.

[0005]

However, in the above-mentioned prior art, since the multiplication factor of the photoelectric conversion circuit largely depends on the temperature, the detection of the signal disconnection becomes inaccurate only by detecting the peak value of the output voltage of the AGC. There is. That is, since the output voltage and the signal level are directly detected, when the input signal is cut off, the detection value cannot be obtained even though the detection value does not have sufficient reliability. There is a problem.

Further, since there is a slight level difference between the timing signals at the time of signal input and at the time of signal disconnection, it is difficult to identify this difference. When the optical signal is cut off, noise from the photoelectric conversion circuit and AGC is amplified, and it is as if the optical signal was input.
There was a problem that wrong operation was performed.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a signal disconnection detection circuit capable of correctly determining the disconnection state of an input signal and the signal input state.

[0008]

In order to achieve the above object, the present invention is a digital transmission system having an equalizing and amplifying and identifying section, wherein an input signal from the identifying section is a predetermined threshold of an isolated pulse in digital communication. A delay circuit that generates a plurality of signals with different phases by sequentially delaying within the rising and falling phase width of the value, and comparing the phase states of the input signal and the plurality of signals, respectively A plurality of flip-flop circuits that output the result of and the signal for determining the normal signal input time and the input signal disconnection time by detecting the autocorrelation of the input signal from the logical product of the output signals of each flip-flop circuit. And a logical product circuit for outputting.

[0009]

According to the present invention, within a period of one cycle corresponding to the transmission rate of the input signal, the input signal is sequentially delayed by the delay circuit to create N signals having different phases, and the N signals are generated. By adding to the corresponding N flip-flops, the phase match / mismatch with the input signal is obtained,
By inputting the result of the match / mismatch to the AND circuit, the level signal is output when the signal has autocorrelation, and the AC signal is output when the signal does not have autocorrelation. Therefore, it is possible to accurately determine whether the normal input signal state or the input signal disconnection state is based on the signal form from the AND circuit.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a signal break detection circuit according to the present invention.

In FIG. 1, T1 is an input terminal for receiving an output signal from a discrimination circuit or a clock extraction circuit (not shown) provided in the preceding stage, and this input terminal T1 has:
A plurality of (N) delay circuits 2-1 to 2-N for sequentially delaying the signals input thereto are continued. Here, the number N of delay circuits is 1 / bit width of the input signal is 1 /
Select to be (N + 1). Also, the input terminal T1
Is also connected in parallel with data input terminals D of N flip-flop circuits (hereinafter abbreviated as FF) 3-1 to 3-N, and clock input terminals CP of FFs 3-1 to 3-N. The output terminals of the delay circuits 2-1 to 2-N are respectively connected to.

The output terminals of the FFs 3-1 to 3-N are connected to the input of the logical product element 1, and the output terminal of the logical product element 1 is connected to the output terminal T2.

Next, the operation of this embodiment configured as described above will be described with reference to the timing charts of FIGS. For convenience of explanation, a case of N = 3 will be described here.

FIG. 2 is a timing chart when the input signal to the input terminal T1 shown in FIG. 1 is normal, where a in FIG. 2 is the input signal to the input terminal T1, and b1 in FIG. 2 is the first signal. 2 shows the output signal of the delay element 2-1, b2 of FIG. 2 shows the output signal of the second delay element 2-2, and b3 of FIG. 2 shows the output signal of the third delay element 2-3. Further, C1 of FIG. 2 shows the result of latching the input signal a of the input terminal T1 in the FF 3-1 by the output of the first delay element 2-1 and C2 of FIG. 2 shows the result of latching in the FF3-2 by the output of the delay element 2-2, and C3 in FIG. 2 shows the result of latching the input signal a of the input terminal T1 in the FF3-3 by the output of the third delay element 2-3. Shown respectively.

The outputs of these FFs 3-1 to 3-3 are input to the logical product element 1, and the output result is shown in d of FIG.

FIG. 3 shows a timing chart when the input signal to the input terminal T1 shown in FIG. 1 is abnormal. 3a shows an abnormal input signal to the input terminal T1, b1 of FIG. 3 shows an output signal of the first delay element 2-1 and b2 of FIG. 3 shows an output signal of the second delay element 2-2. , B3 in FIG. 3 shows the output signals of the third delay element 2-3, respectively. Also, C in FIG.
1 is the first delay element 2-1 for the input signal a at the input terminal T1.
The result latched in FF3-1 by the output of
2 receives the input signal a at the input terminal T1 from the second delay element 2-2
The result latched in FF3-2 by the output of
3 receives the input signal a of the input terminal T1 from the third delay element 2-3
The results of latching in FF3-3 by the output of FIG. The outputs of the FFs 3-1 to 3-3 are logical product elements 1
And the logical product is output. The output result is shown in Fig. 3.
Of d.

In the present embodiment as described above, in the period of one cycle corresponding to the transmission rate of the input signal a, the signal is sequentially delayed by the delay circuits 2-1 to 2-3 and three signals having different phases are provided. Signals b1 to b3 are created, and the phase states of the signals b1 to b3 and the input signal a are set to FF3-1 to FF3.
-3, and the result signal of coincidence / non-coincidence obtained therefrom is input to the logical product element 1 and three delay signals b1 to b3 are input.
Depending on the result of whether or not the input signal a and the input signal a match, a level signal is obtained when there is autocorrelation (normal), and an irregular alternating pattern when there is no autocorrelation (signal disconnection). The signal is obtained.

Therefore, by providing a circuit for coefficienting the alternating pattern for a fixed time in the next stage of the signal disconnection detection circuit shown in this embodiment, the judgment result at the time of normal signal input and at the time of input signal disconnection is binary. It can be expressed by logic, and the states of both can be correctly determined.

[0020]

According to the present invention, as is apparent from the above embodiment, when the input signal is normal, the signal exhibits synchronism corresponding to the transmission speed, and when the input signal is interrupted, it exhibits irregularity due to noise. By utilizing the characteristics that the autocorrelation of the input signal is detected by the delay circuit, flip-flop and AND circuit, it is possible to accurately determine whether the input signal state or the input signal disconnection state. This has the effect of significantly improving the reliability of disconnection detection.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal loss detection circuit of the present invention.

FIG. 2 is a timing chart showing an operation when a normal signal is input in this embodiment.

FIG. 3 is a timing chart showing an operation when an abnormal signal is input in this embodiment.

[Explanation of symbols]

 T1 input terminal T2 output terminal 1 AND element 2-2 to 2-N delay circuit 3-1 to 3-N flip-flop

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04B 10/04

Claims (1)

[Claims] 1. A digital transmission system having an equalizing and amplifying and discriminating section, wherein an input signal from the discriminating section is sequentially delayed within a phase width of rising and falling at a predetermined threshold of an isolated pulse in digital communication, and then phased. A delay circuit for generating a plurality of different signals, and a plurality of flip-flop circuits for comparing the phase states of the input signal and the plurality of signals and outputting the result of the matching / mismatching, A signal disconnection detection circuit comprising: a logical product circuit that detects autocorrelation of an input signal from a logical product of output signals of a flip-flop circuit and outputs a signal for determining whether a normal signal is input or an input signal is disconnected.