JPH0721109A - Integrated system of data communication from human interface device - Google Patents

Abstract

PURPOSE: To provide a system integrating a human interface such as work station or personal computer and a display through the human interface of CHI combination. CONSTITUTION: A CHI is connected to a display unit 130 as an integrated unit to be used for communication with a host computer and a human interface device 170 such as a keyboard 172, mouse 174, write pen 176 and audio/video input device 178, and made into system for which a back panel or the like to be physically connected is unnecessitated. Besides, the display unit 130 and a host system 110 are determined by a bidirectional serial line and simplified data communication is supplied.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to user interfaces, and more particularly to systems for integrating the human interface and display control of workstations or personal computers.

[0002]

BACKGROUND OF THE INVENTION In prior art user interface devices or human interface devices, a user is allowed to interact with a processing unit of a computer. What the device allows is that the user issues commands to the processor and receives messages from the processor. Generally, all cables for human interface devices such as displays, keyboards and positioning devices are physically connected to the processor box. The first disadvantage of this configuration is that in these human interface devices back panel and board
Space is in use, otherwise it is in use for peripheral devices such as printers and disk drives. Other disadvantages are
Installation inconvenience due to all cable connections routed to the back panel. This cable connection allows for electromagnetic interference (EMI) and electrostatic discharge (E).
There are additional disadvantages that are the cause of the SD) problem.

[0003]

Accordingly, electromagnetic interference (EMI) is associated with a system for integrating the human interface and display control of a workstation or personal computer.
And, there is a problem that must be solved to solve the problem of electrostatic discharge (ESD).

[0004]

In order to solve the above problems, according to the present invention, a system for integrating a human interface and display control, known as a combined human interface (CHI). Will be provided. The CHI system combines all human interface devices in one centralized point, such as a display unit. display·
A bidirectional CHI serial line between the unit and the host is provided for data communication. The use of centralized interface points eliminates the need for many dedicated back panel slots. Another advantage of the present invention is the ease of proof (recognition) and control of the display itself such that it can be accessed as any other device on a bidirectional CHI serial channel.

Generally, in CHI systems, the unused bandwidth present in the video cable for the display is used. Because of this, no additional cable connections or connectors are required. VGA
To 1280 x 1024 workstation display monitor timing schemes, given enough unused unused capacity to accommodate all keyboards and positioning devices, as well as audio input and output at full CD rates. There is bandwidth. Host system processing unit (SPU) and human
Bidirectional communication is provided across the video cable to and from the interface device. The various devices are either directly connected to the display or via the display to auxiliary boxes.

Asynchronous, serial communication schemes are used in CHI systems to allow data communication to occur during horizontal and vertical blanking intervals. Asynchronous serial data is transmitted on the video line in exactly the same manner as a normal sync pulse. This allows non-CHI-
Convenience to the system is acceptable.

The CHI system consists essentially of two subsystems. (1) One of which follows the sync pulse separation means in the display unit,
Alternatively, the CHI incorporated in the synchronizing pulse separation means
Circuit (2) The other consists of a host side interface circuit for accepting input data, and an additional data path in the host system for disabling video output. . The CHI circuit has two operation modes. During normal operation (ie, when no CHI data is present), CHI
The circuit only passes the sync pulse received from the separating means to the deflection circuit. When human interface information is present, the CHI circuit generates a normal sync pulse for use by the monitor and conveys it to the interface device through the human interface signal for the second output. video·
Due to the unused bandwidth of the line, transmission of all CHI data will occur during the horizontal and vertical blanking periods.

The second subsystem is included in the host processor. To accept the data from the video line, the video output must be disabled. The sync driver present in the video DAC has been modified to fit both the video data input and the sync input. The DAC is an output enabled to select the line it accepts.

Transmission of human interface data (ie, data transmitted via the CHI system)
Is initiated by the host system, which is the preferred method of data transmission. What is established in this way is that such transmissions do not interfere with the normal video operation of the host system. First, the poll request signal can be transmitted from the host system. This puts the CHI circuit in the normal mode and allows the data to return to the host system. Human interface data transmission, or CHI data transmission, will typically end prior to the horizontal blanking period. CHI data capacities for a 25 MHz clock and fixed channel access times range from about 180 kilobytes per second (kbytes / sec) for standard VGA display systems to about 460 kbytes for high resolution workstation displays. The range is up to / sec. These data rates can easily be increased as the clock rate and / or the channel access time increase.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A system for integrating human interface and display control information according to the present invention will be described below with reference to the drawings. Figure 1
FIG. 1 is a high level block diagram of a computer system embodying the present invention. Host system 110
Controls the display unit 130 via the video line 120. The video line 120 is bidirectional and can transfer data to and from the display unit 130. The display unit 130 is the logical heart of all user input / output functions. An auxiliary box (not shown) can be connected to the display unit 130 and used as the input / output center.

Block 170 is connected to the display unit 130 and represents various human interface devices, eg, (1) block 172 is a keyboard; (2) block 174 is like a mouse. A positioning device; (3) block 176 can be a light pen; and (4) block 178 can be an audio input device.
Other human interface devices can be used in block 170, and many devices can be scaled up or down without departing from the spirit and scope of the invention. Display unit 13
The route formed through 0 eliminates the need for a separate ancillary box due to this configuration with all human interface devices, and
The additional advantage of easy connection of the display to the interface is provided.

FIG. 2 is a block diagram of a computer system formed incorporating a combined human interface. Circuitry included in host system 210 controls display unit 230, in this case graphics card 21.
Controlled by 2. A CHI (combined human interface) circuit 250 resides within display unit 230 and communicates with host system 210 via CHI interface circuit 213. The video line 220 arrives at the CHI circuit 250 via the data line 260 and carries all the data traffic that can be done by a human interface device, such as a keyboard, mouse, etc. (see block 170 in FIG. 1). Similarly, it carries all video data between the host system 210 and the display unit 230. The data transmitted to and from the human interface device, known as CHI data, is transmitted asynchronously by the video line 220, which is derived from the positioning information sent by the mouse to the host system 21.
Even the audio data generated by the 0 and returned via the display unit 230.

Although the video line 220 can also carry both horizontal and vertical sync signal pulses, according to another preferred embodiment, both sync pulses are transmitted to the host.
Transmission is via a sync line 222 from the system 210 to the display unit 230. In yet another embodiment, two separate lines (not shown) are provided, each for host system 210.
And horizontal and vertical sync pulses between the display unit 230 and the display unit 230.

FIG. 3 is a more detailed block diagram of the display unit according to the present invention. display·
Unit 330 (210 in FIG. 2) is a video
Video data, various human interface device data, and synchronization data are received via line 320 (220 in FIG. 2). Sync stripper means 332 removes the horizontal and vertical sync pulses from video line 320 and diverts these signals to sync separation means 336. Note for this embodiment that there is a sync-on-video scheme. Other schemes, such as separate sync lines, work in a similar manner to that described below. Data will also be transmitted on at least these lines that carry horizontal synchronization information. All video data passes through video amplifier 334 to display 340. In the preferred embodiment, this display 340 is a CRT.
Is. Other displays, such as liquid crystal displays, can be used without departing from the scope of this invention.

The sync separation means 336 includes a low pass filter and a high pass filter for separating a horizontal pulse and a vertical pulse. Both horizontal and vertical pulses pass through horizontal and vertical deflection circuits (shown as a separate block 338), respectively. Deflection circuit 338 then transmits these pulses to the horizontal and vertical controllers in display 340.

The sync separator 336 also receives the human interface data transmitted with the sync pulse, eg forwarded by the keyboard. Since the horizontal blanking cycle is about 20-25% of the total horizontal line time, most interface
The data will be transmitted during this time period.
The CHI circuit 350 is arranged between one output of the sync separation means 336 and the deflection circuit 338. During normal operation, ie when there is no human interface data from the keyboard, mouse, etc., the horizontal sync pulse simply passes through the CHI circuit 350 towards the horizontal deflection circuit.

When human interface data or CHI data is present on video line 320, CHI circuit 350 produces a standard sync pulse for the horizontal deflection circuit, and on interface control 360. CHI data passes. C
At least one additional transition is provided that immediately follows the leading edge of the horizontal sync pulse so that the HI circuit 350 can identify the presence of CHI data.

FIG. 4 is a diagram showing another embodiment of the present invention, in which the CHI circuit 4 is provided in the sync separation means 436.
There are 50. The CHI circuit 450 operates in a manner similar to that described with respect to FIG. In this embodiment, a CHI circuit (CHI-capability) can be easily manufactured because no additional integrated circuit chip is required.

FIG. 5 shows the CHI interface 513 present in the host system 510.
Since all CHI data is transmitted with the normal sync pulse, only minor modifications to the host system 510 are required. CHI data is a video digital analog converter (DAC)
It can be transmitted by a synchronous driver present at 520.

The video DAC 520 included in the host system 510 drives the display unit via the video data line 508. DAC52
The two inputs that are input to 0 are the video data inputs 50
1 and sync input 502. Video data input 501
Is driven by the frame buffer / control unit 540, which in turn is followed by a host CPU (not shown).
Driven by. The OR gate 530 is the DAC 520.
To drive. This OR gate 530 has two input terminals, one of which is the sync data line 503 from the frame buffer 540 and the other of which is the CHI.
CHI data out line 504 from interface 513. Synchronous data line 503 or C
When data is present on any of the HI data out lines 504, the OR gate 530 causes the video DAC
Data can be sent to 520. CHI interface 5
13 via the output enable line 506 to the DAC
520 is controlled. The video output from the DAC 520 needs to be disabled to allow acceptance of data from the video data line 508 via the data-in line 507. This is done when the poll command is accepted by the CHI interface 513. A more detailed description of the CHI communication protocol is given below in FIG.

A typical horizontal video signal is shown in FIG. The y-axis is the magnitude of the luminance amplitude for the video signal. Its brightness is white video (A)
To Black Video (B).
What is represented by T1 is the time when the signal is active video. What is represented by T2 is the blanking period when the video signal is inactive so that the sync pulse can be transmitted. It is during this period T2 that the CHI data is transmitted.

A typical horizontal sync-on-video signal is shown in FIG. This signal can be observed as being of four distinct amplitudes. The luminance amplitudes for white video and black video are the same as those for white video (A) and black video (B) shown in FIG. The blank amplitude (C) contains a lower amplitude than black (B). Synchronization is represented by amplitude (D). T1 represents the cycle of active video. T2 is the front of the blanking cycle
It is a pouch. T3 is a period for transmitting the sync pulse. T4 is the back porch of the blanking cycle. The blanking period is of time equal to T2 + T3 + T4. In order for the host system to start transmitting the video data, C before the end of the blanking period (eg, before T4 or during T4), C
The transmission of HI data has to be stopped.

FIG. 8 is a timing diagram showing the basic CHI protocol. Type I signal 810 represents a normal sync pulse from T1 to T6 with no associated CHI activity. Type II signal 820 represents an outward transmission due to the first pulse present from T1 to T2. In the transmission which is recognized and written by the type II signal, the data is transmitted from the host system to the designated human interface device. This outbound data, beginning at T3 and transmitted forward, is represented by item 822. Type III signal 830 represents a polling request with a second pulse present from T3 to T4. This Type III signal is to be transmitted by the display unit to the host system, whose data content is transmitted beginning at T6 and is represented by item 832. Type IV signal 840 represents the response to the identification (ID) request by both the first and second pulses. The data is then transmitted beginning at T6 and is represented by item 842.

As illustrated in FIG. 8, CH
The transmission of I is identified by at least one additional transition that immediately follows the leading edge of the horizontal sync pulse at T1. Since the data is carried in three defined modes (ie, Type II, III and IV signals 820, 830 and 840), these signals cannot pass through deflection circuit 338 (see FIG. 3). . Thus, as shown in FIG. 3, CHI circuit 350 generates a normal sync pulse for deflection circuit 338,
Then, these three signals (type II, III, I
The data transmitted by V) will be passed to another output.

Returning to FIG. 8, the first (from T1 to T2)
What is meant by the presence of only pulses of is that the data follows from the host system and is transmitted according to the specified human interface device. The presence of only the second pulse (from T3 to T4) sets the CHI circuit 350 in transmit mode, and
One human interface device is allowed to send data back to the host system over a given period. (T1-T2 and T3-T4
C) circuit 35 when both pulses are present.
0 transmits ID information to the host system. Included in the data transmitted at this time are all human interface devices connected to display recognition and interface control 360 (see FIG. 3).

The transmission of CHI data is typically performed by the host
Initiated by the system. What is ensured in this way is that such transmissions do not interfere with normal video (ie the transmission of CHI data is done during the video blanking period). In one preferred embodiment, the Type II poll request signal shown in FIG. 8 is enabled to put the CHI circuit 350 into a transfer mode for the return of data to the host system. This is the CHI that disables the video DAC 520
Implemented by interface 513, enables CHI interface circuit 513 to drive video data line 508, as shown in FIG. Since the CHI interface circuit 513 or the display unit is driving the video data line 508, any inbound data transmission must be completed, prior to the end of the blanking period, the video data line 508 Is returned to normal use. Thus,
It can be seen that the time windows available for inbound transmissions are always limited and system dependent.

Upon entering a blanking period that maximizes the time available for CHI data transmission, the host system should immediately transmit a polling request. Given that the overall blanking period is available for data transmission, by looking at the standard horizontal blanking period (see Table 1 below), at least 3
It is indicated that a microsecond minimum window should be available.

[0028]

[Table 1]

Here, in order to calculate the capacity of the CHI channel, 25 MHz is estimated as a standard VGA clock. We estimate a 16-bit header for each data transmission so that the amount of time available for the actual CHI data is reduced to 2 microseconds. Clock 25MHz
In, the data transmission of about 48 bits is possible. If equal time is used during the horizontal blanking time and the vertical blanking period, then the overall data capacity is: That is, "48 bits x total number of lines per frame x number of frames per unit second". For example, for standard VGA timing, its overall data capacity is about 180 ROB / s. The data capacity for various technologies is summarized in Table 2 below.

[0030]

[Table 2]

In all cases, the CHI channel provides sufficient capacity to handle most human interface device inputs such as keyboards, mice, etc. It should be noted that the data presented in Table 2 has a transmission window of 3 microseconds and a data clock rate of 25.
It is based on the assumption of MHz. It is preferable to relax these numbers to increase the amount of data transmitted. For example, standard VGA 640x48
The 0,60 Hz timing has a horizontal blanking period of 6.6 microseconds, which allows a longer window of data transmission, thus increasing the transmission capacity of CHI data.

FIG. 9 shows one embodiment of the CHI logic. The programmable array logic (PAL) circuit 910 includes two counters 920 and 92.
Used in conjunction with 2. A typical program for the PAL circuit 910 is shown in [Typical PAL Program] described later.

The block diagram of FIG. 10 is intended to illustrate one method of integrating human interface data. Instructed at block 1010 is to monitor the video data line until a blanking period is detected by decision block 1020. When the video line enters the blanking cycle, at block 1030, a polling request is transmitted from the host system to the CHI circuit 350. What is ensured with this is that the CHI data transmission does not interfere with normal video operation. At block 1040, the CHI circuit 350 transitions from the first mode of operation (ie, normal video operation) to the second mode of operation (ie, CHI data transmission mode).
In the transmission mode of CHI circuit 350, represented by block 1050, CHI data is transmitted from one of the human interface devices to the host system via CHI circuit 350 in the display unit. After the transmission of CHI data is completed, CHI
Circuit 350 is caused to return to its first mode of operation, as indicated by block 1060.

Although the present invention has been illustrated and described in connection with the preferred embodiment, it should not be limited to the particular arrangements shown herein. It should be understood by those skilled in the art that many changes and modifications can be made within the scope of the claims without departing from the technical idea and scope of the present invention in a broader aspect. The present invention will be summarized below.

1. A display unit having first and second inputs, a first interface connected to the display unit having the first input, and a host process connected to the display unit having the second input A unit and a communication line disposed between the host processing unit and the display unit having the second input, the communication line having a capability of transmitting bidirectional serial data; and the first and second communication lines.
A display unit having an input, a display unit having the first and second inputs to control data communication between the first interface device and a host processor, the communication line An integrated system for data communication from a human interface device with a controlling CHI circuit.

2. An integrated system of data communication from a human interface device according to claim 1 wherein the video data, horizontal and vertical sync pulses, and interface data are carried by communication lines.

3. Interface control means connected to the CHI circuit for transmitting information to and receiving information from the first interface device; vertical sync pulses and horizontal sync pulses; A sync separating means 336 connected to the CHI circuit for distinguishing, and a sync stripper means 33 connected to the sync separating means for extracting the sync pulse from the communication line and transmitting the sync pulse to the separating means.
2 (432) and a video amplifier 334 connected to the sync stripper means for receiving the video data remaining after the sync pulse has been extracted from the communication line. 2. An integrated system for data communication from a human interface device according to item 2.

4. A video DAC 520 connected to the communication line for transmitting data to the display unit and a video DAC 520 for receiving interface data from the display unit.
And a CHI interface 513 connected to and capable of disabling the video DAC via an output enable signal line, and a human interface according to paragraph 2 further comprising a unit for processing by the host.
An integrated system of data communication from the device.

5. A system for integrating data communication from a human interface device, the display unit having first and second inputs, transmitting information to the first interface device, and the first interface Interface / control means 360 connected to the CHI circuit for receiving information from the device, sync separation means 336 (436) connected to the CHI circuit for distinguishing between vertical and horizontal sync pulses , A sync stripper means 332 connected to the sync separating means for extracting the sync pulse from the communication line and transmitting the sync pulse to the separating means, and video data remaining after the sync pulse is extracted from the communication line. Video amplifier 334 connected to the synchronous stripper means for receiving , At least one interface device connected to the first input of the display unit, a host processing unit connected to the second input of the display unit, and between the host processing unit and the second input Has been placed,
A communication line having the ability to transmit serial data in both directions and a display unit, at least one interface device, and a synchronization separation means for controlling data communication between the host processor and communication. CHI circuit 35 for controlling the line
An integrated system of data communication from a human interface device having a configuration including 0 (450).

6. It is an improvement of the above-mentioned fourth modified example, which includes a host processing unit, a display unit and a video line, and the video line carries active video data and video data consisting of a plurality of blanking periods. For integrating data communication from multiple human interface devices in a system comprising: (1) a host processing unit to a CHI circuit having first and second modes of operation in a display unit. Then, immediately after entering the blanking cycle, a polling request signal is transmitted, (2) the CHI circuit is shifted from the first mode to the second mode, and (3) a plurality of human interface devices. Data from one of the From the human interface device including the steps of: (4) and (4) transitioning the CHI circuit from the second mode to the first mode after the data transmission in step (3) is completed. How to integrate data communication.

Next, specific programs that operate in the CHI logic shown in FIG. 9 will be listed.

[Representative PAL Program] {[pd], HP-UHL In-house PAL description written by PAL compiler} pal chi 16r8; input sync in, {horizontal synchronization path from display synchronization separation means} rco, {Loss input} {Ripple carrier output from the counter; when this becomes Ha} {When the counter goes to 25MHz, the counter is 25MHz} {Lock (10.24us passed) 25} {6 Completion Mean; this} {ends ID transmission with} state0, state1, delay, nclrcount, id, sync out, count [7. ． 0]; {out of 25 MHz clock} {8 bits from a partial counter} output nclrcount, {signal for controlling the counter mode} {; when high, the counter normally operates} {low {Out clears} sync out, {for displaying horizontal deflection circuit} {horizontal sync output} delay, {of one state delayed sync in} {version} data to hio , {Local human I / O device} {Serial data output to scan} state0, {state ID bit used as follows} state1, {state1 state0} {CHI transmission none 0} {data 0 from host 0 1} {Data to host 1 0} { ID 1 1 to host} {Note: the actual PAL output is from this table} {inverted; the signals shown above are as they are used in P} {AL,} {and also below {Existing} id; {used internally for signaling ID transmission} {type} pal type '16R8'; pal pin order {1 2 3 4 5} clock, sync in, data in, rco, nc, {6 7 8} count [5], count [4], count [3], {9 10 11 12 13} count [2], gnd, ~ oe, delay, id, {14 15 16 17} nc, state1, state0 data to hio, {18 19 20} syn out, nclrcount, vcc;} begin {recognition of CHI control signal and setting of status bit} delay: = sync in; nclrcount: = delay + state0 + state1; data to hio: inate; 0 * sincate; {External counters are kept clear until synchronization is asserted;} {Then, unless CHI transmission occurs (state0 or st} {either rate1 is high) count until the end of synchronization} { However, in this case, the run continues until the transmission is complete}. } {By the following CASE description, control of state0 and state1} is executed. What is watched at the PAL is a delayed version of the sync asserted} {is a delayed version of the sync for the 4 clocks later; the corresponding} {if this line goes to zero during time, the first CHI A pulse will be generated and then we will be at least at the CHI rate transmission (set state0 bit)}. During the next 4 clocks, PAL looks for another transition to zero} {although this happens when the second CHI pulse is given. In this case, {in this case, the flag of state1 will be set (stat} {depending on whether e0 is set first, read or ID transmission} {instruct to send )} Case id, count [5. ． 2] of 0: begin state0: = (ncrlcount * not delay) + state0; state1: = 0, sync out: = 0; end; 1: begin state0: = state0; state1: = not delay delay + = 0; end; 2: begin state0: = state0; state1: = not sync in + state1; sync out: = 0; end; 3: begin state0: = state0; state1: = state1; sync = out = sync = state. + State0); end; 4: begin state0: = state0; state1: = state1; sync out: = sync out; end; 5: begin state0: = state0; state1: = state1; sync out: = sync out; end; 6: begin state0: = state0; state1: = state1; sync out: = 1; end: in: 7: beg = State0; state1: = state1; sync out: = 1; end; 8: begin state0: = state0; state1: = state1; sync out: = 1; end; 9: begin state0: = state0; state1: = state1 sync out: = 1; end; 10: begin state0: = state0; state1: = state1; sync out: = 1; en d; 11: begin state0: = state0; state1: = state1; sync out: = 1; end; 12: begin state0: = state0; state1: = state1; sync out: = 0; end; 13: begin = state0 state0; state1: = state1; sync out: = 0; end; 14: begin state0: = state0; state1: = state1; sync out: = 0; end; 15: begin state0: = 0; state1: = 0; sync out: = 0; end; otherwise state0: = not rco; state1: = not rco; end; {Regarding case description} end. ;; PAL Attribute File is / user / local / lib / pd-devices ;; Using structure into for "16R8" ;; @ (#) 88/11/02 2.2 b16r8 / DATA SHIN: / DELAY: = / SYNC IN / ID: = / STATE0 + / STATE1 / NCLRCOUNT: = / DELAY * / STATE0 * / STATEE1 / STATE0: = DELAY * / ID * / STATE0 + RCO * IDU + ** IDU + * ] * COUNT [4] * COUNT [3] * COUNT [2] + / ID * COUNT [5] * / STATE0 + / ID * COUNT [4] * / STATE0 + / ID * COUNT [3] * / STATE0 + / ID * COUNT [2] * / STATE0 + / ID * / STATE0 * NCLRCOUNT / STATE1: = RCO + ID + / ID * COUNT [5] * COUNT [4] * COUNT [3] * COUNT [ 2] + / ID * COUNT [5] * / STATE1 + / ID * / COUNT [5] * / COUNT [4] * / COUNT [3] * / COUNT [2] + DELAY * / ID * COUNT [2] * / STATE1 + / ID * COUNT [4] * / STATE1 + / ID * / COUNT [3] * SYNC IN * / STATE1 + / ID * / COUNT [3] * COUNT [2] * / STATE1 / SYNC OUT: = ID + COUNT [5] * COUNT [4 + / COUNT [5] * / COUNT [4] * / COUNT [3] + / COUNT [5] * / COUNT [4] * / COUNT [2] + / COUNT [5] * / COUNT [4] * STATE0 + / COUNT [5] * / COUNT [4] * STATE1 + / COUNT [5] * / COUNT [4] * / SYNC OUT

[0043]

With the configuration described above, the system for integrating the human interface and the display control information according to the present invention,
All human interface devices can be combined in one centralized point, bidirectional CH between display unit and host
Data communication can be performed by the I-serial line, and the use of a centralized interface point has an extremely excellent effect that many dedicated back panels are unnecessary.

[Brief description of drawings]

FIG. 1 is a top level block diagram of a computer system incorporating the present invention.

[Fig. 2] Human interface (CH
I) is a block diagram of a computer system incorporating the circuitry.

FIG. 3 is a more detailed block diagram of a display unit incorporating a CHI circuit according to the present invention.

FIG. 4 is another embodiment of a display unit incorporating a CHI circuit.

FIG. 5: CH in host system according to the present invention
It is a figure which shows an I interface.

FIG. 6 is a diagram showing a representative horizontal video signal.

FIG. 7 illustrates a representative horizontal sync-on-video signal.

FIG. 8 is a timing diagram illustrating the basic CHI protocol according to the present invention.

FIG. 9 is a diagram showing a more detailed embodiment of the CHI circuit.

FIG. 10 is a block diagram of a preferred method for integrating user interface data and display control information.

[Description of Reference Signs] 110 host system 120 video line 130 display unit 170 human interface device 172 keyboard 174 positioning device (mouse) 176 light pen 178 audio input device 210 host system 212 graphics card 213 CHI Interface Circuit 220 Video Line 222 Sync Line 230 Display Unit 250 CHI Circuit 260 Data Line 320 Host System 332 Sync Stripper Means 334 Video Amplifier 336 Sync Separation Means 338 Deflection Circuit 340 Display 350 CHI Circuit 360 Interface Control 362 ID ROM 364 Display control 420 Host system 432 Synchronization Tripper Means 436 Sync Separation Means 450 CHI 501 Video Data Input 502 Sync Input 503 Sync Data Line 504 CHI Data Out Line 506 Output Enable Line 507 Data In Line 508 Video Data Line 520 DAC 530 OR Gate 540 frame buffer / control unit 910 PAL circuit 920 counter 922 counter

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location G06F 13/00 354 D 7368-5B

Claims (1)

[Claims] 1. A display unit having first and second inputs, a first interface connected to the display unit having the first input, and a display unit having the second input. A connected host processing unit, a communication line disposed between the host processing unit and the display unit having the second input, the communication line having a capability of transmitting bidirectional serial data; And a display unit having a second input, disposed on the display unit having the first and second inputs for controlling data communication between the first interface device and a host processor, A human interface comprising a CHI circuit for controlling a communication line. Data communication of the integrated system from the interface device.