JPS60196036A - Remote control output branch unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a communication link for an information handling system having a data display terminal remote from a central processing unit.

[Prior art]

Known information handling systems typically employ one or more host processors with a number of remotely located data terminals. When an operator enters data or commands at a terminal, the data or commands are sent to a host processor for processing. Results or commands to be displayed are sent back to the host or display terminal. In addition, the terminal may provide only a display function (for example, a print function). Such information handling systems often include several display control processors along with a processor dedicated to managing the flow of data between a central processing unit and a group of display terminals. As an example, US Pat. No. 4,271,479 discloses an information processing system 11 having a display control processor used to control a plurality of display terminals. This US patent uses a Display Cluster Adapter (DCA),
A message is sent from the control processor onto one of the 32 transmission lines driven by the driver/receiver module associated with that DCA. If the display terminal is D
If the location is remote from the CA, the cabling cost of such a system increases. Moreover, existing wiring systems cannot accommodate the large amount of cables, making them impractical in many cases.

One possible solution is to multiplex multiple signals,
It is a single cable from the driver/receiver to the terminal. An example of this solution is 13M company I'1)13 (1
Published in November 1975), pages 1955-1956. The solution disclosed therein is to create a unique frequency tone representing each line and display terminal address.

The frequencies 1 to 1 are transmitted along with or before the data signal over a single coaxial cable. Each terminal connected to a single cable has a frequency selection filter tuned to receive a particular one of a plurality of unique frequencies. When the 1-tone is detected, the terminal passes the data signal along with or following that frequency tone.

This solution requires the addition of several analog circuit elements to the existing digital circuit. In addition, the interactive cable must have sufficient bandwidth to transmit the digital signal and unique frequency 1-tone to each display terminal connected to the cable. In order to maintain compatibility with existing digital circuit transmission links, it is highly desirable to use only digital circuits.

[Problem that the invention seeks to solve]

The present invention seeks to solve the above problems of the prior art by providing a simple remote output branch that is easy to install in existing circuits and significantly reduces cable installation cost and space.

The object of the invention is to provide a simple output box (
An object of the present invention is to provide an information processing system having a fan-out box) device.

A related purpose is to create an information processing system in which messages from the DCA to multiple display terminals are aggregated onto a single transmission cable and separated by output branch boxes located one distance from the CA and near the display terminals. It is to provide.

Other purposes include inserting device addresses into messages transmitted over a single cable from the DCA to the receiver, and a remote output branch for decoding the inserted addresses and distributing received messages accordingly. The purpose is to provide equipment.

Yet another object is to provide a remote output box for receiving, decoding and distributing messages having inserted display terminal addresses.

[Means for solving problems]

The present invention uses the digital information provided by the display cluster adapter to form a digital address pie that is prepended to outbound data messages. The additional address byte contains the address of the display terminal to which the data is sent. The data, preceded by the address byte, is then sent to the remote output branch.

The output branch box strips the address byte from the data, decodes the stripped address byte, and routes the data to the correct terminal according to the decoded address byte. Because each message transmitted from a driver/receiver associated with an OCA has a unique address byte associated with it, a single It is possible to use transmission cables.

Since the concentration of messages transmitted to multiple display terminals over a single transmission cable is transparent to the DCA, the display cluster adapter does not require modification to incorporate an output splitter. The DCA provides the same output signal to driver/receiver modules for both single-cable and dual-cable transmissions. The signal provided by the DCA that would normally be used by a driver/receiver module to select one of multiple cables for transmitting a message is instead provided by the driver/receiver module to form an address byte. The byte is then prepended to the message to be transmitted on a single cable.

In addition, since outbound data messages are added to Address Pi 1 during transmission, they can be sent to any terminal in any order. Furthermore, the use of an output diverter device essentially doubles the range of data terminals that can be detected from the DCA. A driver/receiver circuit in the DCA can transmit a message to an output branch over a first distance. The output branch includes a similar driver/receiver circuit capable of transmitting a message a second distance substantially equal to the first distance.

〔Example〕

In the information processing system shown in FIG. 1, a display control processor 1 is connected to an l10 (input/output) bus 2. I10
Bus 2 is connected to a local host adapter 3, the latter to a central processing unit (CPU) 4.

A remote CPU (not shown) is connected to the bus 2 via a communications line 6, a modem 7, and a communications adapter 8. remote CPU,
Local CPU 4, or both, may act as a host and provide application and program instructions to processor 1 in a manner well known to those skilled in the art. Bus 2 carries data and control signals at the central processing unit and processor.

To support an I10 device in accordance with the present invention, a display cluster adapter (DCA) 9 is connected to communicate with bus 2 to control the transmission of messages between processor 1 and driver/receiver module 11. module 11
are respectively output branch boxes (fan-out boxes FOB
) 16-19, supporting a series of serial transmission links such as coaxial cables 12-15.

For this purpose, the module 11 connects each line 12 to
Contains separate driver/receiver circuits for 15. Each output branch box 16-19 has a coaxial cable 21-24
supports a group of serial transmission links such as ``Each cable allows bidirectional traffic to a respective input, output, or input/output device.

For this purpose, each output branch box 16-19 is connected to each line 21-24.
Each has a separate driver/receiver.

Although driver/receiver module 11 is shown having four I10 wires and each output branch 16-19 having eight I10 wires, these numbers are merely exemplary.

2 keyboard display devices 26, 27, display only device 2
8 and a printer 29 are shown as typical data terminal devices included in the information processing system. Display device 26
acts like a console for the system, and a similar keyboard display device 27 includes a CRT 31 and a keyboard 32. The displays 26-28 and printer 29 serve to output information from the system, and the keyboard serves to input information and operator instructions into the system.

Other types of information and control signal input devices, such as a programmable keyboard 33, a magnetic strip card reader 34, and a light pen 36, may provide data input and control to the system in addition to or in place of the keyboard 32.

In the prior art, such as US Pat. No. 4,271,479, the DCA acts as a poller/multiplexer to select one of the 32 l10 wires attached to its driver/receiver module. In this prior art, each of the 32 I10 wires must be run the entire distance to the respective I10 device. The DCA selects one of the four driver/receiver cards in the driver/receiver module and uses one of the eight lines from that driver/receiver card to carry the message. select. This is accomplished using a 5-bit device address register located in the DCA that contains the top two bits used as car select bits and the bottom three bits used as line selection or device address bits. This is a typical example. As illustrated in FIG. 3, according to the present invention, the DC
It is possible to modify the driver/receiver module without modifying the A itself. The modified driver/receiver module 11 is inserted into every 1-bound message immediately before the outbound information word 8.
To form bit address pie 1~, DCAe
using the device address registers pre-existing in the .

An example of a data signal sent from driver/receiver module 11 via lines 12-15 to output boxes 16-19 is shown in FIG. The outbound signal is one 8-pitch 1 ~ start end sequence, one 8-pix I ~ address pi 1 ~
, and one or more 12-bit information words.

The information word is suitable for transmitting all commands and data between display devices 26-29 and the rest of the information handling system.

As shown in Figure 2, transitions in the middle of bits indicate valid bits, and falling transitions such as transition 38 indicate valid bits.
1'', and rising transitions such as transition 39 indicate rOJ, respectively. The start-edge sequence includes multiple line pause pulses 41 followed by a start-edge code violation (the absence of a bit-center transition is called a violation; this is illustrated, for example, by the absence of a pin-to-center transition during time 42.43). It consists of Between two such violations of code 1,
”, and following that violation there is a busy bit representing another “1”. The busy bit is the pin 1 of the transmitted byte (in this case address byte 1).
−1t]. I-less part-time job pill-#2~
#4 is the device 71 to which the message is sent. Bits #5-#7 are not present in this example, so rOJ is sent. Bit #8 is the parity bit 1- [1
” is listed as 1-.

Following the address byte is a 12-bit information word with pill position #1 beginning with busy pin 1-. Pi 1 to #@#], 3 indicates the beginning of a terminal court violation.

In the illustrated example, pin 1 to position #13 are "0", indicating the end of data transition.

If bit position #13 was a "1", an additional 12-bit information word would immediately follow.

Note that address bytes are only present in messages sent from driver/receiver module 11 to output boxes 16-19. Data messages passing between output boxes 16-19 and terminals 26-29 do not contain address bytes, but instead consist of a beginning sequence followed by an information word immediately followed by a termination code violation.

Similarly, messages sent back to driver/receiver module 1 from output branch boxes 16 to 19 are sent to address by 1.
I don't have anything to do with it. This is because any message sent from a terminal to the driver/receiver module 11 via the output branch is in response to a poll request or other command sent to a particular terminal. Therefore, the message received by driver/receiver module 11 in response to a command must have come from a terminal that has already been 71-responsed. Details of this operation will be described later.

FIG. 3 shows a circuit for inserting address PI1~ into ARA1~ bound message. The display cluster adapter 9 has several signals connected to the driver/receiver module 11, namely a clock signal (CK) on line 44, a clock signal (CK) on line 46;
output data (DAT○) on line 47, delayed transmission enable signal (DXE) on line 47, etc. In addition, DCA
9 is 5 pins 1 - device address register (DAR) 4
Has 8. The second two digits of register 48, P1 (I3, R4), are card selection bits, and the lower three digits, PHI (ROlR1, R2), are device address bits. In the prior art system, car 1 and selection bins 1 to 4
The device address pin 1- is used to select one of the eight T/'O devices on that selected card. was used to select. Registers 48 are typically loaded by processor 1 using bus 2 shown in FIG. Reiterating that the preferred embodiment of the present invention uses the second two significant bits of register 48 to select one of the four driver/receiver cards within driver/receiver module 11. I'll keep it. An example of such a driver/receiver card is shown in FIG. However, the lower three device address bits are used by the driver/receiver module 11 to insert into the outbound message to create the eight-pin address by1 mentioned above. .

Signal DXE changes from a low state to a high state when a message is ready for transmission from DCA 9.

Signal DXE enables reception (RE) of module LCM3
Line control module LCM by activating the input
Activate 3. In addition, the signal DXE passes through a delay block 51, an inverter 52, and is ANDed with the undelayed signal DXE by AND gates 1-53 to produce a pulse signal that coincides with the rising edge of the signal DXE. The pulse signal loads address pie 1-56 containing the bits extracted from the lower three digits of register 48 from the bottom surface of shift 1-register 54. In addition, the rising edge of signal DXE sets latch 57 and sets line 58.
change from low state to high state and latch it. This places module LCM4 in transmit mode by activating the transmit enable (XE) input of line control module LCM4. Furthermore, the signal DXE resets the counter 61 to 0 count 1.

When the line control module LCM3 is put into reception mode by the signal DXE, the module LCM3
Begin monitoring line 46 for the start of bit sequence. This beginning sequence is generated by a line control module (not shown) located at DCA 9 and is
line 4 at a rate determined by the clock signal CK on
6” transmit data to the second. When activated by the transmission enable signal on line 58, the line control module L CM
4 begins transmitting an internally generated start sequence through driver/receiver circuit 63 onto T10 line 12. Driver/receiver circuit 63 receives the upper two signals from register 48.
Enabled by the card selection bit.

When module LCM4 finishes generating the 8-bit 1 to start sequence, module LCM4 begins generating a transmit/receive bit clock signal XRBC4 on line 64. Signal XRBC4 is applied to line 44'2 from clock signal CK. Line control module L CM 3 and L
Since CM 4 is driven by the tarock signal on the same line 44 (which clock signal also drives line control module drive line 46), module L CM 3 is activated at the same time that module LCM 4 stops transmitting the beginning sequence. Stop receiving the start sequence. Clock signal X, RBC4, then begins to shift shift 1-register 54 from left to right one bit every tarlock cycle. The data received by module L CM 3 on line 46 is then transferred to line 66 and shifted from the left into register 54 to shift 1. The data sent from the right side of the shift register 54 to shift 1 is sent to module L CM 4.
is transferred to the driver/receiver circuit 63 and sent to the T10 line 12. This causes l10m+2 to carry the start sequence followed by the address byte 56, followed by the information word sent from DCA 9 to driver/receiver module 11 via line 46.

When the DCA 9 has finished transmitting to the driver/receiver module 11, a transmit enable signal (not shown) generated internally in the DCA 9 changes from a high state to a low state. After five clock pulses, the delayed transmit enable signal DXE also changes from a high state to a low state. After this five clock pulse delay, the last three bits of the information word being transmitted occupy the rightmost three bit positions of shift register 54. Additionally, a "0" bit occupies the fourth position from the right of shift 1 to register 54 to indicate the end of transmission according to the signals shown in FIG. Signal DXE, which changes from a high state to a low state, is inverted by an inverter 67, and it is inverted by an AND gate 1-
68 to advance clock signal XRBC4 from line 64 to line 69. Counter 61 is activated to count four pulses on line 69, and at its end on line 71 produces a pulse on line 71. The rising edge of the pulse on line 71 clears latch 57, which disables line control module LCM4 by changing line 58 from a high state to a low state and stops signal X RB C4. The four special clock pulses of XRBC4 provided by counter 61 serve as clocks for sending out the remaining four bits of shift 1 through register 54 from left to right through modules L and CM 4.

When a response message is received on line 12 from the respective output branch box, driver/receiver circuit 63 outputs signals R4 and R.
3 is still active and following the start-of-edge sequence the information word received on line 12 is passed through the driver/receiver circuit 63 to line 72 and the data input signal (DAT
It is returned to DCΔ9 as AI). Note that the response message received by the driver/receiver module 11 does not include the address Pi1~ and takes the form of an information word immediately following the start sequence.

FIG. 4 is a schematic diagram of output branch box 16 shown in FIG. 1, which is representative of output branch boxes 16-19 of FIG.

Data signals are sent from driver/receiver module 11 (FIGS. 1 and 3) to I10 line 12. Driver/receiver circuit 73 receives the signal on line 12 and sends it via line 74 to line control module L CM +. In addition, a tarlock synchronization circuit 76 synchronizes the tarlock signal CKI with the incoming data so that the module LCM+ is also synchronized with the incoming data. Initially, the receive+iJ enable doubling signal 1 is high, placing module 1, CMI, in receive mode and sensing data on line 74.

Line control module LCMI is module L in Figure 3.
Same as CM 3 and L CM 4 and senses line 74 for the 8-bit start sequence when in receive mode. The line control module shown here is equivalent to the C0M9004 manufactured by Standard Micro Systems, and is compatible with IBM's System 3274 Communication Protocol 1-Col. Several events occur simultaneously at the end of the beginning sequence detected by module LCMI. L
CMl issues a busy bit marker signal BBMI pulse. The pulse clears the shift 1~register 77, the first-out buffer FIFO, and the ORage~8
Reset counter 75 via 0.

Additionally, at the end of the start sequence, module LCMl begins transferring data from line 74 to line 78.

In addition, at the end of the detected beginning sequence, the module LCM] transmits/receives the bit clock signal XR.
Start generating BCI. That signal is the clock signal CK
It is derived from I.

Since the data received on line 78 is the same as shown in FIG. 2, the first data appearing on line 78 is an address byte. Register 77 first receives signal BBM.
A "0" appears on line 79 because it is set to all zeros by I. The signal on line 79 is inverted by inverter 81 to satisfy AND gates 1-82, thereby sending the data from line 78 to line 83. The data on line 83 is clocked as determined by signal XRBCI.
It enters the shift register 77 at ray 1-. line 79" second "
0” signal is that the data from line 78 is FIFO on line 86
AND gate 84 acts to prevent entry into the .

At the end of the eight tarok pulses of signal
occupies all 8 bit positions of 7. The busy pin 1- (see Figure 2) of the A1 reply byte is the shift register 7.
7, which takes line 79 from "0" to "1".
”. By disabling AND gate 82 and activating A N D gate 1-84 by this change, data with 71 Helles bytes is transferred from line 78 to ΔN
84 to Dgu 1, via line 86 Clockley 1 to XR
Make it possible to enter FIFO2 with BCI.

The address byte's busy pin I~ is line 79''2.
When changing from the "0" state to the "1" state, the latch 87 is set to generate a "1" and send out the enable signal XE2. Signal XE2 places line control module LCM2 in transmit mode. Module LCM2 begins generating and sending out the beginning sequence on line 88.

Line 88 is connected to multiplexer MUX.

The multiplexer MUX outputs address pins 1-At,
Controlled by A2 and A4. multiplexer MUX
transfers data from lines 88 to driver/receiver circuits D/RO to D/R depending on the value of address pitches hA1, A2, A4.
Transfer to 7. For example, if A1. A2 and A4 are 000
If , D/RO is selected; if 111, D/R7 is selected.

At the end of the 8-bit time for generation and transmission of the beginning sequence, module L CM 2 begins to generate a transmit/receive bit clock signal XRBC2 derived from clock signal CK2. Signal XRBC2 retrieves data from buffer FIFOI onto line 94 to
It begins sending out on line 88 via 2.

Buffers PIFOL and FIFO2 are both first-in, first-out 16-bit buffers, and the data is stored at the first rate C.
It is clocked in at KI and clocked out at second ray 1-CKO. buffer FIFO
I and FIFO2 may be, for example, 74S225 type TTL integrated circuits. When module LCM2 generates and sends out an 8-bit start sequence, module LCM1 transfers the data to buffer FIF at clock rate XRBCI.
Send to OI. When module LCM2 finishes sending out the start sequence, module LCM2 sends the data to data buffer F at clock rays 1 to XRBC2.
1. Start taking out from FO1.

Module LCM2 generates delayed transmit enable signal DXE2 substantially simultaneously with the provision of transmit enable signal XE2 from latch 87. Signal DXE2 is signal XRBC
2 to the AND game 1-96, and the signal XRBC
2 to ORAge via 97 to line 98. line 98
The falling edge of the first pulse of the upper signal XRBC2 sets latch 99, which in turn satisfies AND gate 101. This causes all pulses of clock signal XRBC2 except the very early pulses to appear on line 102 following the "0" to "1" transition of signal DXE2.

Counter 75 generates a transition from a low state to a high state on transition line 103 counting twelve pulses on line 102. The pulse on line 103 is bit position #1 of the information word.
3 (see FIG. 2) and appears at the last bit position FIL of buffer PIFOI. If bit position #13 is rlJ and indicates that another information word follows, the signal FIL becomes "1" and the output of the inverter 104 becomes "0", causing the AND gate to 106 and prevents the pulse from going to line 107. The next pulse on line 102 is then counter 75
is a count of "0", and the line 103 is set to 0.
level and a new count of 12 is started. However, if bit position #13 is "0", the signal FIL becomes "0" and the inverter 10
The output of 4 is "1". This satisfies AND gate 106 and clears latch 87 by allowing the pulse appearing on line 103 to proceed to line 107. Clearing latch 87 causes signal XE2 to change from a high state to a low state and causes signal RE2 to change from a low state to a high state.

This transition of latch 87 places line control module LCM2 in receive mode and module L, CM2 begins monitoring line 108 for a start sequence. In addition, placing the module LCM2 in receive mode stops the clock signal XRBC,2, thereby interrupting the flow of pulses towards the counter 75. This results in line 10
3 on high.

As a result of the operations described above, the fan-out box shown in FIG. and decode the stripped address byte using MUX,
The message was directed to the correct output port (eg line 21) according to the decoded address byte. At the end of this operation, module LCM2 is in receive mode, as described above, and monitors line 108 for the beginning sequence.

If the addressed display terminal (e.g., terminal 26 in FIG. 1) sends a response message on, e.g. It takes the form of an information word followed by an information word. The response message will come from the same terminal from which the original message was sent. This is because shift 1 register 77 still has the address Nosui I~ associated with the original message. Address by 1 - Al, A2, A4 still control multiplexer M U IX, the latter on line 108
Line control module 1. , connect to CM 2.

When the start sequence appears on line 108, J:, the clock synchronization circuit 109 accomplishes a similar function to the synchronization circuit 76 to synchronize the tarlock signal CK2 with the incoming data, and the module LCM2 also synchronizes with the incoming data. I'll do what I do. After receiving the start sequence, module L
CM 2 detects the busy beep I~ as the first beep I- of the incoming information word.

When a busy beep I~ is detected by the internal operation of the module L CM2, it starts the clock signal X, R13C2, and outputs the busy beep I~ marker signal I3B
Generate M2 pulse. Signal B I3 M 2 outputs launch 111 . Latch 111 causes the transmit enable signal XEI to change from a low state to a high state and causes the receive enable signal RE+ to change from a high state to a low state. This transition of latch] 11 is module L, CM 1
put it in transmit mode. In addition, pulse signal B B M
2 clears the counter 75 and also clears the latch 99 via the OR game I~80. Furthermore, at the end of the detected start sequence, module 1-1-4
C begins transferring data from line 108 to line 11:2.

Tarock signal XRBC2 is then on line 11.2-, ,I
The data (information word of the response message) is transferred to - and put into the buffer FIF○2.

When line control module LCM l is placed in transmit mode by latch 111, module LCMI
13 and sends it to coaxial cable 12 via driver/receiver circuit 73. At the end of the beginning sequence occurrence,
The module LCM starts generating the tarok signal XRBCI.

Signal
CM 1. , driver/receiver circuit 73, and coaxial cable 12. In addition, the signal XRBCl is supplied to the AANDs 1-116 along with the signal DXE1. The signal DXE] is supplied to the module LCM1 substantially simultaneously with the supply of the signal XEI and changes from a low state to a high state under control of the module LCM1. At that time, the AND gate 116, the OR data 1-9, the latch 99 and the AND gate 1-1, O] are connected to the first non-pulsed tarok on the line 10 (5>;
Generate R13C1. Again, counter 75 cycles through 12 pulses, and at time point 1-#-J', line 103 changes from a low state to a high state. At this point, the last position F 2 L of the buffer F I F O2 is checked by the inverter 117 and the AN1 gate 118. If Pi1-Position F2L is "1", AND game i~]18 is not satisfied and line 11
The absence of a pulse on 9 keeps latch 11 in its current state.

However, if pin 1 ~ position F 2 L is ``0'', indicating that it is the last information word of the message, then A N D go 1 ~ 118 is satisfied and line 119 is set to low. from the high state to the high state, thereby causing the latch 111 to
Clear and change the belief XEI from the high state to the low state, believe: ? , changes E I from a low state to a high state. This transition of Latch 11 places line control module LCMI in receive mode, waiting for further transmissions via coax Kelp 12 from the rest of the system.

-4- Due to the operation described above, the output branch box shown in Figure 4 is line 21.
It receives the response message above and sends it on line 12 following the beginning sequence.

At the end of this operation, module LCM+ goes into receive mode and monitors line 74 for the beginning sequence.

The circuits shown in FIGS. 3 and 4 may be modified without departing from the invention. For example FIFOI and FIFO2
may be replaced by a shift register or other equivalent device.

〔Effect of the invention〕

Since only a single cable is required between device control adapters, cable costs are reduced compared to conventional systems that require multiple cables. The amount of cost reduction becomes significant as the distance between terminals increases.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an information processing system according to the present invention, and FIG.
3 is a schematic diagram of the display cluster adapter and driver/receiver module of FIG. 1; and FIG. 4 is a schematic diagram of the output branch box of FIG. 1. 1...Central processor, 2...I10 bus, 3
... Local host adapter, 4 ... Local CPU, 6 ... Communication line, 7 ... Modem,
8...Communication adapter, 9...Display cluster adapter (DCA), 11...Driver/receiver module, 12-15...Transmission link (coaxial cable)
, 16-19... Output branch box (FOR). Applicant International Business Machines
Corporation Sub-Agent Patent Attorney Shino 1) Written by Yu F/6/F/62 1, - 阜δ te Continued from page 1 @ Inventor Chris Karapatos Aeo Inventor Lawrence Jednier Morjad Co., Ltd. Inventor Richard March - Anne Morrison - Box 5, Kixton, New York, USA
3, R.D. 1, Rhinebeck, New York, USA 412 Birchula Dora, Lake Cudlin, New York, USA
251 O Box

Claims (1)

[Claims] Transmitting device (9) for transmitting a digital message
and terminal equipment for receiving digital messages (
26) for creating a terminal address byte for each outbound message and inserting the address byte into each outbound message; means disposed within a transmitting device; at least one transmission means (12) connected at one end to the transmitting device for conveying said message; and decoding said terminal address byte inserted in the received message. and means for directing the received message to the terminal according to the decrypted address; A remote control output branching device comprising means for stripping the inserted address byte from a received message.