JPH0721077A - Storage lock system - Google Patents

Abstract

PURPOSE:To accelerate a lock operation by judging whether or not an address to which an access request is issued belongs to a lock area without referring to the cache directory of the other device. CONSTITUTION:When the access request is issued, an access request address is inputted through a line 201 to comparator circuits 213, 214, 223, and 224. Compare enable signals 203 of comparator circuits 214, 223, and 224 corresponding to other access origin devices 105-107 are turned on, and the contents of registers 212, 221, and 222 for lock address storage are compared with the access request address from an access origin device 104, so that whether or not the other access origin devices 105-107 lock the pertinent address can be judged. When the address is matched in any comparator circuit, and the valid flag of the register for lock address storage is connected, '1' is outputted from the comparator circuit, and an access inhibiting signal 205 is outputted through an OR circuit 204.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device lock mechanism shared by a plurality of access source devices (arithmetic processing units, input / output processing units, etc.). In a system in which a plurality of access source devices share a main memory and operate independently, while one access source device accesses a part of the main memory, another part of the main memory accesses another part of the main memory. It is necessary to prohibit access from the access source device. This is called a lock, and the prohibited main memory area is called a lock area. One of the conventional locking methods is disclosed in Japanese Patent Laid-Open No. 57-
There is No. 158081 "Cache control method in multiprocessor system". This is to prepare a lock bit for each entry of the cache directory of each access source device, and lock the area on the main memory indicated by the address in the entry by turning on the lock bit. is there. However, this system is not without the following room for improvement. That is, (1) When an access request for main memory is generated in a certain access source device, the cache memory of all other access source devices is used to determine whether the requested address is locked by another access source device. It is necessary to search the directory, which increases the busy rate of the cache directory of each access source device.
(2) The turnaround becomes large because the main memory access request cannot be processed until the cache directories of all the other access source devices are searched and it is confirmed that they are not locked. Even if a method of providing a register for storing a lock address in each access source device is adopted as a method of locking the area on the main memory, the turnaround becomes large as described above. Further, even when the lock address holding means corresponding to the access source device connected to the storage control device is provided in the storage control device, in a system having a plurality of storage control devices, the same as above. The problem arises. Japanese Laid-Open Patent Publication No. 55-108069 discloses a storage lock system in which each access source device is provided with means for holding a copy of an address locked by all other access source devices. According to this method, even if the above problem is solved, in a large-scale system having a plurality of storage control devices, the amount of hardware will increase enormously. Further, there is a case where a lock by a certain access source device and an access request from another access source device conflict with each other. Therefore, it is necessary to take measures against it. As described above, the object of the present invention is that the busy rate of the cache directory of another access source device does not increase and the turn around does not increase, and the amount of hardware increase is small. Another object of the present invention is to provide a memory lock means which has resolved the conflict between the lock and the access request. A feature of the present invention is that each of a plurality of storage control devices to which a group of access source devices is connected, is connected to another storage control device. Means for holding a copy of the information indicating the lock address storage-locked by the access source device, and means for communicating with each of the other storage control devices to exchange the copy of the information indicating the lock address And, if it is found from the contents of the holding means that the request address of the storage access request from the access source device connected to the storage control device is locked, means for rejecting the access request, and further, A request for registration in the holding means of a copy of the information indicating the lock address from another storage controller,
Means for preferentially accepting an access request from an access source device connected to the storage control device is provided. According to the above characteristics, the lock determination is performed inside each storage control device, and it is necessary to directly access the information indicating the lock address registered in another access source device or another storage control device. Moreover, it requires a much smaller amount of hardware (registers and their control circuits, comparators, inter-device signal lines, etc.) than each access source device has a copy of the information indicating the lock address. Achieved by addition. Further, the effect of the lock which is being executed in a certain storage control device by the priority acceptance means is
This is surely reflected in the determination as to whether or not the access request can be made in another storage control device that conflicts with it. An embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a system configuration diagram of an embodiment of the present invention. In the figure, 101 is a main memory (hereinafter referred to as M
S is abbreviated as S), 102 and 103 are storage control devices (hereinafter abbreviated as SC), and 104 to 107 are access source devices (central processing unit or input / output processing device), 12
Reference numerals 1 and 131 are cache memories (abbreviated as BS below), and 122 and 132 are cache directories (abbreviated as BAA below). 123 and 133 are each SC1
A lock address storing register group corresponding to the access source device connected to 02 and 103, and the contents of the register group and the access request address to the MS sent from the access source device connected to each SC are compared. A lock determination unit (hereinafter abbreviated as LKA) having a comparison circuit for Reference numeral 124 is added according to the present invention.
The register group for storing a copy of the lock address registered in the LKA 133 and the contents of the register group are set to SC1.
A lock determination unit (hereinafter, abbreviated as FLKA) having a comparison circuit for comparing with an access request address to the MS sent from the access source devices 104 and 105 connected to 02, and 134 also has a copy of LKA 123. FLK
A and 125 and 135 are priority logics that determine the processing priority order between the request generated in the access source device connected to each SC and the request from the other SC. FIG. 2 is a diagram showing LKA123 and FLKA124 in detail, but LKA133 and FLKA134.
Is also the same. 201 is the priority logic 12 of FIG.
5 is an access request address line of the request selected in 5, and 202 is a control line of the lock address storage register when the request selected by the priority logic 125 is a lock set request or a reset request , 203 are compare enable lines for controlling whether or not to compare the access request address of the request selected by the priority logic 125 and the contents registered in the lock address storage register. 211 and 212 in the LKA 123 are shown in FIG.
The lock address storing registers corresponding to the access source devices 104 and 105, which are composed of a lock address portion and a valid flag portion. Reference numerals 213 and 214 are comparison circuits. F
Like the LKA 123, the LKA 124 also includes address storage registers 221 and 222 and comparison circuits 223 and 224. In the address storage registers 221, 222,
The same information as the information stored in the LKA 133 in the SC 103 of FIG. 1 is stored as a copy. (Instead of setting LKA and registering lock address,
The present invention can be applied to a system having a lock bit for each entry of the directory, but in that case, the FLKA registration data and control method are not changed. Now, for example, in the access source device 104, when a write access request is made to a certain address on the main memory, and when the request is selected by the priority logic 125, the access request address changes to the line 201. Through comparison circuits 213, 214, 223, 2
24 is input. Since no control (set or reset) is required for the lock address storage register, the signal on the control line 202 is turned off. In order to determine whether or not the other access source devices 105 to 107 lock the requested address, the compare enable signals 203 of the comparison circuits 214, 223 and 224 corresponding to the other access source devices are turned on, The contents of the lock address storage registers 212, 221, 222 are compared with the access request address from the access source device 104. (Do not compare with your own lock address,
Send a mismatch signal. If the addresses match in any of the comparison circuits and the valid flag of the lock address storage register there is set, "1" is output from the comparison circuit. Reference numeral 204 is an OR circuit, which takes the logical sum of the outputs from the respective comparison circuits and outputs an output signal 205. If the output signal 205 is "1", the access request from the access source device 104 is for the lock area of any other access source device.
The output signal 205 suppresses the search for the BAA 122,
Access to BS 121 or MS 101 is not allowed. FLK will now be described with reference to FIGS. 1, 2 and 3.
A control method of A123 and A124 will be described. Figure 3 shows F
It is a figure which shows the registration data of the lock address storage register of LKA (for example, 124), and the generation mechanism of a set signal. In FIG. 1, when the access source device 106 issues a lock set request to the SC 103 and is selected by the priority logic 135, the lock address storage corresponding to the access source device 106 in the LKA 133 is stored in the SC 103. Register is set, and FLKA12 is sent from SC103 to SC102.
A request is made to register in a register that stores a copy of the lock address in 4. FLKA registration request is SC103
From the SC102 to the SC102, the FLKA registration request is suppressed from being sent from the SC102 to the SC103, and the instruction execution order is guaranteed. In the priority logic 125 of SC102, FL from SC103
The KA registration request is accepted with the highest priority. This allows
The effect of the lock that is already being executed in one SC can be reliably reflected in the processing of the access request in the other SC. A lock address storage register (for example, 22) corresponding to the access source device 106 of the FLKA 124.
1) is, as shown in FIG.
And a valid flag section (valid flag 311 and parity 312 of the valid flag). If the request received by the priority logic 125 is a registration request of the lock address storage register corresponding to the access source device 106 in the FLKA 124, the set request signal 303 becomes “1”. At this time, FLKA control reset signal 30
If 4 is "0", the registration request address to FLKA 2
01 is selected by the select circuit 302 and input to the address portion of the lock address storage register. In the valid flag portion, “1” is input to the valid flag 311 and “0” is input to the parity 312 via the AND circuit 308 (this embodiment assumes odd parity). At this time, since the set request signal 303 is "1", the set signals of the address section and the valid flag section are generated via the OR circuits 307 and 309, and the input data is stored. When the access source device 106 issues a lock reset request to the SC 103 and is selected by the priority logic 135, the lock address storage register corresponding to the access source device 106 in the LKA 133 is reset, and F of SC103 to SC102
A reset request is issued to the LKA 124. SC10
If the request selected by the priority logic 125 of No. 2 is the reset request of the lock address storing register corresponding to the access source device 106 in the FLKA 124, the reset request signal 305 becomes “1”. At this time, since the set request signal 303 does not become "1" at the same time, "0" is set to the valid flag 311 of the valid flag part of the lock address storage register, and the parity 312 is set.
"1" is input to. At that time, reset request signal 3
Since 05 is "1", the set signal of the valid flag portion is generated via the OR circuits 306 and 309, and the input data is stored. Address part 31 when the lock is reset
The initial data 301 may be selected and stored by the select circuit 302 to 0, but in FIG. 3, the address set in the address part is held as it is and only the valid flag is reset. When a control logic reset (control reset) signal to the access source device 106 is issued, the FLKA lock address storage register corresponding to the access source device is reset, so that the FL address is reset.
KA has a control reset signal 304. When the control reset signal 304 becomes “1”, even if the request for registration to FLKA is selected by the priority logic 125 at that time,
The selection circuit 302 selects the initial data 301 and inputs it to the address section 310. AN to valid flag 311
The D circuit 308 generates and inputs "0" to guarantee its parity, and a set signal is generated via the OR circuits 307, 306 and 309 to set the input data. Initial data 3 is sent to address part 310 by control reset
Storing 01 is effective to guarantee the parity when the address and the parity thereof are registered in the address portion because the parity of the address portion is not guaranteed at the time of power-on. In this embodiment, the LKA in one SC is
Although the method of setting FLKA in the other SC each time is set, BS1 is set when the access source device 106 issues a lock set request.
21 that the lock area does not exist SC103
If you have the information that can be determined by, the LK in SC103
Register only in A133 and BS121 in SC102
When an access request is received for an area that does not exist, the LKA 133 of the SC 103 is searched, and if the area is locked, the address registered in the LKA 133 may be reregistered in the FLKA 124. According to the present invention, in determining whether or not the address for which an access request is made belongs to the lock area, the cache directory or the lock directory of another device is locked.
Since it is not necessary to refer to the address register group, the lock operation will be faster, and there will be no annoyance such as increasing the busy rate of the cache directory of other devices, so it is expected to speed up the entire system. it can. Moreover, the increase in the amount of hardware such as registers and their control circuits, comparators, and signal lines between devices is small compared to the case where a holding means for holding a copy of the lock address information is provided for each access source device. . Further, A priority circuit that receives a lock address registration request from another storage control device with priority over an access request from the access source device connected to this storage control device, The effect can be surely reflected in the processing of the access request in the other storage control device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. [Fig. 2] Lock address storage register group, lock
A block diagram showing a register group that stores a copy of an address and their peripheral circuits. FIG. 3 is a block diagram showing details of a register for storing a copy of a lock address and its peripheral circuits. [Description of Reference Signs] 101: main storage device 102, 103: storage control devices 104 to 107: access source device 123, 133: lock determination unit 124 regarding an address locked by the access source device connected to this storage control device, 134: Lock determination units 125 and 135 related to addresses locked by an access source device connected to another storage control device: An access source connected to this storage control device for a lock / address registration request from another storage control device Priority circuit that prioritizes access requests from devices

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Makoto Kishi             1 Horiyamashita, Hadano City, Kanagawa Japan             Tate Manufacturing Kanagawa Factory (72) Inventor Toshihisa Matsuo             1 Horiyamashita, Hadano City, Kanagawa Japan             Tate Manufacturing Kanagawa Factory

Claims (1)

[Claims] 1. A storage device and a plurality of access source devices are connected to the storage device, respectively, and are connected to at least one of the plurality of access source devices, and store access requests from the access source devices connected thereto. In a data processing device having a plurality of storage control devices for processing, each of the plurality of storage control devices stores information indicating a lock address storage locked by an access source device connected to each of the other storage control devices. A means for holding a copy, a means for communicating with each of the other storage control devices to send and receive a copy of the information indicating the lock address, and an access source device connected to the storage control device makes an access request. A copy of the information indicating the lock address held in the holding means that the specified address is locked. In response to represent,
A means for rejecting the access request and a registration request from another storage control device requesting registration of a copy of the information indicating the lock address in the holding means are sent from the access source device connected to the storage control device. And a means for accepting the access request in priority to the storage lock method.